Power Management

SL40307A-R19KHF

International Rectifier

Single-Input Voltage, Synchronous Buck Regulator

Manufacturer: International Rectifier

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FEATURES

 Single 5V to 21V application  Wide Input Voltage Range from 1.5V to 21V with external Vcc  Output Voltage Range: 0.6V to 0.86*PVin  0.5% accurate Reference Voltage  Enhanced line/load regulation with Feed-Forward  Programmable Switching Frequency up to 1.5MHz  Internal Digital Soft-Start  Enable input with Voltage Monitoring Capability  Remote Sense Amplifier with True Differential Voltage Sensing  Thermally compensated current limit and Hiccup Mode Over Current Protection  Smart LDO to enhance efficiency  Vp for tracking applications and sequencing  Vref is available externally to enable margining  External synchronization with Smooth Clocking  Dedicated output voltage sensing for power good indication and overvoltage protection which remains active even when Enable is low.  Enhanced Pre-Bias Start up  Body Braking to improve transient  Integrated MOSFET driv ers and Bootstrap diode  Thermal Shut Down  Post Package trimmed rising edge dead-time  Programmable Power Good Output with tracking  Small Size 5mm x 7mm PQFN  Operating Junction Temp: -40 oC<Tj<125oC  Lead-free, Halogen-free and RoHS Compliant

DESCRIPTION

The IR3846 Sup IRBuck® is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3846 a space-efficient solution, providing accurate power delivery for low output voltage and high current applications. IR3846 is a versatile regulator which offers programmability of switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 300 kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Over Voltage Protection (OVP), Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions.

APPLICATIONS

 Netcom Applications  Embedded Telecom Systems  Server Application  Distributed Point of Load Power Architectures  Storage Applications

ORDERING INFORMATION

Standard Pack Orderable Part Number Form Quantity IR3846 PQFN 5mm x 7mm Tape and Reel 750 IR3846MTR1PBF IR3846 PQFN 5mm x 7mm Tape and Reel 4000 IR3846MTRPBF

1 PVin

Input voltage for power stage. Bypass capacitors between PVin and PGND should be connected very close to this pin and PGND; also forms input to feedforward block 2, 3, 22, 23, 26 NC No Connect

4 Boot Supply voltage for high side driver

5 Enable Enable pin to turning on and off the IC.

6 Rt/Sync

Use an external resistor from this pin to LGND to set the switching frequency, very close to the pin. This pin can also be used for external synchronization.

7 OCset

Current limit setpoint. This pin allows the trip point to be set to one of three possible settings by either floating this pin, tying it to VCC or tying it to PGnd.

8 Vsns Sense pin for OVP and PGood

Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. 10 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation.

11 RSo Remote Sense Amplifier Output

12, 25 PGND Power ground. This pin should be connected to the system’s power ground plane. Bypass capacitors between PVin and PGND should be connected very close to PVIN pin (pin 1) and this pin. 13 LGND Signal ground for internal reference and control circuitry.

14 S_Ctrl

Soft start/stop control. A high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. Pull this pin high if this function is not used. 15 RS- Remote Sense Amplifier input. Connect to ground at the load. 16 RS+ Remote Sense Amplifier input. Connect to output at the load.

17 Vref

External reference voltage can be used for margining operation. A capacitor between 100pF and 180pF should be connected between this pin and LGnd. Tie to LGnd for tracking function. 18 Vp Used for voltage sequencing and tracking. Leave open if sequencing or tracking is not needed, ensuring that there is no capacitor on the pin. 19 PGD Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC. 20 Vin Input Voltage for LDO. 21 VCC/LDO_out Bias Voltage for IC and driver section, output of LDO. Add a minimum of 4.7uF bypass cap from this pin to PGnd. 24 SW Switch node. This pin is connected to the output inductor.

5 www.irf.com © 2013 International Rectifier August 01, 2013 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin -0.3V to 25V Vin -0.3V to 25V VCC -0.3V to 8V (Note 1) SW -0.3V to 25V (DC), -4V to 25V (AC, 100ns) BOOT -0.3V to 33V BOOT to SW -0.3V to VCC + 0.3V (Note 2) Input/Output pins -0.3V to 3.9V RS+, RS-, RSo, PGD, Enable, OCset, S_Ctrl -0.3V to 8V (Note 1) PGND to LGND, RS- to LGND -0.3V to + 0.3V Junction Temperature Range -40°C to 150°C Storage Temperature Range -55°C to 150°C ESD Machine Model Class A Human Body Model Class 1C Charged Device Model Class III Moisture Sensitivity level JEDEC Level 3 @ 260°C RoHS Compliant Yes Note: 1. VCC must not exceed 7.5V for Junc tion Temperature between -10°C and -40°C. 2. Must not exceed 8V. THERMAL INFORMATION Thermal Resistance, Junction to Case (θJC_TOP) 30 °C/W Thermal Resistance, Junction to PCB (θJB) 2.71 °C/W Thermal Resistance, Junction to Ambient (θJA) (Note 3) 14.3 °C/W Note: 3. Thermal resistance ( θJA) is measured with components mounted on a high effective thermal conductivity test board in free air.

6 www.irf.com © 2013 International Rectifier April 29, 2013 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL DEFINITION MIN MAX UNIT PVin Input Bus Voltage * 1.5 21 V Vin Supply Voltage 5.0 21 VCC Supply Voltage ** 4.5 7.5 Boot to SW Supply Voltage 4.5 7.5 VO Output Voltage 0.6 0.86 PVin IO Output Current 0 ±35 A Fs Switching Frequency 300 1500 kHz TJ Junction Temperature -40 125 °C * SW node must not exceed 25V ** When VCC is connected to an externally regulated supply, also connect Vin.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0oC < TJ < 125oC. Typical values are specified at TA = 25oC. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power Loss Power Loss PLOSS Vin = PVin = 12V, VO = 1.2V, IO = 35A, Fs = 600kHz, L=0.250uH, TA = 25°C, Note 4 5.3 W MOSFET Rds(on) Top Switch Rds(on)_Top VBoot – VSW = 6.8V, ID = 35A, Without Cu Clip, Tj = 25°C 3.1 4 mΩ Bottom Switch Rds(on)_Bot VCC =6.8V, ID = 35A, With Cu Clip, Tj = 25°C 1.27 1.64 Reference Voltage Feedback Voltage VFB 0.6 V Accuracy Vref=0.6V, Vref=0.6V, Sink Current Isink_Vref Vref=0.7V 12.7 16.0 19.3 µA Source Current Isrc_Vref Vref=0.5V 12.7 16.0 19.3 Vref Comparator Threshold Vref_disable Vref Pin connected externally 0.15 V Vref_enable 0.4 V

7 www.irf.com © 2013 International Rectifier August 01, 2013 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Supply Current Vin Supply Current (Standby) Iin(Standby) Vin=21V, Enable low, No Switching 300 425 µA Vin Supply Current (Dyn) Iin(Dyn) Vin=21V, Enable high, Fs = 600kHz 40 mA VCC Supply Current (Standby) Icc(Standby) Enable low, VCC=7V, No Switching 300 425 µA VCC Supply Current (Dyn) Icc(Dyn) Enable high, VCC=7V, Fs = 600kHz 40 mA Under Voltage Lockout VCC–Start–Threshold VCC_UVLO_Start VCC Rising Trip Level 4.0 4.2 4.4 V VCC–Stop–Threshold VCC_UVLO_Stop V CC Falling Trip Level 3.7 3.9 4.2 Enable–Start–Threshold Enabl e_UVLO_Start Supply ramping up 1.14 1.2 1.36 V Enable–Stop–Threshold Enable_UVLO_Sto p Supply ramping down 0.9 1.0 1.06 Enable leakage current Ien Enable=3.3V 1 µA Oscillator Rt Voltage 1 V Frequency Range F S Rt=80.6k 270 300 330 kHz Rt=39.2k 540 600 660 Rt=15k 1350 1500 1650 Ramp Amplitude Vramp PVin=6.8V, PVin(max) slew rate=1V/us, Note 4 1.02 Vp-p PVin=12V, PVin(max) slew rate=1V/us, Note 4 1.8 PVin=16V, PVin(max) slew rate=1V/us, Note 4 2.4 Ramp Offset Ramp (os) Note 4 0.16 V Min Pulse Width Tmin (ctrl) Note 4 50 ns Fixed Off Time Note 4 200 230 ns Max Duty Cycle Dmax Fs=300kHz, PVin=Vin=12V 86 % Sync Frequency Range Note 4 270 1650 kHz Sync Pulse Duration 100 200 ns Sync Level Threshold High 3 V Low 0.6

8 www.irf.com © 2013 International Rectifier August 01, 2013 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Error Amplifier Input Offset Voltage Vos_Vref VFb – Vref, Vref = 0.6V -1.5 +1.5 % Vref Vos_Vp VFb – Vp, Vp = 0.6V -1.5 +1.5 %Vp Input Bias Current IFb(E/A) -0.5 +0.5 µA Input Bias Current IVp(E/A) 0 4 µA Sink Current Isink(E/A) 0.4 0.85 1.2 mA Source Current Isource(E/A) 4 7.5 11 mA Slew Rate SR Note 4 7 12 20 V/µs Gain-Bandwidth Product GBWP Note 4 20 30 40 MHz DC Gain Gain Note 4 100 110 120 dB Maximum Output Voltage Vmax(E/A) 1.7 2 2.3 V Minimum Output Voltage Vmin(E/A) 100 mV Common Mode Voltage Vcm_Vp Note 4 0 1.2 V Margining Range Vmarg_Vref Note 4 0.4 1.2 V Remote Sense Differential Amplifier Unity Gain Bandwidth BW_RS Note 4 3 6.4 9 MHz DC Gain Gain_RS Note 4 110 dB Offset Voltage Offset_RS Vref=0.6V, 0°C < Tj < 85°C -1.5 0 1.5 mV Vref=0.6V, -40°C < Tj < 125°C -2 2 mV Source Current Isource_RS 3 13 20 mA Sink Current Isink_RS 0.4 1 2 mA Slew Rate Slew_RS Note 4, Cload = 100pF 2 4 8 V/µs RS+ input impedance Rin_RS+ 45 63 85 kohm RS- input impedance Rin_RS- Note 4 63 kohm Maximum Voltage Vmax_RS V(VCC) – V(RSo) 0.5 1 1.5 V Minimum Voltage Min_RS 50 mV Internal Digital Soft Start Soft Start Clock Clk_SS Note 4 180 200 220 kHz Soft Start Ramp Rate Ramp(SS_Start) Note 4 0.3 0.4 0.5 mV / µs S_CTRL Threshold High 2.4 V Low 0.6 V Bootstrap Diode Forward Voltage I(Boot) = 30mA 360 520 960 mV

9 www.irf.com © 2013 International Rectifier August 01, 2013 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Switch Node SW Leakage Current lsw SW = 0V, Enable = 0V 1 µA SW = 0V, Enable = HIGH, Vp=0 V Internal Regulator (VCC/LDO) Output Voltage VCC Vin(min) = 7.2V, Io=0- 30mA, Cload = 2.2uF, DCM=0 6.3 6.8 7.1 V Vin(min) = 7.2V, Io=0- 30mA, Cload = 2.2uF, DCM=1 4 4.4 4.8 VCC dropout VCC_drop Vin = 7V, Io=70 mA, Cload = 2.2uF 0.7 V Short Circuit Current Ishort Note 4 70 mA Zero-crossing Comparator Delay Tdly_zc 256 / Fs s Zero-crossing Comparator Offset Vos_zc Note 4 0 mV Body Braking BB Threshold BB_threshold Fb > Vref, Sw duty cycle, Note 3 0 % FAULTS Power Good Power Good Low Upper Threshold VPG_low(upper) Vsns Rising, 0.4V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp Power Good Low Upper Threshold Falling delay VPG_low(upper)_Dly Vsns > VPG_low(upper) 1.5 2.5 3.5 µs Power Good High Lower Threshold VPG_high(lower) Vsns Rising, 0.4V < Vref < 1.2V 95 % Vref Vsns Rising, Vref < 0.1V 95 % Vp Power Good High Lower Threshold Rising Delay VPG_high(lower)_Dly Vsns rising 1.28 ms Power Good Low Lower Threshold VPG_low(lower) Vsns falling, 0.4V < Vref < 1.2V 90 % Vref Vsns falling, 0.1V < Vref 90 %Vp Power Good Low Lower Threshold Falling delay VPG_low(lower)_Dly Vsns < VPG_low(lower) 101 150 199 µs PGood Voltage Low PG (voltage) I PGood = -5mA 0.5 V

10 www.irf.com © 2013 International Rectifier August 01, 2013 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Tracker Comparator Upper Threshold VPG(tracker_upper) Vp Rising, Vref < 0.1V 0.4 V Tracker Comparator Lower Threshold VPG(tracker_lower) Vp Falling, Vref < 0.1V 0.3 V Tracker Comparator Delay Tdelay(tracker) Vp Rising, Vref < 0.1V 1.28 ms Over Voltage Protection (OVP) OVP Trip Threshold OVP (trip) Vsns Rising, 0.45V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp OVP Fault Prop Delay OVP (delay) Vsns rising 1.5 2.5 3.5 µs Over-Current Protection OC Trip Current I TRIP OCSet=VCC, VCC = 6.8V, TJ = 25°C 41 44.4 48 A OCSet=floating, VCC = 6.8V, TJ = 25°C 32 35 38 A OCSet=PGnd, VCC =6.8V, TJ = 25°C 24 26.88 30 A Hiccup blanking time Tblk_Hiccup Note 4 20.48 ms Thermal Shutdown Thermal Shutdown Note 4 145 °C Hysteresis Note 4 20 °C Notes: 4. Guaranteed by design but not tested in production.

11 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = 12V, VCC = Internal LDO, Io=0-35A, Fs= 60 0kHz, Room Temperature, LFM=200. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (mΩ) 1.2 0.25 744309025 (Wurth Electronik) 0.165 1.8 0.33 744309033 (Wurth Electronik) 0.165 3.3 0.33 744309033 (Wurth Electronik) 0.165 5.0 0.33 744309033 (Wurth Electronik) 0.165

12 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vin = VCC = 5V, Io=0-35A, Fs= 600kHz, Room Te mperature, LFM=200. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (mΩ) 1.2 0.25 744309025 (Wurth Electronik) 0.165 1.8 0.33 744309033 (Wurth Electronik) 0.165 3.3 0.33 744309033 (Wurth Electronik) 0.165 5.0 0.33 744309033 (Wurth Electronik) 0.165

13 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = VCC = 5V, Io=0-25A, Fs= 600kHz, Room Temp erature, LFM=200. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (mΩ) 1.0 0.19 SL40307A-R19KHF (ITG) 0.200 1.2 0.19 SL40307A-R19KHF (ITG) 0.200

17 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C) OCset=VCC OCset=Float OCset=GND OCset=VCC OCset=Float OCset=GND OCset=VCC OCset=Float OCset=GND

19 www.irf.com © 2013 International Rectifier August 01, 2013 Vcc PVin=Vin Intl_SS EN > 1.2V Vp > 1.0V Vo Figure 5: Recommended startup for Normal operation Vcc PVin=Vin Intl_SS EN > 1.2V Vp Vo Figure 6: Recommended startup for sequencing operation (ratiometric or simultaneous) Vcc PVin=Vin Vp VDDQ Vref 0V Vo EN > 1.2V VDDQ/2 VTT Tracking Figure 7: Recommended startup for memory tracking operation (Vtt-DDR) Figure 5 shows the recommended startup sequence for the normal (non-tracking, non-sequencing) operation of IR3846, when Enable is used as a logic input. In this operating mode Vref is left floating. Figure 6 shows the recommended startup sequence for sequenced operation of IR3846 with Enable used as logic input. Figure 7 shows the recommended startup sequence for tracking operation of IR3846 with Enable used as logic input. For this mode of operation, Vref should be connected to LGND. PRE-BIAS STARTUP IR3846 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for cont rol MOSFET (Ctrl FET) is generated. Figure 8 shows a typical Pre-Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 9 shows the series of 16x8 startup pulses. Vo[V] [Time] Pre-Bias Voltage Figure 8: Pre-Bias startup

16 End of

12.5% 25% 87.5% 16 ... ... ... ... Figure 9: Pre-Bias startup pulses SOFT-START IR3846 has an internal digital soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and VCC rise

20 www.irf.com © 2013 International Rectifier August 01, 2013 above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft-start (Intl_SS) signal linearly rises with the rate of 0.4mV/µs from 0V to 1.5V. Figure 10 shows the waveforms during soft start. The normal Vout startup time is fixed, and is equal to:  mSSmV VVTstart 5.1/4.0 15.075.0   (1) During the soft start the over-current protection (OCP) and over-voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. POR Intl_SS Vout 0.15V 0.75V t1 t2 t3 1.5V 3.0V Figure 10: Theoretical operation waveforms during soft-start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between 300kHz – 1500kHz by connecti ng an external resistor from R t pin to LGnd. Table 1 tabulates the oscillator frequency versus Rt. Table 1: Switching Frequency(Fs) vs. External Resistor(Rt) Rt (KΩ) Freq (KHz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 SHUTDOWN IR3846 can be shutdown by pulling the Enable pin below its 1.0V threshold. During shutdown the high side and the low side drivers are turned off. OVER CURRENT PROTECTION The Over Current (OC) protection is performed by sensing the inductor current through the R DS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The Over Current (OC) limit can be set to one of three possible settings by floating the OCset pin, by pulling up the OCset pin to VCC, or pulling down the OCset pin to PGnd. The current limit scheme in the IR3846 uses an internal temperature compensated current source to achieve an almost constant OC limit over temperature. Over Current Protection circuit senses the inductor current flowing through the Synchronous MOSFET. To help minimize false tripping due to noise and transients, inductor current is sampled for about 30 nS on the downward inductor current slope approximately 12.5% of the switching period before the inductor current valley. However, if the Synchronous MOSFET is on for less than 12.5% of the switching period, the current is sampled approximately 40nS after the start of the downward slope of the inductor current. When

21 www.irf.com © 2013 International Rectifier August 01, 2013 the sampled current is higher than the OC Limit, an OC event is detected. When an Over Current event is detected, the converter enters hiccup mode. Hiccup mode is performed by latching the OC signal and pulling the Intl_SS signal to ground for 20.48 mS (typ.). OC signal clears after the completion of hiccup mode and the converter attempts to return to the nominal output voltage using a soft start sequence. The converter will repeat hiccup mode and attempt to recover until the overload or short circuit condition is removed. Because the IR3846 uses valley current sensing, the actual DC output current limit will be greater than OC limit. The DC output current is approximately half of peak to peak inductor ripple current above selected OC limit. OC Limit, inductor value, input voltage, output voltage and switching frequency are used to calculate the DC output current limit for the converter. Equation (2) to determine the approximate DC output current limit. iII LIMITOCP  (2) IOCP = DC current limit hiccup point ILIMIT = Current Limit Valley Point ∆i = Inductor ripple current Figure 11: Timing Diagram for Current Limit Hiccup THERMAL SHUTDOWN Temperature sensing is provided inside IR3846. The trip threshold is typically 145oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is in itiated when the sensed temperature drops within the operating range. There is a 20 oC hysteresis in the thermal shutdown threshold. REMOTE VOLTAGE SENSING True differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. The RS+ and RS- pins of the IR3846 form the inputs to a remote sense differential amplifier (RSA) with high speed, low input offset and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. The input range for the differential amplifier is limited to 1.5V below the VCC rail. Note that IR3846 incorporates a smart LDO which switches the VCC rail voltage depending on the loading. When determining the input range assume the part is in light load and using the lower VCC rail voltage. There are two remote sense configurations that are usually implemented. Figure 12 shows a general remote sense (RS) configuration. This configuration allows the RSA to monitor output voltages above VCC. A resistor divider is placed in between the output and the RSA to provide a lower input voltage to the RSA inputs. Typically, the resistor divider is calculated to provide VREF (0.6V) across the RSA inputs which is then outputted to RSo. The input impedance of the RSA is 63 KOhms typically and should be accounted for when determining values for the resistor divider. To account for the input impedance, assume a 63 KOhm resistor in parallel to the lower resistor in the divider network. The compensation is then designed for 0.6V to match the RSo value. Low voltage applications can use the second remote sense configuration. When the output voltage range is within the RSA input specifications, no resistor divider is needed in between the converter output and RSA. The second configuration is shown in Figure 13. The RSA is used as a unity gain buffer and compensation is determined normally.

28 www.irf.com © 2013 International Rectifier August 01, 2013 L VV dt di DoL  , with body braking (3) L V dt di oL  , without body braking (4) IL = Inductor current VD = Forward voltage drop of the body diode of the Sync FET. Vo = output voltage L = Inductor value The Body Braking mechanism is kept OFF during pre- bias operation. Also, in the event of an extremely severe load step-down transient causing OVP, the Body Brake is overridden by the OVP latch, which turns on the Sync FET. MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is very critical parameter for low duty cycle, high frequency applications. Conventional approach limits the pulse width to prevent noise, jitter and pulse skipping. This results to lower closed loop bandwidth. IR has developed a proprietary scheme to improve and enhance minimum pulse width which utilizes the benefits of voltage mode control scheme with higher switching frequency, wider conversion ratio and higher closed loop bandwidth, the latter results in reduction of output capacitors. Any design or application using IR3846 must ensure operation with a pulse width that is higher than the minimum on-time. This is necessary for the circuit to operate without jitter and pulse- skipping, which can cause hi gh inductor current ripple and high output voltage ripple. sin out s on FPV V F Dt  (5) In any application that uses IR3846, the following condition must be satisfied: onon tt (min) (6) sin out on FPV Vt (min) (7) (min)on out sin t VFPV  (8) The minimum output voltage is limited by the reference voltage and hence V out(min) = 0.6V. Therefore, for Vout(min) = 0.6V, (min)on out sin t VFPV  (9) SVnS VFPV sin /1250 6.0  Therefore, at the maximum recommended input voltage 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 571 kHz. Conversely, for operation at the maximum recommended operating frequency (1.5 MHz) and minimum output voltage (0.6V). The input voltage (PVin) should not exceed 8V, otherwise pulse skipping may happen. MAXIMUM DUTY RATIO A certain off-time is specified for IR3846. This provides an upper limit on the operating duty ratio at any given switching frequency. The off-time remains at a relatively fixed ratio to switching period in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which IR3846 can operate. Figure 30 shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feed forward mechanism. Figure 30: Maximum duty cycle vs. switching frequency

30 www.irf.com © 2013 International Rectifier August 01, 2013 When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: DccinBoot VVPVV  (15) Figure 33: Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple currents generated during the on time of the control FETs should be provided by the input capacitor. The RMS value of this ripple for each channel is expressed by: in o V VD  (17) Where: D = Duty Cycle IRMS = RMS value of the input capacitor current Io = output current. Vin = Power Stage input voltage Io=35A and D = 0.1, the IRMS = 10.5A. Ceramic capacitors are recommended due to their peak current ca pabilities. They al so feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 7x22uF, 25V ceramic capacitors, GRM31CR61E226KE15L from Murata. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEV-FK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. Inductor Selection Inductors are selected based on output power, operating frequency and effi ciency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but may also result in reduced efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ∆i). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for t he desired operating ripple current can be determined using the following relation: s oin FDtt iLVV 1;   sin o oin FiV Where: Vin = Maximum input voltage V0 = Output Voltage ∆i = Inductor Ripple Current Fs = Switching Frequency ∆t = On time for Control FET D = Duty Cycle If ∆i ≈ 30%* Io, then the inductor is calculated to be 0.24μH. Select L=0.25μH, 744309025, from Wurth Electronik which provides an inductor suitable for this application. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criterion is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other co ntributing components. These components can be described as:

32 www.irf.com © 2013 International Rectifier August 01, 2013 VOUT VREF C POLE C3R3 Ve FZ FPOLE E/A Z f Frequency Gain(dB) H(s) dB Fb Comp Z IN Figure 35: Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vout) is given by: 331)( CsR CsR Z ZsHV V IN f out The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: 3)( R RsH  (23) 332 CRFz (24) First select the desired zero-crossover frequency (Fo): ESRo FF  and so FF  )10/1~5/1( (25) Use the following equation to calculate R3: LCin ESRoramp FV RFFVR (26) Where: Vramp = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor R5 = Feedback Resistor Vin = Maximum Input Voltage β = (RS+ - RS-) / Vo FLC = Resonant Frequency of the Output Filter To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: LCZ FF  %75 oo Z CL F 175.0 (27) Use equation (24), (25) and (26) to calculate C3. One more capacitor is sometimes added in parallel with C3 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: POLE POLE p CC CCF  (28) The pole sets to one half of the switching frequency which results in the capacitor CPOLE: S S POLE FR CFR C   (29) For a general unconditional stable solution for any type of output capacitors with a wide range of ESR values, we use a local feedback with a type III compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 36.

33 www.irf.com © 2013 International Rectifier August 01, 2013 VOUT VREF R5R4 C3R3 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain (dB) |H(s)| dB Fb Comp Figure 36: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: IN f out e Z ZsHV V  )( By replacing Zin and Zf, according to Figure 36, the transfer function can be expressed as:   44 3325 54433 11)( CsRCC CCsRCCsR RRsCCsRsH  (30) The compensation network has three poles and two zeros and they are expressed as follows: 01 PF (31) CRFP   (32) CR CC CCR FP    (33) CRFZ   (34)  54534 RCRRCFZ (35) Cross over frequency is expressed as: ooramp in o CLV (36) Based on the frequency of the zero generated by the output capacitor and its ESR, relative to the crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. Table 3: Different types of compensators Compensator Type FESR vs FO Typical Output Capacitor Type II FLC < FESR < FO < FS/2 Electrolytic Type III F LC < FO < FESR SP Cap, Ceramic The higher the crossover frequency is, the potentially faster the load transient re sponse will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency ( F o) is selected such that: The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45 o for overall stability. The specifications for designing channel 1: Vin = 12V Vo = 1.2V Vramp = 1.8V (This is a function of Vin, pls. see Feed-Forward section) Vref = 0.6V β = (RS+ - RS-) / Vo (This assumes the resistor divider placed between Vout and the RSA scales down the output voltage to Vref. If the RSA is not used or Vout is connected directly

34 www.irf.com © 2013 International Rectifier August 01, 2013 to the RSA, β = 1. Please refer to the Remote Sensing Amplifier section) Lo = 0.250 µH Co = 6 x 100µF, ESR≈3mΩ each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 100µF capacitor used in this design is 56µF at 1.2 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency F LC and using equation (20) to compute the small signal Co. These result to: FLC = 17.4 kHz FESR = 947 kHz Fs/2 = 300 kHz Select crossover frequency F0=100 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. Detailed calculation of compensation Type III: Desired Phase Margin Θ = 70°   sin1 sin1 2 oZ FF 14.1 kHz   sin1 sin1 2 oP FF 567.1 kHz Select:  21 5.0 ZZ FF 7.05 kHz and  sP FF 5.03 300 kHz Select C4 = 2.2nF. Calculate R3, C3 and C2: in oscooo VC VCLFR 2 ; R3 = 3.60 kΩ, Select: R3 = 2.7 kΩ RFC ; C3 = 8.49 nF, Select: C3 = 8.2 nF RFC ; C2 = 196 pF, Select: C2 = 160 pF Calculate R4, R5 and R6: ; R4 = 127.6 Ω, Select R4 = 127 Ω ; R5 = 5.13 kΩ, Select R5 = 4.02 kΩ

56 RVV

; R6 = 4.02 kΩ, Select R6 = 4.02 kΩ If (β x Vo) equals Vref, R6 is not used. Setting the Power Good Threshold In this design IR3846, the PGood outer limits are set at 95% and 120% of VREF. PGood signal is asserted 1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V (Figure 37) . As long as the Vsns voltage is between the threshold ranges, Enable is high, and no fault happens, the PGood remains high. The following formula can be used to set the PGood threshold. V out (PGood_TH) can be taken as 95% of Vout. Choose Rsns1=4.02 KΩ.

35 www.irf.com © 2013 International Rectifier August 01, 2013 1195.02 )_( RsnsVREF VRsns THPGoodout    (37) Rsns2 = 4.02 kΩ, Select 4.02 kΩ. OVP comparator also uses Vsns signal for Over- Voltage detection. With above values for Rsns2 and Rsns1, OVP trip point (Vout _OVP) is 212.1_ Rsns RsnsRsnsVREFVout OVP  (38) Vout_OVP = 1.44 V Selecting Power Good Pull-Up Resistor The PGood is an open drain output and require pull up resistors to VCC. The va lue of the pull-up resistors should limit the current flowing into the PGood pin to less than 5mA. A typical value used is 10kΩ.

36 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL APPLICATION INTERNALLY BIASED SINGLE SUPPLY IR3846 Boot SW FB VSNS Vcc PGood Vin PGNDAGND Vp Vref Rt/Sync Comp RS+ RS- RSo Cpvin2 Cboot Lo Cout Cref Cvcc Rpg Rt Cvin 39.2 K

10 K10uF

0.1uF 6 x 100uF0.250uH 7 x 22uF Cpvin3 0.1uF 1uF Ren1 7.5 K Ren2 49.9 K Cc3 160pF Cc2 8.2nF Cc1 2200pF Rbode Rfb2 4.02 K Rfb1 4.02 K Rsns2 4.02 K Rsns1 4.02 K Rc2 2.7 K Rc1 127 Vo PGood Cpvin1 330uF PVinEn OCselect Co1 0.1 uF S_Ctrl Figure 37: Application circuit for a 12V to 1.2V, 21A Point of Load Converter Using the Internal LDO Suggested Bill of Material for application circuit 12V to 1.2V Part Reference Qty Value Description Manufacturer Part Number Cpvin1 1 330uF SMD, electrolytic, 25V, 20% Panasonic EEV-FK1E331P Cpvin2 7 22uF 1206, 25V, X5R, 10% Murata GRM31CR61E226KE15L Cref 1 100pF 0603, 50V, C0G, 5% Murata GRM1885C1H101JA01D Cvin 1 1.0uF 0603, 25V, X5R, 20% Murata GRM188R61E105KA12D Cvcc 1 10uF 0603, 10V, X5R, 20% TDK C1608X5R1A106M Cpvin3 Cboot Co1 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D Cc1 1 2200pF 0603, 50V, X7R, 10% Murata GRM188R71H222KA01D Cc2 1 8.2nF 0603, 50V, X7R, 10% Murata GRM188R71H822KA01D Cc3 1 160pF 0603, 50V, NPO, 5% Murata GRM1885C1H161JA01D Cout1 6 100uF 1206, 6.3V, X5R, 20% Murata GRM31CR60J107ME39L L0 1 0.250uH 250nH,14x13x9mm DCR=0.165ohm Wurth Electronik Inc. 744309025 Rbd 1 20 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF20R0V Rc1 1 127 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1270V Rc2 1 2.7K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF2701V Ren1 1 7.5K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF7501V Ren2 1 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V Rfb1 Rfb2 Rsns1Rsns1 4 4.02K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4021V Rt 1 39.2K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF3922V Rpg 1 10K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1002V U1 1 IR3846 PQFN 5x7mm International Rectifier IR3846MPBF

37 www.irf.com © 2013 International Rectifier August 01, 2013 EXTERNALLY BIASED DUAL SUPPLIES Figure 38: Application circuit for a 12V to 1.2V, 21A Point of Load Converter using external 5V VCC Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC Part Reference Qty Value Description Manufacturer Part Number Cpvin1 1 330uF SMD, electrolytic, 25V, 20% Panasonic EEV-FK1E331P Cpvin2 7 22uF 1206, 25V, X5R, 10% Murata GRM31CR61E226KE15L Cref 1 100pF 0603, 50V, C0G, 5% Murata GRM1885C1H101JA01D Cvin 1 1.0uF 0603, 25V, X5R, 20% Murata GRM188R61E105KA12D Cvcc 1 10uF 0603, 10V, X5R, 20% TDK C1608X5R1A106M Cpvin3 Cboot Co1 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D Cc1 1 2200pF 0603, 50V, X7R, 10% Murata GRM188R71H222KA01D Cc2 1 8.2nF 0603, 50V, X7R, 10% Murata GRM188R71H822KA01D Cc3 1 160pF 0603, 50V, NPO, 5% Murata GRM1885C1H161JA01D Cout1 6 100uF 1206, 6.3V, X5R, 20% Murata GRM31CR60J107ME39L L0 1 0.250uH 250nH,14x13x9mm DCR=0.165ohm Wurth Electronik Inc. 744309025 Rbd 1 20 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF20R0V Rc1 1 127 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1270V Rc2 1 2.7K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF2701V Ren1 1 7.5K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF7501V Ren2 1 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V Rfb1 Rfb2 Rsns1Rsns1 4 4.02K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4021V Rt 1 39.2K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF3922V Rpg 1 10K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1002V U1 1 IR3846 PQFN 5x7mm International Rectifier IR3846MPBF

38 www.irf.com © 2013 International Rectifier August 01, 2013 EXTERNALLY BIASED SINGLE SUPPLY IR3846 Boot SW FB VSNS Vcc PGood Vin PGNDAGND Vp Vref Rt/Sync Comp RS+ RS- RSo Cpvin2 Cboot Lo Cref Cvcc Rpg Rt Cvin 39.2 K 0.1uF 0.190uH 7 x 22uF Cpvin3 0.1uF 1uF Ren1 21 K Ren2 41.2 K Cc3 100pF Cc2 8.2nF Cc1 2200pF Rbode Rfb2 4.53 K Rfb1 4.53 K Rsns2 4.53 K Rsns1 4.53 K Rc2 3.9 K Rc1 78.7 Vo PGood Cpvin1 330uF PVinEn OCselect Cout 6 x 100 uF Co1 0.1 uF Figure 39: Application circuit for a 5V to 1.2V, 21A Point of Load Converter Suggested bill of material for application circuit 5V to 1.2V Part Reference Qty Value Description Manufacturer Part Number Cpvin1 1 330uF SMD, electrolytic, 25V, 20% Panasonic EEV-FK1E331P Cpvin2 7 22uF 1206, 25V, X5R, 10% Murata GRM31CR61E226KE15L Cref 1 100pF 0603, 50V, C0G, 5% Murata GRM1885C1H101JA01D Cvin 1 1.0uF 0603, 25V, X5R, 20% Murata GRM188R61E105KA12D Cvcc 1 10uF 0603, 10V, X5R, 20% TDK C1608X5R1A106M Cpvin3 Cboot Co1 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D Cc1 1 2200pF 0603, 50V, X7R, 10% Murata GRM188R71H222KA01D Cc2 1 8.2nF 0603, 50V, X7R, 10% Murata GRM188R71H822KA01D Cc3 1 100pF 0603, 50V, NPO, 5% Murata GRM1885C1H101JA01D Cout1 6 100uF 1206, 6.3V, X5R, 20% Murata GRM31CR60J107ME39L L0 1 0.190uH 10x6.8x7.3mm, DCR=0.20mΩ Inter- Technical,LLC SL40307A-R19KHF Rbd 1 20 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF20R0V Rc1 1 78.7 Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF78R7V Rc2 1 3.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF3901V Ren1 1 21K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF2102V Ren2 1 41.2K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4122V Rfb1 Rfb2 Rsns1Rsns1 4 4.53K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4531V Rt 1 39.2K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF3922V Rpg 1 10K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1002V U1 1 IR3846 PQFN 5x7mm International Rectifier IR3846MPBF

40 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vout=1.2V, Iout=3.5-14A, Fs=600kHz, Room Temperature, No air flow Figure 46: Vout Transient Response, 3.5A to 14.0A step at 2.5A/uSec CH2:Vout, CH4:Iout

41 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vout=1.2V, Iout=24.5-35A, Fs=600kHz, Room Temperature, No air flow Figure 47: Vout Transient Response, 24.5A to 35A step at 2.5A/uSec CH2:Vout, CH4:Iout

42 www.irf.com © 2013 International Rectifier August 01, 2013 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vout=1.2V, Iout=35A, Fs=600kHz, Room Temperature, No air flow Figure 48: Bode Plot with 35A load: Fo = 100.6 kHz, Phase Margin = 52.5 Degrees

44 www.irf.com © 2013 International Rectifier August 01, 2013 LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, input capacitors, output capacitors and the IR3846 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3846. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for PVin, Vin and VCC should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use at least one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 6-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 51a-f illustrates the implem entation of the layout guidelines outlined above, on the IRDC3846 6-layer demo board. Figure 51a: IRDC3846 Demo board Layout Considerations – Top Layer - Compensation parts should be placed as close as possible to the Comp pins - SW node copper is kept only at the top layer to minimize the switching noise - Single point connection between AGND & PGND, should be placed near the part and kept away from noise sources PGND PVin Vout AGND - Ground path between VIN- and VOUT- should be minimized with maximum copper - Bypass caps should be placed as close as possible to their connecting pins - Filled vias placed under PGND and PVin pads to help thermal performance. PGND

47 www.irf.com © 2013 International Rectifier August 01, 2013 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in follow ing figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self- centering on specific processes. For further information, please refer to “SupIRBuck ® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) PAD SIZES PCB SPACING

48 www.irf.com © 2013 International Rectifier August 01, 2013 SOLDER RESIST  IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD). This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability.  When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer  However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined.  When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X & Y), in order to accommodate any layer to layer misalignment.  Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. PAD SIZES PAD SPACING

49 www.irf.com © 2013 International Rectifier August 01, 2013 STENCIL DESIGN  Stencils for PQFN can be used with thicknesses of than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results.  Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. SOLDER PASTE STENCIL PAD SIZES

53 www.irf.com © 2013 International Rectifier August 01, 2013 ENVIRONMENTAL QUALIFICATIONS Qualification Level Industrial Moisture Sensitivity Level 5mm x 7mm PQFN MSL3 ESD Machine Model (JESD22-A115A) Class A <200V Human Body Model (JESD22-A114F) Class 1C 1000V to <2000V Charged Device Model (JESD22-C101D) Class III 500V to ≤1000V RoHS Compliant Yes Data and specifications subject to change without notice. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com

Product Information

SL40307A-R19KHF specifications and overview.

Summary

Single-Input Voltage, Synchronous Buck Regulator

Description

Single-Input Voltage, Synchronous Buck Regulator

Source title SL40307A-R19KHF Datasheet(PDF) - International Rectifier

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