SL2ICS20 NXP | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Datasheet sections
- 1 SCOPE
- 2 REFERENCE DOCUMENT S
- 2.1 Philips Documents
- 3 MECHANICAL SPECIFI CATION
- 3.1 Wafer
- 3.2 Wafer Backside
- 3.3 Chip Dimensions
- 3.4 Passivation
- 3.5 Au Bump
- 4 FAIL-DIE IDENTIFICATION
- 5 ORDERING INFORMATI ON
- 5.1 Bumped die on sawn wafer
- 6 CHIP ORIENTATION A ND BONDPAD LOCATIONS
- 7 ELECTRICAL SPECIFI CATIONS
- 7.1 ABSOLUTE MAXIMUM RATINGS 1,
- 7.2 OPERATING CONDITIONS
- 7.3 ELECTRICAL CHARACTERISTICS
- 8 FINAL WAFERTEST SP ECIFICATION
- 9 HINTS FOR LABEL IC ENCAPSULATION
- 9.1 Protection against Visible Light
- 9.2 Protection against UV Light
- 9.3 Resistance to X-Rays
- 10 DEFINITIONS
- 11 DISCLAIMERS
- 11.1 Life support applica tions
- 11.2 Licence Policy
- 12 REVISION HISTORY
I?CODE SLI Label IC Bumped Wafer Specification December 2002Product Specification Revision 3.0 Public Philips Semiconductors ADDENDUM
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
1 SCOPE
This specification describes the electrical, physical and dimensional properties of Au-bumped sawn wafers on FFC of I•CODE 1 SLI Label ICs on a Philips C075EE process and is the base for delivery of tested I•CODE SLI Label ICs.
2 REFERENCE DOCUMENTS
2.1 Philips Documents
- MIL-STD 883D Method 3023
- MIL-STD 883D Method 3015
- SNW-FQ-627
- PICTOH-QS007
- General Specification for 8” Wafer
- General Quality Specification
- I•CODE SLI Label IC, Functional Specification
- Application Note Coil Design Guide
- Specification of the IBIS Wafermap
3 MECHANICAL SPECIFICATION
3.1 Wafer
- Diameter: 8”
- Thickness: 150 µm ± 15 µm
- Flatness: max. tbf
3.2 Wafer Backside
- Material: Si
- Treatment: ground + stress releave
- Roughness: Ra max. 0.5 µm Rt max. 5 µm
3.3 Chip Dimensions
- Chip size: 900 x 780 µm
- Scribe lines: 80 / 80 µm
3.4 Passivation
- Type: sandwich structure
- Material: PSG / Nitride (on top)
- Thickness: 500 nm / 600 nm 1 I• CODE is a registered trademark of Philips Electronics N.V.
3.5 Au Bump
- Bump material: > 99.9% pure Au
- Bump hardness: 35 – 80 HV 0.005
- Bump shear strength: > 70 MPa
- Bump height: 18 µm
- Bump height uniformity: - within a die: ± 2 µm - within a wafer: ± 3 µm - wafer to wafer: ± 4 µm
- Bump flatness: ± 1.5 µm
- Bump size: - LA, LB 92 x 92 µm- VSS2, TESTIO 62 x 62 µm
- Pad size (no bump!) - LA, LB 78 x 78 µm - VSS3, TESTIO 48 x 48 µm
- Bump size variation: ± 5 µm
- Under bump metallisation: sputtered TiW
4 FAIL-DIE IDENTIFICATION
Every die is electrically tested according to data sheet. Identification of chips with electrical parameters not conform with the data sheet is done by inking and wafer mapping (all dies at wafer periphery are identified as ‘FAIL’). The ink information refers to unsawn wafers. At sawn wafers (on FFC) additional ICs are be marked as ‘FAIL’ in the wafer map if damaged during the sawing process. These ICs will not be inked.
4.1 Wafer Mapping
Wafer mapping for failed die information is available on Floppy-Disk. Format: IBIS format
5 ORDERING INFORMATION
5.1 Bumped die on sawn wafer
- Order Code: SL2 ICS20 01DW/V4D
- 12NC: 9352 716 15005 2 VSS is conntected to substrate. 3 VSS is conntected to substrate.
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
6 CHIP ORIENTATION AND BONDPAD LOCATIONS
PAD(center) x [µm] y [µm] LA 0.0 0.0 LB 665.0 -30.0 TESTIO 687.0 -632.0 VSS -93.0 -385.0 Not to scale! (1) X-Scribeline width: tbd µm (7) LB bump edge to chip edge, y-length: 69[+7] µm (2) Y-Scribeline width: tbd µm (8) LB bump edge to chip edge, x-length: 39[+7] µm (3) Chip step, x-length: X-Scribeline + 900 µm (9) TESTIO bump edge to chip edge, x-length:32[+7] µm (4) Chip step, y-length: Y-Scribeline + 780 µm (10) TESTIO bump edge to chip edge, y-length:32[+7] µm (5) LA bump edge to chip edge, y-length: 39[+7] µm (11) VSS bump edge to chip edge, y-length: 279[+7] µm (6) LA bump edge to chip edge, x-length: 104[+7] µm (12) VSS bump edge to chip edge, x-length: 26[+7] µm [+7µm] ... for pad edge to chip edge! Figure 1 (1) X Y LA TESTIO VSS LB (4) (3) (5) (6) (2) (9) Widths and lengths are measured from metal to metal. (12) (11) (10) (8) (7)
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
7 ELECTRICAL SPECIFICATIONS
7.1 ABSOLUTE MAXIMUM RATINGS 1, 2
Tstg Storage Temperature Range - 55 to +140 °C Tj Junction Temperature - 55 to +140 °C VESD ESD Voltage Immunity MIL-STD-883D, Method 3015.7, Human Body Model ± 2 kVpeak Imax LA-LB Maximum Input Peak Current ± 60 mApeak NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
7.2 OPERATING CONDITIONS
CONDITIONS MIN TYP1 MAX UNIT Tj op Operating Junction Temperature - 25 + 85 °C ILA-LB Input Current2 30 mArms VLA-LB Minimum Supply Voltage for READ/WRITE/EAS ± 2.5 ± 2.6 ± 2.9 Vrms fop Operating Frequency 3 13.553 13.560 13.567 MHz NOTES: 1. Typical ratings are not guaranteed. These values listed are at room temperature. 2. The voltage between LA and LB is limited by the on-chip voltage limitation circuitry (corresponding to parameter ILA-LB). 3. Bandwidth limitation (±7 kHz) according to ISM band regulations.
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
7.3 ELECTRICAL CHARACTERISTICS
Tjop = - 25 to +85 °C SYMBOL PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT Cres Input Capacitance between LA - LB 2 VLA-LB = 2 Vrms 22.3 23.5 24.7 pF Pmin Minimum Operating Supply Power 3 280 µW m Modulation of RF Voltage for Demodulator Response m V - V V + V max min tP sm Modulation Pulse Length tD Demodulator Response Time m ≥ 10 %, 100% µs Rmod Load Modulation Ω tret EEPROM Data Retention Tamb ≤ 55 °C 10 Years nwrite EEPROM Write Endurance 100 000 Cycles NOTES: 1. Typical ratings are not guaranteed. These values listed are at room temperature. 2. Measured with an HP4285A LCR meter at 13.56 MHz. 3. Including losses in resonant capacitor and rectifier. ** : refer to ISO/IEC 15693-2 and 15693-3 including pulse shapes and tolerances; proper coil design assumed
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
8 FINAL WAFERTEST SPECIFICATION
- Minimum yield per wafer: 30 % of 35416 potential good dies .
- Minimum yield per lot: 30%
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
9 HINTS FOR LABEL IC ENCAPSULATION
9.1 Protection against Visible Light
As a result of the ultra low power design of the I•CODE SLI Label IC some analogue circuits on the chip are light sensitive. This means that common sun light can impact the operation of the label if the chip is not protected against visible light radiation. Measurements have shown that a radiation of E max = 60 W/m2 (spectrum: 400 to 1000 nm) causes a reduced operating range of the plain chip. Measurements of direct sunlight in summer deliver values up to 260 W/m 2. To ensure proper operation an expected minimum radiation reduction factor of approx. 9 (2 x 260/60 = 8.7) must be provided by the encapsulation. That means special care has to be taken to ensure a sufficient light application requirements.
9.2 Protection against UV Light
An EEPROM memory, as it is also used in the I•CODE SLI Label IC, has some principle sensitivity to UV light (applies to EEPROM-technology in general). Thus strong UV exposure in the production of inlets/labels has to be avoided. UV protection has to be ensured using appropriate assembly methods.
9.3 Resistance to X-Rays
X-ray exposure on comparable Philips ICs (with even smaller feature size) caused neither a long term influence on the behaviour of the ICs nor on the data retention of the EEPROMs.
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
10 DEFINITIONS
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics section of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
11 DISCLAIMERS
11.1 Life support applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so on their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
11.2 Licence Policy
Purchase of this Philips IC with a functionally according to ISO/IEC 15693 Standard does not convey an implied license under any patent right on this standard. A license for the Philips portfolio of patents on the ISO/IEC 15693 Standard can be obtained via the Philips Intellectual Property and Standards department. For more information please contact the nearest Philips Semiconductors sales office.
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20
12 REVISION HISTORY
Table 1 Bumped Wafer Specification SL2 ICS20 Revision History REVISION DATE CPCN PAGE DESCRIPTION 1.0 Sept. 2000 - Initital version. 1.1 Feb. 2002 New die size and dimensions
2.0 June
2.1 Sept. 2002
3 Include IBIS Wafermap
3.0 Dec. 2002 Product Specification
Philips Semiconductors Product Specification Rev.3.0 December 2002 Bumped Wafer Specification SL2 ICS 20 NOTES
Philips Semiconductors - a worldwide company Contact Information For additional information please visit http://www.semiconductors.philips.com .Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without any notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors