SL2101 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

  • Single chip synthesized broadband solution
  • Configurable as both up converter and downconverter requirements in double conversion tuner applications
  • Incorporates 8 programmable mixer power settings
  • Compatible with digital and analogue system requirements
  • CSO -65 dBc, CTB -68 dBc (typical)
  • Extremely low phase noise balanced local oscillator, with very low fundamental and harmonic radiation
  • PLL frequency synthesizer designed for high comparison frequencies and low phase noise
  • Buffered crystal output for pipelining system reference frequency
  • I 2C Controlled

Applications

  • Double conversion tuners
  • Digital Terrestrial tuners
  • Cable telephony
  • Cable Modems
  • M A T V

Description

The SL2101 is a fully integrated single chip broadband mixer oscillator with low phase noise PLL frequency synthesizer. It is intended for use in double conversion tuners as both the up and down converter and is compatible with HIIF frequencies up to 1.4 GHz and all standard tuner IF output frequencies. It also contains a programmable power facility for use in systems where power consumption is important. The device contains all elements necessary, with the exception of local oscillat or tuning network, loop filter and crystal reference to produce a complete synthesized block converter, compatible with digital and analogue requirements. August 2004

Ordering Information

SL2101C/KG/NP1P SSOP Tubes SL2101C/KG/NP1Q SSOP Tape & Reel SL2101C/KG/NP2P SSOP* Tubes SL2101C/KG/NP2Q SSOP* Tape & Reel SL2101C/KG/LH2N MLP* Trays SL2101C/KG/LH2Q MLP* Tape& Reel * Pb free All codes baked and drypacked -40°C to +85 °C SL2101 Synthesized Broadband Converter with Programmable Power Data Sheet Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Quick Reference Data All data applies at maximum power setting with the following conditions unless otherwise stated; a) nominal loads as follows;

1220 MHz output load as in Figure 4

44 MHz output load as in Figure 5

b) input signal per carrier of 63 dBµV *dBm assumes a 75 Ω characteristic impedance, and 0 dBm = 109 dBµV Functional Description The SL2101 is a broadband wide dynamic ra nge mixer oscillator with on-board I 2C bus controlled PLL frequency synthesizer, optimized for a pplication in double conversi on tuner systems as both the up and down converter. It also has application in any system where a wide dynamic range broadband synthesized frequency converter is required. The SL2101 is a single chip solution containing all necessa ry active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaini ng network. The pin assignment is contained in Figures 2 and 3 for the SSOP and MLP packages and the block diagram in Figure 1. The device also contains a programmable facility to adj ust the power in the lna/mixer so allowing power to be traded against intermodulation performance for power critical applications, such as telephony modems. Characteristic Units RF input operating range 50-1400 MHz Input noise figure, SSB, 50-860 MHz 860-1400 6.5 - 8.5 8.5 - 12 dB dB Conversion gain 12 dB CTB (fully loaded matrix) -68 dBc CSO (fully loaded matrix) -65 dBc P1 dB input referred 110 dB µV Local oscillator phase noise as upconverter SSB @ 10 kHz offset SSB @ 100 kHz offset -90 -112 dBc/Hz dBc/Hz Local oscillator phase noise as downconverter SSB @ 10 kHz offset SSB @ 100 kHz offset -93 -115 dBc/Hz dBc/Hz Local oscillator phase noise floor -136 dBc/Hz PLL spurs on converted output with input @ 60 dBµV< - 7 0 d B c PLL maximum comparison frequency 4 MHz PLL phase noise at phase detector -152 dBc/Hz

Zarlink Semiconductor Inc. Converter Section In normal application the RF input is interfaced thro ugh appropriate impedance matching and an AGC front end to the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region of 50 to 1400 MHz and for high intermodul ation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. The lna/mixer current and hence signal handling and device power consumption are programmable through the I2C bus as tabulated in Figure 7. The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and 9 respectively and for narrow band downconversion in Fi gures 10 and 11 respectively. The input referred two tone intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and gain versus frequency and NF specification limits, over se lectable power settings are contained in Figures 13, 14 and 15 respectively. The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this stage the RF signal is mixe d with the local oscillator fr equency, which is generated by the on-board oscillator. The oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure 19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator. Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of an IF in the range 30-1400 MHz so covering standard HI IFs between 1 and 1.4 GHz and all conventional tuner output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is shown in Figure 4, which will typically be terminated wi th a differential 200 load. When used as a narrowband downconverter the output should be differentially loaded with a discrete differential to single ended converter as in Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20. The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22 respectively. In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation performance. The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference Data'. PLL Frequency Synthesizer The PLL frequency synthesizer section co ntains all the elements necessary, with the exception of a reference frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The programmable divider is of MN+A archit ecture, where the dual modulus prescale r is 16/17, the A counter is 4-bits, and the M counter is 11 bits. The output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency. This fr equency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to

Zarlink Semiconductor Inc. the comparison frequency by the reference divider which is pr ogrammable into 1 of 29 ratios as detailed in figure 23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Fi gure 25 is used when driving a second SL2101 as a downconverter. The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. The programmable divider output Fpd divided by two an d the reference divider output Fcomp can be switched to port P0 by programming the device into test mode. The test modes are described in Figure 26. The crystal reference frequency can be switched to BUFR EF output by bit RE as described in Figure 27. The BUFREF output is not available on the MLP package. Programming The SL2101 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SC L lines respectively as defined by I 2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tabl es 1 and 2 in Figure 28 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes ar e received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this peri od, the device generates an internal STOP condition, which inhibits further reading. Write Mode With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 214 -20 inclusive. Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29. Byte 5 controls the test modes, see Figure 26, the buffere d crystal reference output sele ct RE, see Figure 27, the power setting, see Figure 7 and the output port P0. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data by tes can be entered, where byte interpretation follows the same procedure, without re-addres sing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after an y data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read Mode When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25° C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high th is indicates that the programmed information may have been corrupted and the device reset to the power up condition. Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked.

Zarlink Semiconductor Inc. Programmable Features Synthesizer programmable divider Function as described above Reference programmable divider Function as described above. Charge pump current The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in Figure 29. Power setting The device power and hence signal handling can be programmed by bits I2 - I0 within data byte 5, as defined in Figure 7. In all power settings the synthesizer remains enabled to facilitate rapid PLL lock reacquisition Test mode The test modes are defined by bits T2 - T0 as described in Figure 26. General purpose ports, P0 The general purpose port can be programmed by bits P0; Logic '1' = on Logic '0' = off (high impedance) - this is the default state at device power on Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the BUFREF output by bit RE as described in Figure 27. The BUFREF output defaults to the 'ON' conditi on at device power up. This output is only available on the SSOP package. Figure 4 - Nominal Output Load as Upconverter into Differential SAWF 10nH 10nH Vcc SL2101 OUTPUT OUTPUTB 200 Ω 200 Ω SAWF 33 Ω 33 Ω

Zarlink Semiconductor Inc. Figure 8 - Typical RF Input Impedance as Broadband Upconverter (Maximum Power Setting) Figure 9 - RF Input Impedance Matching Network as 50 - 860 MHz Upconverter CH1 S 11 1 U FS START 1 000.000 000 MHz STOP 1 400.000 000 MHz DB1 4.7V Cor Avg Smo PRm Z 0

27 Jul 2001 11:24:54

1_: 4.3164 -99.426 1.6007 pF 1 000.000 000 MHz 2_: 3.7266 -80.117 1.15 GHz 3_: 4.1328 -70.223 1.25 GHz 4_: 4.7617 -58.166 1.4 GHz 200 Ω 100nF 100nF 47nH RFINPUT RFINPUTB SL2101 RFIN75 Ω

Zarlink Semiconductor Inc. Figure 10 - Typical RF Input Impedance as Narrow Band Downconverter (maximum power setting) Figure 11 - RF Input Impedance Matching Network as 1.22 GHz Downconverter CH1 S 11 1 U FS START 1 000.000 000 MHz STOP 1 400.000 000 MHz UA6 4.7V Cor Avg Smo PRm Z 0

27 Jul 2001 09:05:31

1_: 20.07 -46.965 3.3888 pF 1 000.000 000 MHz 2_: 19.795 -34.527 1.15 GHz 3_: 20.666 -26.233 1.25 GHz 4_: 25.772 -15.155 1.4 GHz 2.7pF 10nF 3.9nH RFINPUT RFINPUTB SL2101 RFIN 200 Ω

Zarlink Semiconductor Inc. Figure 21 - Typical IF Output Impedance as Upconverter, Single-Ended I2 I1 I0 Typ NF (dB) Gain (dB) typ IPIP3 (dBµV) 0 0 0 10.3 15.6 124 0 0 1 9.3 15.1 119 0 1 0 8.8 14.0 112 0 1 1 8.7 12.1 106 1 0 0 11.6 15.4 121.3 1 0 1 9.0 15.1 119.7 1 1 0 8.3 13.9 112.6 1 1 1 8.0 11.9 106.3 Figure 20 - Downconverter Gain, NF and IP3 with Recommended (Fig. 4) Load Versus Power Setting CH1 S 11 1 U FS START 1 000.000 000 MHz STOP 1 400.000 000 MHz DB1 4.7V Cor Avg Smo PRm Z 0 1_: 4.3164 -99.426 1.6007 pF 1 000.000 000 MHz 2_: 3.7266 -80.117 1.15 GHz 3_: 4.1328 -70.223 1.25 GHz 4_: 4.7617 -58.166 1.4 GHz

Zarlink Semiconductor Inc. Figure 22 - Typical IF Output Impedance as Downconverter, Single-Ended R4 R3 R2 R1 R0 Ratio 00000 2 00001 4 00010 8 00011 1 6 00100 3 2 00101 6 4 00110 1 2 8 00111 2 5 6 0 1 0 0 0 Illegal state 01001 5 01010 1 0 01011 2 0 01100 4 0 01101 8 0 01110 1 6 0 01111 3 2 0 CH1 S 11 1 U FS START 10.000 000 MHz STOP 100.000 000 MHz UA6 4.7V Cor Avg Smo PRm Z 0

27 Jul 2001 09:48:39

1_: 1.3588 k -1.1071 k 7.1882 pF 20.000 000 MHz 2_: 606.87 -695.97 40 MHz 3_: 305.72 -549.5 70 MHz 4_: 213.55 -449.58 100 MHz

Zarlink Semiconductor Inc. Figure 28 - Read/Write Data Formats Table 1 - Write Data Format (MSB is transmitted first) MSB LSB Address 1 1 0 0 0 MA1 MA0 0 A Byte 1 Programmable divider 0 214 213 212 211 210 29 28 A Byte 2 Programmable divider 27 26 25 24 23 22 21 20 A Byte 3 Control data 1 C1 C0 R4 R3 R2 R1 R0 A Byte 4 Control data T2 T1 T0 I2 I1 I0 RE P0 A Byte 5 Table 2 - Read Data Format (MSB is transmitted first) A : Acknowledge bit MA1,MA0 : Variable address bits (see Table 3) 214-20 : Programmable division ratio control bits I2-I0 : lna/mixer power select (see Figure 7) C1-C0 : Charge pump current select (see Figure 29) R4-R0 : Reference division ratio select (see Figure 23) T2-T0 : Test mode control bits (see Figure 26) RE : Buffered crystal reference output enable (see Figure 27 P0 : P0 port output state POR : Power on reset indicator FL : Phase lock flag MSB LSB Address 1 1 0 0 0 MA1 MA0 1 A Byte 1 Programmable divider POR FL 0 0 0 0 0 0 A Byte 2 Table 3 - Address Selection MA1 MA0 Address input voltage level 0 0 0-0.1Vcc 0 1 Open circuit 1 0 0.4Vcc – 0.6 Vcc # 1 1 0.9 Vcc - Vcc

Zarlink Semiconductor Inc. Figure 29 - Charge Pump Current Electrical Characteristics - Test conditions (unless otherwise stated). Tamb = -40o to 85oC, Vee= 0V, Vcc=5 V+-5%. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage at maximum power setting unless otherwise stated. C1 C0 Current in mA Min. Typ. Max. Characteristic Pin Min. Typ. Max. Units Conditions Supply current 6, 12,17, 19, 22 90 120 mA IF outputs will be connected to Vcc through the differential load as in Figures 4, 5 & 6. See Figure 7 for programmable settings. Input frequency range 9, 10 50 1400 MHz Operating condition only. Output frequency range 14, 15 30 1400 MHz Operating condition only. Composite peak input signal 9, 10 97 dBµV Operating condition only. All synthesizer related spurs on IF Output 14, 15 -60 dBc Within channel bandwidth of

8 MHz and with input power of

µV. Upconverter application Input frequency range 9, 10 50 860 MHz Input impedance 75 Ω See Figure 8. Input return loss 6 dB With input matching network as in Figure 9. Input Noise Figure 9.5 dB Tamb=27°C, see Figure 13, with input matching network as in Figure 9. See Figure 15 for programmable settings. Conversion gain 9 dB Differential voltage gain to 200 Ω load on output of SAWF as in Figure 4, see Figure 14. See Figure 15 for programmable settings.

Zarlink Semiconductor Inc. Note 1: All power levels are referred to 75 Ω and 0 dBm = 109 dB µV Note 2: Any two tones within RF operating range at 94 dB µV beating within band, with ou tput load as in Figure 4 Note 3: Port powers up in high impedance state Note 4: To maximise phase noise the tuning range should be minimi sed and Q of resonator maximised. The application as in Figure 18 has a tuning range of 200 MHz. Note 5: If the BUFREF output is not used it should be left open circuit or connected to Vccd and disabled by setting RE = '0'. Charge pump drive output current 27 0.5 mA Vpin = 0.7 V Crystal frequency 1,2 2 20 MHz See Figure24 and Figure 25 for application. Recommended crystal series resistance 10 200 Ω 4 MHz parallel resonant crystal External reference input frequency 2 2 20 MHz Sinewave coupled through 10 nF blocking capacitor External reference drive level 2 0.2 0.5 Vpp Compatible with BUFREF output. (SSOP package only) Phase detector comparison frequency 4M H z Equivalent phase noise at phase detector SSB, within loop bandwidth -148 dBc/Hz F comp = 1 MHz -152 dBc/Hz F comp = 250 kHz -158 dBc/Hz F comp = 62.5 kHz Local oscillator programmable divider division ratio 240 32767 Reference division ratio See Figure 23. Output port sink current leakage current mA µA See Note 3. Vport = 0.7 V Vport =Vcc BUFREF output output amplitude output impedance 0.35 250 Vpp Ω AC coupled. Note 5. Enabled by bit RE=1 and default state on power-up. BUFREF output only available on SSOP package Address select Input high current Input low current -0.5 mA mA See Figure 28, Table 3 Vin=Vcc Vin=Vee Characteristic Pin Min. Typ. Max. Units Conditions

Zarlink Semiconductor Inc. Absolute Maximum Ratings - All voltages are referred to Vee at 0 V (pins 7, 8, 11, 13, 16, 18, 23, 25). Characteristic Pin Min. Max. Units Conditions Supply voltage, Vcc 6, 12, 17, 19, -0.3 6 V RF input voltage 9, 10 117 dBuV Differential, AC coupled inputs All I/O port DC offsets -0.3 Vcc+0.3 V SDA, SCL DC offsets 3, 4 -0.3 6 V Vcc = Vee to 5.25 V Storage temperature -55 150 °C Junction temperature 125 °C Power applied. Package thermal resistance, chip to case (SSOP) 20 °C/W Package thermal resistance, chip to ambient (SSOP) 85 °C/W Power consumption at 5.25 V 630 mW Maximum power setting. ESD protection (pins 3-28) 1 kV Mil-std 883B method 3015 cat1 ESD protections (pins 1, 2) 0.75 kV

Zarlink Semiconductor Inc. Figure 30 - Input and Output Interface Circuits (RF section) RF inputs Oscillator inputs IF outputs

Zarlink Semiconductor Inc. Figure 31 - Input and Output Interface Circuits (PLL section) Vccd 120K Vccd Vccd * On SDA only 200µA 1mA Output port BUFREF output SDA/SCL (pins 3 and 4) ADD input Reference oscillator Loop amplifier

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