SL20T0081 SLS | Alldatasheet
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SLS System Logic Semiconductor SL20T0081
81 COMMON x 132 SEGMENT STN LCD DRIVER / CONTROLLER
SLS System Logic Semiconductor SL20T0081 INTRODUCTION The SL20T0081 is a single -chip graphic dot -matrix liquid crystal display driver & controller that can be co nnected directly to a microprocessor bus. 8 -bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crysta l drive signal independent of the micro-processor. The SL20T0081 contains 81x132 bits of display data RAM and there is a 1 -to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, and the device contains 81 common output circuits and 132 segment output circuits, so that a single chip can drive a 81x132 dot display (capable of displaying 8 columns x 5 rows of a 16 x 16 dot font). Moreover, the capacity of the display can be extended through the use of master/ slave structures between chips. The chips are able to minimize power consumption because no exte rnal operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low -power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock RC oscillator circuit, the SL20T0081 Series chips can be used to create the lowest power display sys tem with the fewest components for high performance portable systems. Direct display of RAM data through the display data RAM. RAM capacity : 81x132 = 8580 bits
FEATURES
RAM bit data : “1” Non-illuminated “0” illuminated (during normal display) High-speed 8-bit MPU interface The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs. Serial interface available (supports write operation only). Abundant command functions Display data Read/Write,display ON/OFF, Normal/Reverse display m ode, page address set, display start line set, column address set, status read, display all point ON/OFF, LCD b ias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. Static drive circuit equipped internally for indicators 1 driver, with 4 kinds of flashing mode Duty LCD Driver Bias Maximum display matrix 1/81 1/10 or 1/8 81 x 132 1/65 1/9 or 1/7 65 x 132 1/55 1/8 or 1/6 55 x 132 1/49 1/8 or 1/6 49 x 132 1/33 1/6 or 1/5 33 x 132 OVERVIEW DEVICE SPECIFICATION Table 1. Duty and Bias selection
SLS System Logic Semiconductor SL20T0081 Built-in Power Supply Circuit Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of x2 / x3 / x4 / x5, where the step-up voltage reference power supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/o C or external input). LCD driver voltage regulator resistors and voltage followers equipped internally. RC oscillator circuit equipped internally (external clock can also be selected). Operating Voltage Range Supply Voltage (VDD) : 2.4V ~ 3.6V LCD driver Voltage (VLCD) : 4.5V ~ 16.0V Low Power Consumption Operating power : 40uA typical (conditions:VDD =3V, x 4 boosting (VCI = VDD ), V0 =11V, Internal power supply ON,display OFF and normal mode is selected ) Standby power : 10uA maximum (during power save [standby] mode) Operating Temperatures Wide range of operating temperatures : -40 to 85o C CMOS Process Package Type TCP
SLS System Logic Semiconductor SL20T0081 VDD VSS CAP1+ CAP1- CAP2+ CAP2- CAP3+ VOUT VEXT VR IREF IRE HPMB SEG Drivers COM Drivers Power Supply Circuit Display Data Memory 81 x 132 bits Display Data Read Circuit Column Address Decoder Row Address Decoder Timing Generation Read/Write Circuit COMSOscillation Circuit Command Decoder MPU Interface Status CE1 CE2 RS RD (E) P68/86 PS WR (R/W) D7 (SI) D6 (SCK) CLS MS DISP CL SYNC FRS SEG0 SEG131 COM40 COM79 COMS CAP4+ DUTY0 DUTY1 VCI FR RESET COM Drivers COM0 COM39 DUTY2 BLOCKDIAGRAM
SLS System Logic Semiconductor SL20T0081 PAD CENTER COORDINATES PAD PAD PAD PAD No. name No. name
1 DUMMY5 -4121 -1411 57 CAP1- 540 -1411
2 DUMMY6 -3990 -1411 58 CAP1+ 620 -1411
3 DUMMY7 -3930 -1411 59 CAP1+ 700 -1411
4 DUMMY8 -3870 -1411 60 CAP2+ 780 -1411
5 DUMMY9 -3810 -1411 61 CAP2+ 860 -1411
6 DUMMY10 -3750 -1411 62 CAP2- 940 -1411
7 DUMMY11 -3690 -1411 63 CAP2- 1020 -1411
8 DUMMY12 -3630 -1411 64 VDD 1100 -1411
9 DUMMY13 -3570 -1411 65 VEXT 1180 -1411
10 DUMMY14 -3510 -1411 66 IREF 1260 -1411
11 FRS -3420 -1411 67 TEST_VREF 1340 -1411
12 FR -3340 -1411 68 VSS 1420 -1411
13 SYNC -3260 -1411 69 V1 1500 -1411
14 CL -3180 -1411 70 V1 1580 -1411
15 DISP -3100 -1411 71 V2 1660 -1411
16 VDD -3020 -1411 72 V2 1740 -1411
17 VSS -2940 -1411 73 V3 1820 -1411
18 CE1 -2860 -1411 74 V3 1900 -1411
19 CE2 -2780 -1411 75 V4 1980 -1411
20 VDD -2700 -1411 76 V4 2060 -1411
21 RESETB -2620 -1411 77 V0 2140 -1411
22 RS -2540 -1411 78 V0 2220 -1411
23 VSS -2460 -1411 79 VR 2300 -1411
24 WR(R/W) -2380 -1411 80 VR 2380 -1411
25 RD(E) -2300 -1411 81 VSS 2460 -1411
26 VDD -2220 -1411 82 VSS 2540 -1411
27 D<0> -2140 -1411 83 VDD 2620 -1411
28 D<1> -2060 -1411 84 MS 2700 -1411
29 D<2> -1980 -1411 85 CLS 2780 -1411
30 D<3> -1900 -1411 86 VSS 2860 -1411
31 D<4> -1820 -1411 87 P68/80 2940 -1411
32 D<5> -1740 -1411 88 PS 3020 -1411
33 D<6> -1660 -1411 89 VDD 3100 -1411
34 D<7> -1580 -1411 90 HPMB 3180 -1411
35 VSS -1500 -1411 91 VSS 3260 -1411
36 VDD -1420 -1411 92 IRE 3340 -1411
37 DUTY0 -1340 -1411 93 VDD 3420 -1411
38 DUTY1 -1260 -1411 94 TRCON 3510 -1411
39 VDD -1180 -1411 95 VSS 3570 -1411
40 VSS -1100 -1411 96 TRIM<4> 3630 -1411
41 DUTY2 -1020 -1411 97 TRIM<3> 3690 -1411
42 VDD -910 -1411 98 VSS 3750 -1411
43 VDD -790 -1411 99 TRIM<2> 3810 -1411
44 VDD -670 -1411 100 TRIM<1> 3870 -1411
45 VCI -560 -1411 101 VSS 3930 -1411
46 VCI -480 -1411 102 TRIM<0> 3990 -1411
47 VSS -370 -1411 103 DUMMY15 4121 -1411
48 VSS -250 -1411 104 DUMMY16 4361 -1250
49 VSS -130 -1411 105 COM<39> 4361 -1190
50 VOUT -20 -1411 106 COM<38> 4361 -1130
51 VOUT 60 -1411 107 COM<37> 4361 -1070
52 CAP4+ 140 -1411 108 COM<36> 4361 -1010
53 CAP4+ 220 -1411 109 COM<35> 4361 -950
54 CAP3+ 300 -1411 110 COM<34> 4361 -890
55 CAP3+ 380 -1411 111 COM<33> 4361 -830
56 CAP1- 460 -1411 112 COM<32> 4361 -770
SLS System Logic Semiconductor SL20T0081 PAD CENTER COODINATES (continued) PAD PAD PAD PAD No. name No. name
113 COM<31> 4361 -710 169 SEG<20> 2730 1411
114 COM<30> 4361 -650 170 SEG<21> 2670 1411
115 COM<29> 4361 -590 171 SEG<22> 2610 1411
116 COM<28> 4361 -530 172 SEG<23> 2550 1411
117 COM<27> 4361 -470 173 SEG<24> 2490 1411
118 COM<26> 4361 -410 174 SEG<25> 2430 1411
119 COM<25> 4361 -350 175 SEG<26> 2370 1411
120 COM<24> 4361 -290 176 SEG<27> 2310 1411
121 COM<23> 4361 -230 177 SEG<28> 2250 1411
122 COM<22> 4361 -170 178 SEG<29> 2190 1411
123 COM<21> 4361 -110 179 SEG<30> 2130 1411
124 COM<20> 4361 -50 180 SEG<31> 2070 1411
125 COM<19> 4361 10 181 SEG<32> 2010 1411
126 COM<18> 4361 70 182 SEG<33> 1950 1411
127 COM<17> 4361 130 183 SEG<34> 1890 1411
128 COM<16> 4361 190 184 SEG<35> 1830 1411
129 COM<15> 4361 250 185 SEG<36> 1770 1411
130 COM<14> 4361 310 186 SEG<37> 1710 1411
131 COM<13> 4361 370 187 SEG<38> 1650 1411
132 COM<12> 4361 430 188 SEG<39> 1590 1411
133 COM<11> 4361 490 189 SEG<40> 1530 1411
134 COM<10> 4361 550 190 SEG<41> 1470 1411
135 COM<9> 4361 610 191 SEG<42> 1410 1411
136 COM<8> 4361 670 192 SEG<43> 1350 1411
137 COM<7> 4361 730 193 SEG<44> 1290 1411
138 COM<6> 4361 790 194 SEG<45> 1230 1411
139 COM<5> 4361 850 195 SEG<46> 1170 1411
140 COM<4> 4361 910 196 SEG<47> 1110 1411
141 COM<3> 4361 970 197 SEG<48> 1050 1411
142 COM<2> 4361 1030 198 SEG<49> 990 1411
143 COM<1> 4361 1090 199 SEG<50> 930 1411
144 COM<0> 4361 1150 200 SEG<51> 870 1411
145 COMSR 4361 1210 201 SEG<52> 810 1411
146 DUMMY17 4361 1270 202 SEG<53> 750 1411
147 DUMMY18 4121 1411 203 SEG<54> 690 1411
148 DUMMY19 3990 1411 204 SEG<55> 630 1411
149 SEG<0> 3930 1411 205 SEG<56> 570 1411
150 SEG<1> 3870 1411 206 SEG<57> 510 1411
151 SEG<2> 3810 1411 207 SEG<58> 450 1411
152 SEG<3> 3750 1411 208 SEG<59> 390 1411
153 SEG<4> 3690 1411 209 SEG<60> 330 1411
154 SEG<5> 3630 1411 210 SEG<61> 270 1411
155 SEG<6> 3570 1411 211 SEG<62> 210 1411
156 SEG<7> 3510 1411 212 SEG<63> 150 1411
157 SEG<8> 3450 1411 213 SEG<64> 90 1411
158 SEG<9> 3390 1411 214 SEG<65> 30 1411
159 SEG<10> 3330 1411 215 SEG<66> -30 1411
160 SEG<11> 3270 1411 216 SEG<67> -90 1411
161 SEG<12> 3210 1411 217 SEG<68> -150 1411
162 SEG<13> 3150 1411 218 SEG<69> -210 1411
163 SEG<14> 3090 1411 219 SEG<70> -270 1411
164 SEG<15> 3030 1411 220 SEG<71> -330 1411
165 SEG<16> 2970 1411 221 SEG<72> -390 1411
166 SEG<17> 2910 1411 222 SEG<73> -450 1411
167 SEG<18> 2850 1411 223 SEG<74> -510 1411
168 SEG<19> 2790 1411 224 SEG<75> -570 1411
SLS System Logic Semiconductor SL20T0081 PAD CENTER COODINATES (continued) PAD PAD PAD PAD No. name No. name
225 SEG<76> -630 1411 281 DUMMY1 -3990 1411
226 SEG<77> -690 1411 282 DUMMY2 -4121 1411
227 SEG<78> -750 1411 283 DUMMY3 -4361 1270
228 SEG<79> -810 1411 284 COM<40> -4361 1210
229 SEG<80> -870 1411 285 COM<41> -4361 1150
230 SEG<81> -930 1411 286 COM<42> -4361 1090
231 SEG<82> -990 1411 287 COM<43> -4361 1030
232 SEG<83> -1050 1411 288 COM<44> -4361 970
233 SEG<84> -1110 1411 289 COM<45> -4361 910
234 SEG<85> -1170 1411 290 COM<46> -4361 850
235 SEG<86> -1230 1411 291 COM<47> -4361 790
236 SEG<87> -1290 1411 292 COM<48> -4361 730
237 SEG<88> -1350 1411 293 COM<49> -4361 670
238 SEG<89> -1410 1411 294 COM<50> -4361 610
239 SEG<90> -1470 1411 295 COM<51> -4361 550
240 SEG<91> -1530 1411 296 COM<52> -4361 490
241 SEG<92> -1590 1411 297 COM<53> -4361 430
242 SEG<93> -1650 1411 298 COM<54> -4361 370
243 SEG<94> -1710 1411 299 COM<55> -4361 310
244 SEG<95> -1770 1411 300 COM<56> -4361 250
245 SEG<96> -1830 1411 301 COM<57> -4361 190
246 SEG<97> -1890 1411 302 COM<58> -4361 130
247 SEG<98> -1950 1411 303 COM<59> -4361 70
248 SEG<99> -2010 1411 304 COM<60> -4361 10
249 SEG<100> -2070 1411 305 COM<61> -4361 -50
250 SEG<101> -2130 1411 306 COM<62> -4361 -110
251 SEG<102> -2190 1411 307 COM<63> -4361 -170
252 SEG<103> -2250 1411 308 COM<64> -4361 -230
253 SEG<104> -2310 1411 309 COM<65> -4361 -290
254 SEG<105> -2370 1411 310 COM<66> -4361 -350
255 SEG<106> -2430 1411 311 COM<67> -4361 -410
256 SEG<107> -2490 1411 312 COM<68> -4361 -470
257 SEG<108> -2550 1411 313 COM<69> -4361 -530
258 SEG<109> -2610 1411 314 COM<70> -4361 -590
259 SEG<110> -2670 1411 315 COM<71> -4361 -650
260 SEG<111> -2730 1411 316 COM<72> -4361 -710
261 SEG<112> -2790 1411 317 COM<73> -4361 -770
262 SEG<113> -2850 1411 318 COM<74> -4361 -830
263 SEG<114> -2910 1411 319 COM<75> -4361 -890
264 SEG<115> -2970 1411 320 COM<76> -4361 -950
265 SEG<116> -3030 1411 321 COM<77> -4361 -1010
266 SEG<117> -3090 1411 322 COM<78> -4361 -1070
267 SEG<118> -3150 1411 323 COM<79> -4361 -1130
268 SEG<119> -3210 1411 324 COMSL -4361 -1190
269 SEG<120> -3270 1411 325 DUMMY4 -4361 -1250
270 SEG<121> -3330 1411
271 SEG<122> -3390 1411
272 SEG<123> -3450 1411
273 SEG<124> -3510 1411
274 SEG<125> -3570 1411
275 SEG<126> -3630 1411
276 SEG<127> -3690 1411
277 SEG<128> -3750 1411
278 SEG<129> -3810 1411
279 SEG<130> -3870 1411
280 SEG<131> -3930 1411
SLS System Logic Semiconductor SL20T0081 Power Supply Pins LCD Power Supply Circuit Pins Pin Name I/O Function VDD Power Supply Positive Power Supply. VSS Power Supply System Ground. VCI Power Supply Voltage Booster input pin. The power supply for the voltage booster. VCI input voltage is the reference of boosted output voltage (VOUT) of voltage booster. Power Supply LCD driver supply voltage pins. When the internal LCD power supply circuit is enabled, these voltages are generated by it. When the internal LCD power supply circuit is disabled, these voltages must be supplied externally, and they should have the following relationship. VSS < V4 < V3 < V2 < V1 < V0 PIN DESCRIPTION Pin Name I/O Function CAP1+ O Voltage booster pin. Connect a capacitor between this pin and the CAP1- pin CAP1- O Voltage booster pin. Connect a capacitor between this pin and the CAP1+ pin CAP2+ O Voltage booster pin. Connect a capacitor between this pin and the CAP2- pin CAP2- O Voltage booster pin. Connect a capacitor between this pin and the CAP2+ pin CAP3+ O Voltage booster pin. (refer the application example to connecting a capacitor) VOUT O Voltage booster pin. Connect a capacitor between this pin and VSS. VEXT I This is the external reference voltage input pin of the LCD power supply circuit. This pin is valid only when internal reference voltage circuit is disabled (IREF=0). CAP4+ O Voltage booster pin. (refer the application example to connecting a capacitor) IRE I Internal voltage regulator resistor enable pin. This pin selects the resistors for the V0 voltage level adjustment. IRE = 1 : Use the internal resistors IRE = 0 : Do not use the internal resistors. The V0 voltage level is controlled by the external resisters that connected among V0 pin and VR pin and VSS. VR I External V0 voltage adjustment pin. VR pin is valid only when the internal voltage regulator resistors are not used (IRE=0) IREF I Internal reference voltage circuit enable pin. IREF = 0 : Internal reference voltage circuit is disabled. External reference voltage is inputted via VEXT pin. IREF = 1 : Internal reference voltage circuit is enabled.
SLS System Logic Semiconductor SL20T0081 System Control pins Pin Name I/O Function MS I This pin selects the master/slave operation for the SL20T0081 chip. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display. MS = 1 : Master operation MS = 0 : Slave operation Following table shows difference of the master operation and the slave operation. MS Internal Oscillator Circuit Enabled Disabled CLS
0 Disabled-
Disabled Input Input Input CL I/O This is the display clock input/output pin. When multiple SL20T0081 chips are used in master/slave mode, all of CL pins must be connected each other. DISP I/O This is the liquid crystal display blanking control pin. When multiple SL20T0081 chips are used in master/slave mode, all of DISP pins must be connected each other. HPMB I This is the power control pin for the power supply circuit for liquid crystal drive. HPMB = 1 : Normal mode HPMB = 0 : High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either 0 or 1 when the slave operation mode is selected. CLS I Internal RC oscillator enable pin. CLS = 1 : Internal oscillator circuit is enabled. CLS = 0 : Internal oscillator circuit is disabled. When CLS=0, the display clock must be inputted through the CL pin. This pin is valid only when SL20T0081 operating in master operation. SYNC I/O LCD synchronization signal input/output pin. When multiple SL20T0081 chips are used in master/slave mode, all of SYNC pins must be connected each other. DUTY0 DUTY1 DUTY2 I The LCD driver duty ratio selection pins. DUTY1 DUTY0 Duty ratio 0 0 1/33 DUTY2 1 1 1/811 Common Output normal Even, Odd When Duty = (1, 1, 1), 1/81 duty ratio is selected, and common o utput pin configuration is changed. At this mode, all even numbered common output pins are outputting right side of the device and all odd numbered common output pins are outputtin g left side of the device.
SLS System Logic Semiconductor SL20T0081 System Interface pins Pin Name I/O Function D7 ~ D0 (SI) (SCK) I/O 8bit bi-directional data bus that should be connected to the standard MPU data bus. When PS=0 the serial interface is enabled and pins are set as following. D7 : Serial data input (SI) D6 : Serial interface clock input (SCK) D5 ~ D0 : high impedance state When the chip does not be selected, D7 ~ D0 are set to high impedance. RS I Display data / Control data selection signal input pin RS = 1 : D7 ~ D0 input are display data RS = 0 : D7 ~ D0 input are control data RESET I Device Reset pin. When RESET = 0, device initialization operation is executed. CE1 CE2 I Chip Select signal input pins When CE1 = 0 and CE2 = 1, then the chip select becomes active, and data/command I/O is enabled. RD (E) I
- When the device connected to an 8080 MPU bus, this pin acts as “active LOW”read signal input pin. If the device is selected and RD = 0, then SL20T0081 outputs the data to data bus pins.
- When the device connected to a 6800 MPU bus, this pin acts as “active HIGH”R/W enable signal input pin. If the device is selected and RD = 1, then SL20T0081 executes read or write operation that controlled by WR signal. WR (R/W) I
- When the device connected to an 8080 MPU bus, this pin acts as “active LOW”write signal input pin. If the device is selected and WR = 0, then SL20T0081 accepts the data via data bus pins.
- When the device connected to a 6800 MPU bus, this pin acts as read/write control signal input pin. WR(R/W) = 1 : Read WR(R/W) = 0 : Write P68/80 I Bus type selection pin. P68/80 = 1 : 6800 MPU bus type interface. P68/80 = 0 : 8080 MPU bus type interface PS I Parallel data transfer / Serial data transfer mode selection pin. PS = 1 : Parallel data transfer mode. PS = 0 : Serial data transfer mode. When PS = 0, RD(E) and WR(R/W) pins are fixed to either 0 or 1. PS Data transfer mode Data busRead SCK pinWrite
1 Parallel data transfer D7 ~D0enabled -enabled
0 Serial data transfer D7 (SI)disabled D6 (SCK)enabled
SLS System Logic Semiconductor SL20T0081 Liquid Crystal Drive Pins LCD common driver output pins. Common driver output voltage is controlled by internal scanning data and FR signal. Pin Name I/O Function SEG0 SEG131 O LCD segment driver output pins. Segment driver output voltage is controlled by display data and FR signal. Display data FR Segment driver output voltage Normal Display Reverse Display 1 0 VSS V3 0 0 V3 VSS 1 1 V0 V2 0 1 V2 V0 Power save VSS COM0 COM79 O COMS(R) COMS(L) O Common drive output for the icons. There are two COMS pin, COMS( R), COMS(L). They output same signal. When in master/slave mode, the same sig nal is output by both master and slave. Scan Data FR 1 0 0 1 0 0 Power save mode Common driver output voltage VSS VSS FR O Static segment driver output pin. This pin is paired with FRS pin. FRS O Static segment driver output pin. This pin is paired with FR pin.
SLS System Logic Semiconductor SL20T0081 MICROPROCESSOR INTERFACE Chip Select Input There are CE1 and CE2 pins for chip selection. The SL20T0081 can interface with an MPU only when CE1 is “L”and CE2 is “H”. When these pins are set to any other combination, RS, RDB(E) a nd_WRB(RW) inputs are disabled and D0to D7 are to be high impedance. And, in case of serial interfa ce, the internal shift register and the counter are reset. Parallel / Serial Interface SL20T0081 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial inter face is determined by PS pin. Table 3. Parallel / Serial Interface Mode in table 4. The type of data transfer is determined by signals at RS, RD(E) and WR(R/W) as shown in table 5. Table 4. Microprocessor Selection for Parallel Interface Table 5. Parallel Data Transfer
Description
L L H H H L L H H L Display data read out Display data write Register status read Writes to internal register (instruction) PS Type CE1 P68/80 Interface mode 6800-series MPU mode L 8080-series MPU mode CE2CE1ParallelH L Serial CE1 CE2 *x Serial-mode CE2 H *x :Don’t care
and caused by the line length, the operation check on the actual machine is recommended. needs not to check this flag before each instruction, which improves the MPU performance. Figure 3. Serial Interface Timing
after the address sets, but can be output at the second read of data. Figure 4. Write Timing
Figure 5. Read Timing
Figure 8. Display Data RAM Map (1/81, 1/65 duty mode)
from the display clock. 2 -frame AC driver waveforms with internal timing signal are shown in figure 8. shows the SYNC, CL, and DISP status. Table 6. Master and Slave Timing Signal Status
instruction specifies the scanning direction of the common output pins. Table 7. The Relationship between Duty Ratio and Common Output
to “Instruction Description”. Table 8 shows the referenced combinations in using Power Supply circuits. Table 8. Recommended Power Supply Combinations
Figure 9. Power supply circuits for various voltage boosting
amplifier circuits showing Figure 10, it is necessary to be applied internally or externally. Table 9. VREF Voltage at Ta = 25o Table 10. Electronic Contrast Control Register (64 Steps)
Figure 10. Internal Voltage Regulator Circuit
V0 and VR. We determine V0 by two instructions, “Regulator Resistor Select”and “Set Reference Voltage”. Table 11. Internal Rb/Ra ratio depending on 3-bit data (R2 R1 R0) Figure 11. Electronic Volume Level
- LCD driver voltage, V0 = 10V
- 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
- Maximum current flowing Ra, Rb = 1uA
The following table shows the range of V0 depending on the above requirements. Table 12. V0 Depending on Electronic Volume Level
V1 to V level and each duty ratio. Table 13. The Relationship between V1 to V4 Level and Duty Ratio degrade. When this occurs, setting the HPMB pin to “L”(high power mode) can improve the quality of the display. a liquid crystal drive power supply externally ( VOUT or V0 or V1, V2, V3, V4 ).
SLS System Logic Semiconductor SL20T0081 RESET CIRCUIT Setting RESET to “L”or Reset instruction con internal function. When RESET becomes “L”, following procedure is occurred. Display ON/OFF: OFF All segments ON/OFF: OFF(normal) ADC select: OFF(normal) Reverse display ON/OFF: OFF(normal) Power control register (VC, VR, VF) = (0,0,0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF(normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (VR5, VR4, VR3, VR2, VR1, VR0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, following procedure is occurred. Read-modify-write: OFF Static indicator mode: OFF Static indicator register:(S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage control register: (VR5, VR4, VR3, VR2, VR1, VR0) = (1, 0, 0, 0, 0, 0) Test mode release While RESET is “L”or Reset instruction is executed,no instruction except read status could be accepted. Reset status appears at D4. After D4 becomes “L”, any instruction can be accepted. RESET must be connected to th e reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESET is essential before used.
Table 14. Instruction Table 0 1 0 1 0 1 0 1 0 0 0Display start line reset Reset the Display Start line. 0 1 0 1 0 1 0 1 0 1 0N-line inversion reset Reset the N-line inversion.
mode is controlled by 2’nd byte. instructions set display off and all segments on. Table 15. Instruction Table (continued)
SLS System Logic Semiconductor SL20T0081 DON =1 : display ON DON =0 : display OFF RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 1 1 DON Display Start Line Set Sets the line address of display RAM to determine the Initial D isplay Line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 1 : : : : : : 1 1 1 1 1 0 631 1 1 1 1 1 Set Page Address Sets the Page Address of display data RAM from the microprocess or into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the page address doesn’t effect to display status. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 P3 P2 P1 P1 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 Display ON/OFF Turns the Display ON/OFF
SLS System Logic Semiconductor SL20T0081 Set Column Address Sets the Column Address of display RAM from the microprocessor into Column Address register. Along with the Column Address, the Column Address defines the address of the di splay RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 A7 A6 A5 A4 RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 Read Status Read the internal status of the SL20T0081. Set Column Address MSB Set Column Address LSB RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0 Flag Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy BUSY Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG131 SEGO), 1: normal direction (SEGO SEG131) ADC ON/OFF RESET Indicates display ON / OFF status. 0: display ON, 1: display OFF Indicates the initialization is progress by RESET signal. 0: chip is active, 1: chip is being reset
write data to the addressed page. after Read or Write operation. Figure 12. Sequence for Writing Display Data Figure 13. Sequence for Reading Display Data 8-bit data from display data RAM specified by the column address a nd page address can be read by this Instruction. address register. Display data cannot be read through the serial interface. pins can be reversed by software. This makes IC layout flexible in LCD module assembly.
SLS System Logic Semiconductor SL20T0081 RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal display EON = 1: entire display ON Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. Set Read-Modify-Write This instruction stops the automatic increment of the column ad dress by the read display data instruction,but the column address is still increased by the write display data inst ruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 0 0 Reverse Display ON / OFF Reverses the display status in LCD panel without rewriting the contents of the display data RAM. All segments ON / OFF Forces the whole LCD points to be turned on regardless of the co ntents of the display data RAM.At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 0 1 Bias LCD bias Bias = 0 DUTY0DUTY1Duty ratio Bias = 1 1/33 0 0 1/6 1/5 1/49 0 1 1/8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/9 1/7 1/81 0 0 1/10 1/8 DUTY2
before the set Read-Modify-Write instruction is started. Figure 14. Sequence for Cursor Display supply, which is initialized by the RESET pin.
SLS System Logic Semiconductor SL20T0081 Common Output Direction (COD) set COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 SHL x x x COD = 0: normal direction ( COM0 COM79 ) COD = 1: reverse direction ( COM79 COM0 ) Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. X: Don’t care RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Regulator Resistor Select Selects resistance ratio of the internal resistor used in the i nternal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 (1+ Rb / Ra) ratio 3.0000 0 0 1 0 01 0 1 3.5 4.0 4.5 5.0 (default) 5.5 6.0 6.4
reference voltage register. After second instruction, reference voltage mode is released. Figure 15. Sequence for Setting the Reference Voltage
SLS System Logic Semiconductor SL20T0081 Set Static Indicator State Consists of two bytes instruction. The first byte instruction ( set Static Indicator Mode) enables the second byte instruction (set Static Indicator Register) to be valid. The first byte sets the static indicator ON /OFF. When it is on, the second byte updates the contents of static indicator register wi thout issuing any other instruction and this Static Indicator state is released after setting the data of indicator register. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 1 0 SM The 2nd Instruction : Set Static Indicator Register RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 x x x x x x S0S1 The 1st Instruction : Set Static Indicator Mode (ON/OFF) SM = 0: static instruction OFF SM = 1: static instruction ON S0S1 Status of static indicator output
00 OFF
10 ON (about 1 second blinking)
1 0 ON (about 0.5 second blinking) 1 1 ON (always ON) NOP Non Operation Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 1 1 Test Instruction (Test Instruction_1 &Test Instruction_2) Thee are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident,it can be cleared by applying “0”signal to the RESET input pin or the reset instruction. RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 1 x x xx 0 0 1 0 0 1 x x xx
Figure 16. Power Save (Compound Instruction) a. The oscillator circuit and LCD power supply circuit are halted. b. All liquid crystal drive circuit are halted, and the segment in common drive outputs a VSS level. operate, providing the minimum required consumption current for the static drive. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate.
2 Bytes Command
Figure 17. Initializing with the Built-in Power Supply Circuits
Figure 18. Initializing without the Built-in Power Supply Circuits
Figure 19. Data Display setup
Figure 20. Power OFF
Figure 21. Relations between powers and V voltages
- VDD and VLCD are based on VSS = 0V.
- Voltages V0 > V1> V2 > V3 > V4 > VSS must always be satisfied. (VLCD = V0 - VSS)
- If supply voltage exceeds its absolute maximum range,this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. Table 16. Absolute Maximum Ratings
Table 17. DC Characteristics
SLS System Logic Semiconductor SL20T0081 (VSS = 0V, VDD =2.4 to 3.6V, Ta =-40 to 85o C)Table 18. DC Characteristics (continued) x2 -2.4 3.6 x3 -2.4 3.6 x4 -2.4 3.6 V x5 -2.4 3.2 VVVoltage converter input voltage Voltage converter output voltage VOUT X2 /x3 /x4 /x5 voltage conversion (no-load) 95 99 - % VOUT Voltage regulator operating voltage VOUT 6.0 16.0- V VOUT Voltage regulator operating voltage V0 4.5 15.0- V V0 *9 Reference voltage VREF 2.1 2.16 VTa=25o C (-0.05%/o C) 2.04 Item Symbol Condition Condition Min. Typ. Max. Units Pin
Table 19. Dynamic Current Consumption (1) Table 20. Dynamic Current Consumption (2) Table 21. Current Consumption during Power Save Mode (Ta =25o
Table 22. The Relationship between Oscillation Frequency and Frame Frequency assurance during access from the MPU. *2. In case of external power supply is applied. *4. D0 to D7, SYNC, FR, DISP, CL pins. *6. Applies when the DB[7:0], SYNC, FR, DISP, and CL pins are in high impedance. *8. See table 22 for the relationship between oscillation frequency and frame frame frequency. *10.On-chip reference voltage source of the voltage regulator circuit to adjust V0.
Figure 22. Read/Write Characteristics (8080-series Microprocessor) Table 23. Read/Write Characteristics (8080-series Microprocessor)
Figure 23. Read/Write Characteristics (6800-series Microprocessor) Table 24. Read/Write Characteristics (6800-series Microprocessor)
Figure 24. Serial Interface Characteristics Table 25. Serial Interface Characteristics
SLS System Logic Semiconductor SL20T0081 REFERENCE APPLICATIONS MS IRE VCI VSS VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD +-C2 +-C2 +-C2 +-C2 +-C2 Example 1 : When using internal LCD power circuit (4-time voltage boost / VCI = VDD) (a) Using internal voltage regulator resistors (IRE=1) MS IRE VCI VSS VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD +-C2 +-C2 +-C2 +-C2 +-C2 (b) Using external voltage regulator resistors (IRE=0) Ra Rb MS IRE VCI VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD +-C2 +-C2 +-C2 +-C2 +-C2 Example 2 : Using Internal LCD power circuit (not using voltage booster circuit) MS IRE VCI VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD +-C2 +-C2 +-C2 +-C2 +-C2 (d) Using external voltage regulator resistors (IRE=0) Ra Rb External Power Supply External Power Supply LCD power supply configuration (c) Using internal voltage regulator resistors (IRE=1) VSS VSS VSS VSS VSSVSS
SLS System Logic Semiconductor SL20T0081 MS IRE VCI VSS VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD +-C2 +-C2 +-C2 +-C2 +-C2 Example 3 : Using Internal LCD power circuit (Only use voltage follower ci rcuit) MS IRE VCI VOUT C4+ C3+ C1- C1+ C2+ C2- VR VDD Example 4 : Using External LCD power supply External Power Supply External Power Supply
Figure 27. Data transfer interface