SL1935

SL1935 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

Single chip synthesised tuner solution for quadrature down conversion, L-band to Zero IF . DVB compliant, operating dynamic range -70 to -20dBm. Compatible with DSS and DVB variable symbol rate applications. Selectable baseband path, programmable through I 2C bus. Excellent quadrature balance up to 30MHz baseband Excellent immunity to spurious second harmonic (RF and LO) mixing effects. Low oscillator phase noise and reradiation. High output referred linearity for low distortion and multi channel application. Integral fast mode compliant I 2C bus controlled PLL frequency synthesiser, designed for high comparison frequencies and low phase noise performance. Buffered crystal output for clocking QPSK demodulator. ESD protection (Normal ESD handling procedures should be observed).

Applications

Satellite receiver systems. Data communications systems. Figure 1. Pin connections 361 18 19 XT ALCAP XT AL SDA SCL BUFREF VCCD VCC RF RFB VCC IFIA IFIB VCC OFIA OFIB VEE IOUT ADD PUMP DRIVE POR T P0 VEE T ANKS T ANKSB VEE T ANKV T ANKVB VEE IFQA IFQB VCC OFQA OFQB VEE QOUT AGCCONT

Description

The SL1935 is a complete single chip bus controlled Zero IF tuner and operates from 950 to 2150MHz. It includes an on-board low phase noise PLL frequency synthesiser and low noise LNA/AGC. The SL1935 is intended primarily for application in digital satellite Network Interface Modules and performs the complete tuner function. The device contains all elements necessary, with the exception of local oscillator tuning network and crystal reference, to produce a high performance I(n-phase) & Q(uadrature) downconversion tuner function. Due to the high signal handling design the device does not require any front end tracking filters. The SL1935 includes selectable baseband signal paths, allowing application with two externally definable filter bandwidths, facilitating application in variable symbol rate and simulcast systems. The SL1935 is optimised to interface with the VP310 (ADC/QPSK/FEC) Satellite Channel Decoder, available from Zar link Semiconductor and offers a full front end solution. I SL1935 Single Chip Synthesized Zero IF Tuner April 2004

Ordering Information

SL1935D/KG/NP1P (Tubes) 36 pin SSOP SL1935D/KG/NP1Q (Tape and Reel) 36 pin SSOP Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.

Figure 2. Block diagram Frequency Agile Phase Splitter AG C Sender Divide by 2 15 bitProgrammable Divider I2C Bus Interface Charge Pump Reference Divider VCC 7,10,13,24 VCCD VEE 16,21,27,30,33 AGCCONTRF8RFB9 TANKS 32 TANKSB 31 TANKV 29 TANKVB 28 SDA 3 SCL 4 ADD 18 XTAL 2 XTALCAP 1

5 BUFREF

34 PORT P0

35 DRIVE

36 PUMP

15 OFIB

14 OFIA

12 IFIB

11 IFIA

17 IOUT

20 QOUT

26 IFQA

25 IFQB

23 OFQA

22 OFQB

Table 1. Quick Reference Data are required to complete the tuner system. allocations are shown in Figure 1. guarantee an operating dynamic range of -70 to -20dBm. and is then divided by two to provide 950 to 1500MHz. Note: 6dB interstage filter loss assumed in external base band paths. dBm assumes 75Ω characteristic impedance.

Quadrature Downconverter Section - continued The oscillators share a common varactor line drive and both require an external varactor tuned resonator optimised for low phase noise performance. The recommended application circuit for the local oscillators is detailed in Fig.9 and the typical phase noise performance is detailed in Fig.10. The local oscillator frequency is coupled internally to the PLL frequency synthesiser programmable divider input. The mixer outputs are coupled to the baseband buffer amplifiers, providing for one of two selectable baseband outputs in each channel. The required output is selected by bit BS in the I 2C bus transmission (Table 6). These outputs are fed off chip via ports ‘OPIA’ and ‘OPIB’ (‘OPQA’ and ‘OPQB’), then back on chip through ports ‘IPIA’ and ‘IPIB’ ( ‘IPQA’ and ‘IPQB’), allowing for the insertion of two independent user definable filter bandwidths. Each output provides a low impedance drive (Fig.11) and each input provides a high impedance load . An example filter for 30MS/s is detailed in Fig.13. Both path gains are nominally equal. NB 6dB insertion loss is assumed in each channel, however a different pot down ratio may be applied. Each baseband path is then multiplexed to the final baseband amplifier stage, providing further gain and a low impedance output drive. The nominal output load test condition is detailed in Fig.14. PLL Frequency Synthesiser Section The PLL frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and a loop filter to control the selected oscillator to produce a complete PLL frequency synthesised source. The device, produced using high speed logic, allows for operation with a high comparison frequency and enables the generation of a loop with excellent phase noise performance. The LO signal from the selected oscillator drives from the phase splitter into an internal preamplifier, providing gain and reverse isolation from the divider signals. The output of the preamplifier interfaces directly with the 15-bit fully programmable divider. The programmable divider has MN+A architecture, the dual modulus prescaler is 16/17, the A counter is 4-bits and the M counter is 11-bits. The output of the programmable divider is fed to the phase comparator and compared in both phase and frequency domains to the comparison frequency. This frequency is derived from either the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider, programmable into 1 of 29 ratios and detailed in Table 3. The typical application for the crystal oscillator is shown in Fig.15. The output of the phase detector feeds a charge pump and a loop amplifier. When used with an external loop filter and a high voltage transistor it integrates the current pulses into the varactor line voltage used to control the selected oscillator. The programmable divider output Fpd divided by two and the reference divider output Fcomp are switched to port P0 by programming the device into test mode. Test modes are detailed in Table 4. The crystal reference frequency can be switched to the BUFREF output by bit RE as detailed in Table 7. Programming The SL1935 is controlled by an I 2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed on the SDA and SCL lines respectively as defined by the I 2C bus format. The device can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 9a and 9b detail the format of the data. The SL1935 may be programmed to respond to several addresses and enables the use of more than one device in an I 2C bus system. Table 9c details the how the address is selected by applying a voltage to the ‘ADD’ input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal ‘STOP’ condition which inhibits further reading. Write mode Bytes 2 and 3 contain frequency information bits 2 14 to 20 inclusive (Table 9). Byte 4 controls the synthesiser reference divider ratio (Table 3) and the charge pump setting (Table 5). Byte 5 controls test modes (Table 4), baseband filter path select BS (Table 6), local oscillator select VS (Table 8), buffered crystal reference output select RE (Table 7) and the output port P0. After reception and acknowledgment of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as byte 2 or 4, a logic ‘0’ indicates byte 2 and a logic ‘1’ indicates byte 4. Having interpreted this byte as either byte 2 or 4, the following byte will be interpreted as byte 3 or 5 respectively. After receiving two complete data bytes, additional data bytes may be entered and byte interpretation follows the same procedure without re- addressing the device. The procedure continues until a ‘STOP’ condition is received.

received, or after the generation of a STOP condition. from the device takes the form shown in Table 9b. Function as described above. Function as described above. Function as described above. The charge pump current can be programmed by bits C1 & C0 (Table 5). The test modes are defined by bits T2 - T0 as described in Table 4. the ‘ON’ condition at device power up. a logic ‘0’ if the device is unlocked. The typical key performance data at Vcc = 5V and +25oC ambient are detailed in Table 1. Table 2. Programmable Features Table 3. Reference division ratios

Table 5. Charge pump current Table 6. Baseband path select Table 4. Test modes Table 7. Buffered crystal Table 8. Local oscillator select

Table 9a. Write data format (MSB is transmitted first) Table 9b. Read data format (MSB is transmitted first) Table 9c. Address selection Key to Tables 9a to 9c Note: * Programmed by connecting a 30kΩ resistor between pin and Vcc 0.50.2 10 +j0.2 +j0.5 +j1 +j2 +j5 — j5 — j2 — j1 — j0.5 — j0.2 STOP 2150MHz START 950MHz X X X X X 1 234 Normalised to 75 Ω Marker Freq (MHz) 950 1400 1600 2150 Z real Ω Z imag Ω -100 -75 -65 -45 Figure 3. RF input impedance (typical) Address Programmable divider Programmable divider Control data Control data MSB 214 213 LSB 212 VS 211 BS MA1 210 MA0 RE A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Address Status Byte MSB POR FL LSB MA1 MA0 A A Byte 1 Byte 2 MA1 MA0 Address input voltage level 0 - 0.1 Vcc Open circuit 0.4 Vcc - 0.6 Vcc*

0.9 Vcc - Vcc

Figure 13. Example baseband interstage filter for 30MS/s Figure 14. Nominal baseband output load test condition

1 XTALCAP

2 XTAL

Figure 15. Crystal oscillator application (typical)

Figure 16. Input matching network Table 10. Electrical Characteristics Test conditions (unless otherwise stated); Tamb = -20o to +80oC, Vee= 0V, Vcc =Vccd = 5V+-5%. temperature and supply voltage unless otherwise stated.

9 SL1935

System I and Q channel in band ripple System baseband path gain match LO second harmonic interference level LNA second harmonic interference level Synthesiser and other spurii on I and Q outputs In band leakage to RF input CONVERTER Converter input impedance Converter input return loss System input referred P1dB Converter output impedance, OFIA, OFIB, OPQA and OPQB. Converter output leakage to unselected output, OFIA, OFIB, OPQA and OPQB. Oscillator VCOS operating range Oscillator VCOV operating range Local oscillator SSB phase noise BASEBAND AMPLIFIERS Baseband input impedance, IFIA, IFIB, IFQA And IFQB. Resistance Capacitance Baseband unselected input leakage to output Baseband amplifier output impedance Baseband output limiting Baseband bandwidth 1dB Baseband output roll-off 17,20 17,20 17,20 17,20 8,9 8,9 8,9 14,15 22,23 31,32 28,29 11,12 25,26 17,20 17,20 17,20 17,20 -70 102 1900 1450 2.0 -50 -35 -60 -26 -78 3000 2150 -40 dBm dBm dB deg dB dB dBc dBc dBµV dBm Ω dB dBµV Ω dBc MHz MHz dBc/Hz kΩ pF dBc Ω Vp-p MHz dB/oct Note 6 AGCCONT = 0.75V -20 AGCCONT = 4.25V Interstage filter (Fig.13) Interstage filter (Fig.13) Interstage filter (Fig.13) Note 8. Note 9. Within 0-100MHz band under all gain settings, RF input set to deliver 108dBµV on output Within RF band 950-2150MHz. Note 11. With input matching (Fig.16) Converter gain =-5dBm (to OFIA/ OPQA, OFIB/OPQB outputs. Fig.7) 0.1 to 30MHz (Fig.11) Relative to selected output Giving LO = 950 to 1500MHz (Application as in Fig.9) (Application as in Fig.9) @10kHz offset, PLL loop bw < 1kHz Application is measured at baseband output frequency of 10MHz (Fig.10). 0.1- 30MHz bandwidth Relative to selected input. Level at hard clipping (load as Fig.14) (Load as Fig.14) Above 3dB point, no load Continued Table 10. Electrical Characteristics (Continued) System gain roll off System gain variation with temperature dB dB Within RF band 950-2150MHz -20˚C to +80˚C AGCONT input current µA19 -150 150 The baseband inputs must be externally ac coupled

Table 10. Electrical Characteristics (Continued) All power levels are referred to 75Ω, and 0dBm = 109dBµV. 6dB pad as interstage filter and load impedance as detailed in Figure 14. fc+155MHz at 100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included. 100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included. output intermodulation spur at 9MHz. 30MHz 3dB bandwidth interstage filter included. delivering 700mVp-p at baseband outputs (pins 17,20). AGC monotonic from Vee to Vcc (Fig.4). Port powers up in high impedance state. with the oscillator tuned to 2GHz, measured with no input pre-filtering. If the BUFREF output is not used it should be left open circuit or connected to Vccd, and disabled by settingRE = ‘0’. This parameter is very application dependant. With good RF isolation <-60dBm can be achieved.

Figure 17. Input and output interface circuits (RF section)

Figure 18. Input and output interface circuits (PLL section)

The supply connector is a 5 pin 0.1” pin header. The order of connections is 5V – GND – 30V – GND – 5V. (see Tables 8 and 9a to 9c). range 1500MHz to 2150MHz (approximately). which varies the AGCCONT input from 0V to Vcc. external AGC voltage source used. can now be manually tuned by varying the 30V supply. Table 11. Absolute Maximum Ratings (All voltages referred to Vee at 0V and Vcc = Vccd)

Figure 19. Top view

Figure 20. Bottom view

Figure 21. of XTALCAP XTAL SDA SCL BUFref VccD Vcc RFin RFinB Vcc IFIa IFIb Vcc OFIa OFIb Ve e Iout ADD AGC cont Qout Ve e OFQB OFQA Vcc IFQB IFQA Ve e TANKVb TANKVa Ve e TANKSb TANKSa Ve e PORT P0 DRIVE PUMP IC1 SL1935 TR1BCW31 C2715nF C2668pF R1913K R20 22K R1813K 30V L1 L2 L3 L4 D1 BB837 D2 BB837 BB831 D4 BB831 C252n2 R161K R17 1K GND XL14MHz C3 150pFC2 82pF SDA 5V0 GND SCL CN7I2C 5VD 5VD 5V C5 1nF 1nF RFinA 5V 100nF 100nF 100nF C10 100nF R31K R41K C113p9 C123p9 C24 100nF C23 100nF C22 100nF C21 100nF R14 R13 R111K R12 1K C193p9 C203p9 SK2 I OUT SK3 Q OUT SK1RF IN RFinA C13 220nFR5100R R61K C14 15pF IOUT IOUT C18220nF R10100R C17 15pF QOUT QOUT OFQB C1610nF AGC C3022uF C29100pF C28 100nF C32100pF C31100nF C36100nF C37100pF C3822uF 5VD 30V 5V C35100pF C34 100pF C33100pF D5PORT 0 R152K7 RV 15KR21620R R22620R 5VD AGC 12345 CN8DC POWER C39 100pF C40100pF TP8AG C R7 75R R232K R242K TP1 TP2 TP3 TP4 TP5 TP6 TP71 2 JP1

Purchase of Zarlink Semiconductor I2C components conveys a licence under the Phillips I2C Patent rights to use these components in an I2C system,provided that the system conforms to the I2C Standard Specification as defined by Phillips.

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