SL1466

SL1466 MITEL | Alldatasheet

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Technical content

FEATURES

n Single chip PLL system for wideband FM demodulation n Simple low component count application n Fully balanced low radiation design n High operating input sensitivity n 2 stage AGC detect for control over internal and external AGC stages n Low distortion video output drive n Video polarity invert n Digital AFC with window adjust n ESD protection (Normal ESD handling procedures should be observed)

ORDERING INFORMATION

Fig.1 Pin connections - top view The SL1466 is a wideband PLL FM demodulator, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of external local oscillator tank and loop filter components, to form a complete PLL system operating at 403 or 480MHz. An AFC system is provided, whose output signals can be used to correct for any frequency drift at the head end local oscillator.

APPLICATIONS

n Satellite receiver systems n Data communications systems Fig. 2 Block diagram 14 15

28 V CC

VIDEO – VIDEO FB– IF VCC IF IPB IF GND AGC TIME CONSTANT IF AGC SET RF AGC SET NC RF AGC CONTROL GND DIGF LO DIGF HI AFC SET AFC WINDOW OSC V CC OSC + OSC – OSC GND VCO GAIN SET VIDEO DRIVE VIDEO POL SELECT NC NC SL1466 QP28 IF IP AGC AMP IF IP NC NC RF AGC CONTROL NC AGC DETECT RF AGC SET AGC TIME CONST LO TANK VCO GAIN SET DIGF HI DIGF LO AFC WINDOW AFC SET VIDEO POLARITY VIDEO DRIVE VIDEO FB– VIDEO – VIDEO + VIDEO FB+ S/H AFC IF IPB Vcc GND 28 1 14 17 18 IF AGC SET 19 7 8 10 PHASE DETECTOR REF ON CHIP VCO SELECT SL1466 Wideband PLL FM Demodulator Preliminary Information DS 3979 2.2 August 1997

ELECTRICAL CHARACTERISTICS

TAMB = -20°C to +80°C, VCC = +4.75 to +5.25V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Pin Value Units Conditions Min Typ Max Supply current, Icc 6,23,28 65 mA RF Section Operating frequency 21, 22 480 MHz Input sensitivity 21, 22 -60 dBm At 27 °C Input overload 21, 22 0 -7 dBm Input Impedance 21, 22 75 Ω Internal AGC AMP range 50 dB VCO Section VCO dF/dV (Ko) 10 54 MHz/V VCO supply sensitivity 6,7,8,9 1.0 MHz/V At 27 °C VCO temperature sensitivity 7,8 0.05 MHz/ °C 0-55 °C, VCC =5V, 750ppmNTC, 0.5pF tuning cap. Video section Phase detector gain (Kd) 0.5 V/rad Differential loop filter Loop amplifier input 570 Ω R1 in note on loop parameters impedance Video drive output swing 11 0.9 Vp-p Into 75 Ω , 18MHz frequency deviation 11 1.8 Vp-p Into 1K Ω , 18MHz frequency deviation Video drive output 11 100 Ω At 27°C Impedance Video drive luminance non - linearity 11 2 % 75 Ω load Differential gain 11 ±2% 7 5 Ω load Differential phase 11 ±2 Deg 75 Ω load Tilt 11 1.0 % 75 Ω load Base line distortion 11 0.5 dB 75 Ω load Intermodulation 11 -46 -40 dB 75 Ω load, see note 1 Signal/noise 11 58 dB 75 Ω load, see note 2 Video polarity select input 12 V EE V Negative polarity Low Video polarity select input 12 V CC V Positive polarity High Video polarity switch 12 10 µAV CC =5.25V Vin=0V leakage current Video polarity switch 12 10 µAV CC =5.25V Vin=5.25V leakage current Positive to negative video 11 1 dB gain balance AFC section AFC window minimum 0.44 MHz Deadband measured at 90% of widths AFC high voltage AFC output high voltage 2,3 V CC -0.4 V CC V AFC output low voltage 2,3 0 0.4 V

NOTE: 1. Product of input modulation f1 at 4.43MHz p-p deviation and f2 at 6MHz, 2MHz p-p deviation, (PAL chroma and sound subcarriers). 2. Ratio of luminance bar amplitude (100% white), 13.5MHz p-p deviation, to output rms noise in 6MHz bandwidth with no input modulation. 3. The above characteristics were measured in the Application circuit shown in Fig.10, with an input power of -50dBm andƒ(RFIN) =480MHz, unless otherwise stated. Characteristic Min Max Units Conditions Supply voltage -0.3 7 V RF input voltage 2.5 Vp-p Storage temperature -55 125 °C Junction temperature 150 °C QP 28 package thermal 93 °C/W resistant, chip to ambient QP 28 package thermal 34 °C/W resistance, chip to case ESD protection 2 kV Mil std 883B method 30115 cat 1. ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V PIN DESCRIPTION PIN NO PIN NAME DESCRIPTION (Note units are MHz, Amps and Volts)

1 GND Chip ground

2 DIGFLO Flag = high when F (local oscillator) < F (IFIN) - F (WINDOW)/2

3 DIGFHI Flag = high when F (local oscillator) >F (IFIN) + F (WINDOW)/2

4 AFCSET Connected to V

5 AFCWINDOW Control input current sink sets width of AFCWINDOW

F =2250 Ko x I where I is the AFCWINDOW current F is the window width and Ko is the VCO gain

6 OSC V CC Oscillator VCC

7 OSC+ External tank

8 OSC- External tank

9 OSC GND Oscillator ground

10 VCO GAIN SET Control voltage input to set VCO GAIN. Connect to V CC 11 VIDEO DRIVE Video output (1K Ω , 1.8V p-p) 12 VIDEO POL SELECT Control voltage input to set Video polarity. 0 Volts = inverted,

5 Volt = normal

15 RF AGC CONTROL Control output current to tuner AGC control port. See Fig. 4. 16 NC

17 IF AGC SET Connect to V

18 AGC TIME CONSTANT Control input current source. Pulse at carrier frequency F(IFIN) with mark/space proportional to applied device AGC gain. Use external R-C to set time constant. 47K, 100nF

PIN NO PIN NAME DESCRIPTION (Note units are MHz, Amps and Volts) 19 RF AGC SET Connect to V CC via 1.8K resistor

20 IF GND IF stage ground

21 IF IP IF input (preferred input for single ended use)

22 IF IPB IF input

23 IF V

24 VIDEO FB- Loop amp negative input. Connected to VIDEO + via loop network

25 VIDEO- Loop amp negative output

26 VIDEO+ Loop amp positive output

27 VIDEO FB+ Loop amp positive input. Connected to VIDEO- via loop network 28 V CC Chip VCC FUNCTIONAL DESCRIPTION The SL1466 is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and requiring a minimal external component count. It contains all the elements required for the construction of a phase locked loop circuit, with the exception of tuning components for the local oscillator. Also included is an AFC detector circuit for generation of error signals to correct for any frequency drift in the outdoor unit local oscillator. A block diagram is shown in Fig. 2 and a typical application in Fig. 6. The internal pin connections are shown in Fig. 1. In normal applications the second satellite IF of typically 403.2 or 479.5 MHz is fed to the RF preamplifier, which contains a two stage level detect circuit. This generates two AGC signals, one of which controls the gain of the internal IF amplifier stage and one which can be used for controlling the gain of an external RF preamplifier so maintaining a fixed level to the input of the phase detector for optimum threshold, performance. The typical AGC curves are shown in Fig. 4. The output of the preamplifier is fed to the mixer section which is of a balanced design for low radiation. In this stage the IF signal is mixed with the local oscillator signal, which is generated by an on board oscillator. The oscillator is tuned internally, requiring only an external fixed LC tank and is optimised for high linearity over the normal deviation range. Typical frequency versus video drive voltage response for the oscillator is shown in Fig. 8. This response was measured with a modulated carrier. The compensated oscillator temperature stability is typically 0.05MHz/°C. The gain of the oscillator is nominally Ko = 54MHz/Volt. Note: Because there is a x3 amplifier in the video output section, the overall chip gain (MHz/V) is one third of the VCO gain or18MHz/Volt. The gain may be set accurately by means of potential divider connected to Pin 10. (+4.5V) The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop amplifier transfer characteristics. The output of the loop amplifier is referenced so as to eliminate V CC dependence of the VCO. The loop amplifier drives a buffer amplifier, which can be connected to a 75 Ohm load or a high impedance stage to give greater linearity and approximately 6dB higher demodulated signal. The video polarity can be inverted depending on the sense of the video polarity select input; open circuit or a resistor to V CC gives positive video whereas a resistor to V EE gives negative video. R2 C1 VIDEO DRIVERF INPUT VCO VCO GAIN = Ko RAD/SEC/VOL T VIDEO X 3 PHASE DETECT OR GAIN = Kd VOLT/RAD Fig. 3 Design of PLL loop parameters

The SL1466 is normally used as a type 2 second order loop and can be represented by the above diagram. for such a system the following loop parameters apply. T 1= C1 R1 T 2= C1 R2 and T 1= Ko KD /ω n T2=2 ξ/ω n where: KO is the VCO gain in radians seconds per volt KD is the phase detector gain in volts per radian ω n is the natural loop bandwidth ξ is the loop damping factor From these factors the loop 3dB bandwidth can be determined from the following expression; which approximates to ω 3dB = 2ξω n, when ξ >>1 N.B. VCO gain within the PLL is three times higher than at the video drive pin due to gain in the output stage. NOTE: R1 is the loop amplifier input resistor. R2 and C2 are the generic designators for the loop components R7-R9 and C9, C14 on the circuit diagram. AGC FACILITY A sophisticated two stage level detect circuit has been provided which will control both internal IF AGC and external tuner AGC amplifiers in order to maintain a fixed level to the input of the phase detector of around –20dBm for optimum threshold performance. The internal AGC amplifier provides 50dB of gain adjust and the external AGC control provides for 15dB of gain adjust, thus covering 65dB of dynamic range at the tuner input. The RF output current RF AGC CONTROL can be converted to a positive gradient control voltage by an external resistor. AFC FACILITY The SL1466 contains a digital frequency error detect circuit, which generates an output consisting of two logic flags, DIGFHI and DIGFLO, dependant on whether the LO frequency is above or below the input frequency. These flags have an overlap region where both are high; this is equivalent to the deadband window. The function of the AFC outputs is shown in Fig. 7 and the accompanying Table. 3dB n n Fig. 4 RF AGC control current and AGC time cinstant voltage vs Input power AGC TIME CONSTANT (V) -10 400 350 300 250 200 150 100 -90 -70 -50 -30 RFCONT TC Pin dBm RFC AGC CONTROL CURRENT ( µA)

Fig. 5a SL1466 I.O.ports internal circuitry Vcc VEE DIGFHI DIGFLO AFC DIGFLO, DIGFHI outputs (Pins 2, 3) 62 µA VREF 4.8k AFC KEY AFC KEY INPUT (Pin 4) VREF;Vcc –2.5V AFC WINDOW Vcc VEE VEE VEE 2.5mA 2.5mA 3mA OSC OSC OSC 50 50 AFC WINDOW (Pin 5) OSC (Pin 7, 8) 4.8k VEE VCCVCC 125 125 VCO GAIN ADJUST

125 VCC/2

VCO GAIN ADJUST (Pin 10) VIDEO DRIVE (Pin 11) VCC VEE

60 VIDEO

3.3mA Vcc VEE µA µA µA AFC SET AFC SET (Pin 4) VCO GAIN SET VCO GAIN SET (Pin 10)

Fig. 5b SL1466 I.O ports internal circuitry Vcc AGC TIMECONST ANT (Pin 18) VREF;Vcc –2.4V AGC TIME CONST ANT IF IP (Pins 21, 22) VEE IF IP 350 350 415 415 VCC IF IP RF AGC SET (Pin 19) REF;Vcc –2VV RF AGC SET Vcc VIDEO POLARITY (Pin 12) VIDEO 160k 2.5V VEEVEE POLARITY RF AGC control (Pin 15) VEE RF AGC CONTROL IF AGC SET (Pin 17) IF AGC SET VREF, Vcc –3.15V VEE RF AGC CONTROL (Pin 15) IF AGC SET (Pin 17) AGC TIME CONSTANT (Pin 18)

Fig. 5c SL1466 I.O ports internal circuitry Fig. 6 Typical application circuit. Note: Loop component values may need re-optimising on Application and VCO gain setting. VCC VIDEO+, VIDEO– (Pins 25, 26) EEV 500 A VIDEO+ VCC EEV 500 A VIDEO– µ µ IF IP (Pins 21, 22) VEE IF IP 350 350 415 415 VCC IF IP

28 VCC

100µF VCC 14 NC NC13

12 VIDEOPOL

11 VIDEODRIVE

10 VCOGAINSET

94.5T,3MM,0 56" L1 C1 NTC0.5p. 750PPM OSCGND C3a C3b 100nF 100pF VCCVCC 12 3 R1 100K Tayo Yudan UMK107 UK0R5CZ-B

8 OSC-

5 AFCWINDOW

4 AFCSET

3 DIGFLHI

IC1 SL1466_IEE

f(LO) Fig. 7 SL1466 digital AFC output FREQUENCY ERROR DIGFLO DIGFHI f(LO) Below window 1 0 f(LO) Within window 1 1 f(LO) Above window 0 1 Fig.8 VCO performance (S curve characteristics) 4.5 540 3.5 2.5 1.5 420 430 440 450 460 470 480 490 500 510 520 530 VIDEO DRIVE Volts Up Down RF IN MHz

Adjust the tank coil by squeezing it slightly until the signal on both Pins goes high (i.e. > Vcc –0.4 Volts). These Pins remain high provided the LO frequency is tuned to within the AFC WINDOW aperture,( ± 0.22MHz). Optimising the loop components The network connected from Pin 26 (VIDEO+) to Pin 24 (VIDEOFB–) and from Pin 25 (VIDEO–) to Pin 27 (VIDEO FB+) forms the loop filter. The components shown are based on a natural frequency ƒn of 2.46MHz (ω n =2x π x2.46 Mrads/s ) and damping factor ξ =2.6, and assuming Ko = 54MHz/V. The closed loop gain of the receiver (i.e. the ratio of the output amplitude to the input carrier frequency variation versus frequency) has a low pass filter characteristic. Its roll off is determined by the natural frequency whilst its in band flatness is determined by the damping factor. Both factors will affect the 3dB bandwidth as discussed earlier. A narrow bandwidth will cause loss of high frequency resolution whilst a large bandwidth will degrade the overall signal/noise in the output waveform. Thus a selection procedure might be as follows: n Calculate R7 (R9) and C9 (C14) based on ƒ n = 2.46MHz, ξ =2.6 and connect as in Fig. 5. n Set the video generator for 1Vp–p composite video and the test generator for a carrier frequency of 479.5MHz, frequency deviation of 13.5MHz and power level –30dBm. n Turn on the pre–emphasis filter. Use the 15kHz test pattern to give black/white screen. n Monitor the video analyser or TV set. n Adjust the de–emphasis filter until the bar amplitude is 1Vp–p or 0% error. Reduce transmitter power level until sparklies or streaking appear. n Adjust component values for minimum power level when streaking and sparklies occur together. AGC settings The signal level at the input to the limiter preceding the phase detector is maintained at an level of around –20dBm or more by an internal (device) AGC and an external (tuner) AGC circuit. Current pulses at the carrier frequency with mark/space proportional to this input power are sourced out of pin 18 (AGC TIME CONSTANT). These are smoothed and turned into a voltage by the external components R4, C4. The time constant R4 C4 should be adjusted so that the expected signal fading rate can be tracked but its value is not critical, 5mSec typically. Fig. 4 shows a typical external AGC control curve. Also shown is the AGCTIMECONST voltage which is an indication of the level of internal AGC gain being applied, (the control range is the flat part of the curve). APPLICATION NOTES Tuning procedure The component values shown in the applications circuit Fig. 6 are optimised for operation at an IF of 479.5MHz. The AFC circuit can be used to fine tune the external tank as follows: With the SL1466 connected as in the test set up Fig. 11 or its equivalent using 75Ω cables. Set the video generator for 1V p-p output. Set the satellite test transmitter for a carrier frequency of 479.5MHz, frequency deviation 13.5MHz, power level -30dBm. Turn on the pre-emphasis filter. Monitor the voltage levels on Pin 2 (DIGFLO) and Pin 3 (DIGFHI).

Fig. 9 Test demo PCB

Fig. 10 Test/Demo circuit diagram R&S SPGF Waveform Generator Pre-Emphasis Modulator/ Upconverter SL1466 De-Emphasis R&S UAF Video Analyser Video Monitor R&S SFZ Satellite Test Transmitter 479.5MHz f = 13.5MHz Fig. 11 Test set up H219 100µF VCC 14 NC NC13 94.5T,3MM,0 56" L1 C1 NTC0.5p. 750PPM OSCGND C3a C3b 100nF 100pF VCCVCC 12 3 R1 100K Tayo Yudan UMK107 UK0R5CZ-B IC1 SL1466_IEE

Dimensions are shown thus: mm (in). For further package information, please contact your local Customer Service Centre. Internet: http://www.gpsemi.com CUSTOMER SERVICE CENTRES l FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07 l GERMANY Munich Tel: (089) 419508-20 Fax : (089) 419508-55 l ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 l JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 l KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 l NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 l SOUTH EAST ASIA Singapore Tel:(65) 3827708 Fax: (65) 3828872 l SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 l TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 l UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © Mitel Corporation 1998 Publication No. DS3979 Issue No. 2.2 August 1997 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM HEADQUARTERS OPERATIONS MITEL SEMICONDUCTOR Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 MITEL SEMICONDUCTOR

1500 Green Hills Road,

Scotts Valley, California 95066-4922 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576/6231 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.

28 LEADS AT

0·63 (0·025) NOM. SPACING 0·127/0·25 (0·004/0·010) PIN 1 REF. SPOT 28-LEAD SUBMINIATURE PLASTIC DIL - QP28 NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your Mitel Semiconductor Customer Service Centre for further information. 0·64/0·76 (0·025/0·030) 1·55/1·73 (0·061/0·068) 0·17/0·30 (0·007/0·012) 1·40/1·55 (0·055/0·061) PIN 1 9·80/9·98 × 45° REF. 5·80/6·20 (0·230/0·244) 0·17/0·25 (0·007/0·010) 0·41/0·89 (0·016/0·035) 0-8° 3·81/3·99 (0·150/0·157)