SL1461MPAS

SL1461SA ZARLINK | Alldatasheet

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Technical content

Wideband PLL FM Demodulator Advance Information DS4358 ISSUE 1.3 September 1999

Ordering Information

The SL1461SA is a wideband PLL FM demodulator, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of external oscillator sustaining network and loop feedback components, to form a complete PLL system operating at frequencies up to 800MHz. An AFC with window adjust is provided, whose output signal can be used to correct for any frequency drift at the head end local oscillator.

FEATURES

I Single chip PLL system for wideband FM demodulation I Simple low component count application I Allows for application of threshold extension I Fully balanced low radiation design I High operating input sensivity I Improved VCO stability with variations in supply or temperature I AGC detect and bias adjust I 75Ω video output drive with low distortion levels I Dynamic self biasing analog AFC I Full ESD Protection* * Normal ESD handling procedures should be observed

APPLICATIONS

I Satellite receiver systems I Data communications Systems MP16 Fig.1 Pin connections - top view 1611 6 7 10 AFC PUMP AFC WINDOW ADJUST V EE OSCILLATOR + OSCILLATOR – AGC BIAS AGC OUTPUT RF INPUT AFC OUTPUT VCC VIDEO FEEDBACK + VIDEO – VIDEO + VIDEO FEEDBACK – VIDEO OUTPUT RF INPUT SL1461SA Fig.2 SL1461SA block diagram AGC BIAS RF INPUTS AGC OUTPUT LOCAL OSCILLATOR AFC WINDOW ADJUST VIDEO FEEDBACK + VIDEO + VIDEO – FEEDBACK – VIDEO OUTPUT AFC PUMP AFC OUTPUT VIDEO

SP1461SA Advance Information -40 2.0 0.5 0.25 570 240 1.9 0.5 1.0 0.3 0.4 mA MHz dBm dBm MHz/V MHz/V KHz/°C V/rad V/rad Ω Ω dB MHz Vp-p Ω Degree dB dB µA µA µA µA µA V 800 700 1.2 2.5 -40 400 250 400 0.4

ELECTRICAL CHARACTERISTICS

Tamb = -20°C to +80°C, VCC = +4.5V to +5.5V. The electrical characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Min. Typ. Max. Supply current Operating frequency Input sensitivity Input overload VCO sensitivity (dF/dV) VCO linearity VCO supply stability VCO temperature stability Phase detector gain Loop amplifier input impedance Loop amplifier output impedance Loop amplifier open loop gain Loop amplifier gain bandwidth product Loop amplifier output swing Video drive output impedance Video drive: Luminance nonlinearity - differential gain - differential phase - intermodulation - signal/noise - Tilt - baseline distortion AGC output current AGC bias current AFC window current AFC charge pump current AFC leakage current AFC output saturation voltage Preamp limiting Refer to application in Fig. 3 Refer to application in Fig. 3; with 13.5MHz p-p deviation See note 5 See note 5 Differential loop filter Single ended loop filter Single ended Single ended Single ended Single ended Single ended 1KΩ load, See note 3 and 4 75KΩ load, See note 3 and 4 75KΩ load, See note 3 and 4 See notes 1, 3 and 4 1KΩ load, See note 2 and 4 1KΩ load, See note 3 and 4 1KΩ load, See note 3 and 4 Maximum load voltage drop 2V 400µA gives 1.5V deadband window With charge pump disabled AFC output enabled UnitsValue ConditionsCharacteristics 300 450 Note 1. Product of input modulation f 1 at 4.43MHz, 13.5MHz p–p deviation and f 2 at 6MHz p–p deviation, (PAL chroma and sound subcarriers). Note 2. Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz bandwidth with no input modulation. Note 3. Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk. Note 4. See page 3 Note 5. Assuming operating frequency of 479.5MHz set with V CC @ 5.0V and ambient temperature of +20°C. Only applies to Application shown in Fig. 3. also refer to Fig. 8.

SL1461SAAdvance Information Fig.2 SL1461SA block diagram TEST CONFIGURATION BASE BAND VIDEO 1V p–p VIDEO GENERATOR ROHDE & SCHWARZ SGPF TV SAT TEST TX ROHDE & SCHWARZ SFZ RF CARRIER FREQ 479.5MHz FM MODULATION 13.5MHz P–P PRE–EMPHASISED VIDEO MONTFORD TEST OVEN SL1461 TEST APPLICATION BOARD See Fig. 3 for details PRE EMPHASISED BASE BAND VIDEO VIDEO AMPLIFIER/ DE EMPHASISED NETWORK DE EMPHASISED BASE BAND VIDEO 1V p–p VIDEO ANALYSER ROHDE & SCHWARZ UAF The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in the Electrical Characteristics Table coincide with high temperatures and extremes of supply voltage. No adjustment to the recorded figures has been made to compensate for the effects of temperature on the external components of the application test board, in particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature compensation of the external circuitry will result in performance figures closer to the stated typical figures. 2.5 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 125 150 111 V Vp-p V V V V V V V V V V °C/W ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Min. Typ. Max. Supply voltage RF input voltage RF input DC offset Oscillator ± DC offset Video ± DC offset Video feedback ± DC offset Video output DC offset AFC pump DC offset AFC disable DC offset AFC deadband DC offset AGC bias DC offset AGC output DC offset Storage temperature Junction temperature MP16 package thermal resistance, chip to ambient ConditionsCharacteristics -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55

SP1461SA Advance Information 250 °C/W mW kV kV ABSOLUTE MAXIMUM RATINGS cont. All voltages are referred to VEE at 0V Min. Typ. Max. MP16 package thermal resistance, chip to case Power consumption at 5.5V ESD protection - pins 1 to 15 ESD protection - Pin 16 ConditionsCharacteristics 1.7 Mil-std-883 method 3015 class 1 Mil-std-883 method 3015 class 1 Fig.3 Standard application circuit 1611 6 7 10 SL1461SA AGC BIAS AFC WINDOW ADJUST 50K 27K 100nF 47 F +5V 47nF 100nF 5K1 4n7 4K7 1nF RF INPUT 1nF 47 F 1K2 1K2 4K7 VIDEO OUTPUT 470nF BB515 BB515 100pF 100pF RV1 RV2 R6 C3 C4 1nF C12 C2C1 C11 TP1 TP2C10 C8C7 TP3 TP4 FUNCTIONAL DESCRIPTION The SL1461SA is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and requiring a minimum external component count. It contains all the elements required for construction of a phase locked loop circuit, with the exception of tuning components for the local oscillator, and an AFC detector circuit for generation of error signal to correct for any frequency drift in the outdoor unit local oscillator. A block diagram is contained in Fig. 2 and the typical application in Fig. 3. The internal pin connections are contained in Fig.6/6a In normal applications the second satellite IF frequency of typically 402 or 479.5MHz is fed to the RF preamplifier, which has a working sensitivity of typically -40 dBm, depending on application and layout. The preamplifier contains an RF level detect circuit, which generates an AGC signal that can be used for controlling the gain of the IF amplifier stages, so maintaining a fixed level to the RF input of the SL1461SA, for optimum threshold performance. The bias point of the AGC circuit can be adjusted to cater for variation in AGC line voltage requirement and device input power. The typical AGC curves are shown in Fig. 9. It is recommended that the device is operated with an input signal between -30 and -35dBm. This ensures optimum linearity and threshold performance, and gives a good safety margin over the typical sensitivity of -40dBm. The output of the preamplifier is fed to the mixer section which is of balanced design for low radiation. In this stage the RF signal is mixed with the local oscillator frequency, which is generatedby an on–board oscillator. The oscillator block uses an external varactor tuned sustaining network and is optimised for high linearity over the normal deviation range. A typical frequency versus voltage characteristic for the oscillator is contained in Fig. 7. The loop output is designed to compensate for first order temperature variation effects; the typical stability is shown in Fig. 8 The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop transfer characteristic . Feedback can be applied either in differential or single ended mode; if the appropriate phase detector gains are assumed in calculating loop filters, both modes should give the same loop response. The loop amplifier drives a 75Ω output impedance buffer amplifier, which can either be connected to a 75Ω load or used to drive a high input impedance stage giving greater linearity and approximately 6dB higher demodulated signal output level.

SL1461SAAdvance Information DESIGN OF PLL LOOP PARAMETERS Fig.4 VCO R2 C1 BASEBAND OUTPUTR1RF INPUT GAIN = K0 RAD SEC/VOLT GAIN = KD VOLT/RAD The SL1461SA is normally used as a type 1 second order loop and can be represented by the above diagram. For such a system the following parameters apply; K0KD n n and where: K0 is the VCO gain in radian seconds per volt KD is the phase detector gain in volts per radian n is the natural loop bandwidth is the loop damping factor R1 is loop amplifier input impedance Note: K0 is dependant on sensitivity of VCO used. KD = 0.25V/rad single ended, 0.5V/rad differential From these factors the loop 3dB bandwidth can be determined from the following expression; AFC FACILITY The SL1461SA contains an analog frequency error detect circuit, which generates DC voltage proportional to the integral of frequency error. If the incident RF is high then the AFC voltage increases, if low then the voltage decreases. The AFC voltage can then be converted by an ADC to be read by the micro controller for frequency fine tuning; if used in an I system it is recommended the device is used with either the SP5055 or SP5056 frequency synthesiser which contains an internal ADC readable via the I2C bus. The voltage corresponding to frequency alignment is arbitrary and user defined; if used with the SP5055 it is suggested the aligned voltage is 0.375 VCC , corresponding to the centre code of the ADC on port 6. The AFC detect circuit contains a deadband centre around the aligned frequency. The deadband can be adjusted from zero window to approximately 25MHz width assuming an oscillator dF/dV of 15MHz/V. If the incident RF is within this window the AFC voltage does not integrate, except by component leakage. With reference to Fig.5; in normal operation the demodulated video is fed to a dual comparator where it is compared with two reference voltages, corresponding to the extremes of the deadband, or window. These voltages are variable and set by the window adjust input. The comparators produce two digital outputs corresponding to voltages above or below the voltage window, or frequency above or below deadband. These digital control signals are used to control a complimentary current source pump. The current signals are then fed to the input of an amplifier which is arranged as an integrator, so integrating the pulses into a DC voltage. If the frequency is correctly aligned both the current source and sink are disabled, therefore the DC output voltage remains constant. There will be a small drift due to component leakage; the maximum drift can be calculated from;

SP1461SA Advance Information Fig.5 AFC system block diagram WINDOW ADJUST HIV LOV VALIGN FREQ BASEBAND VIDEO VCC VCC VEE CEXT EXTR VAFC

SL1461SAAdvance Information Fig.6 SL1461SA I/O port internal circuitry AGC OUTPUT VCC VREF; 2.7V AGC output VREF; 2V AGC BIAS AGC bias adjust AFC window adjustRF inputs VREF; 3V 2x1500 RF INPUTS VREF; 1.6V AFC WINDOW AFC output stage VCC AFC PUMP AFC OUTPUT Video amp outputs VIDEO + VIDEO –330 330 2mA 2mA 10K

SP1461SA Advance Information Fig.6a SL1461SA I/O port internal circuitry Local oscillator Video amp feedback inputs 2x570 VIDEO FEEDBACK + VIDEO FEEDBACK – 2 x 5k VREF; 1.2V OSCILLATOR + OSCILLATOR – Video output drive VCC OUTPUT 105 4mA VIDEO FROM PHASE DETECTOR Fig.7 Typical VCO frequency vs DC control voltage 520 500 480 460 440 420 400 360 1 1.5 2 2.5 3 3.5 4 4.5 5 FREQ MHz DC VOLTAGE

SL1461SAAdvance Information Fig.8 SL1461SA VCO centre frequency uncompensated temperature stability 479.5 478.5 477.5 476.5 475.5 –20 30 80 VCO STABILITY vs TEMP and SUPPLY TEMP/°C 480 479 478 477 476 55 5 FREQUENCY (MHz) 4.5 4.75 5.25 5.5 SUPPLY (V) Fig.9 SL1461SA AGC output voltage for differing values of AGC bias resistor AGC 2.0 1.5 1.0 0.5 V CC VOLTAGE RF INPUT LEVEL (dBm) UNMODULATED OUTPUT AGC BIAS RESISTOR 5.1K AGC BIAS CURRENT 297 A AGC LOAD RESISTOR 3.9K AGC BIAS RESISTOR 10.5K AGC BIAS CURRENT 150 A AGC LOAD RESISTOR 4.7K AGC BIAS RESISTOR 32K AGC BIAS CURRENT 52 A AGC LOAD RESISTOR 10K = 5.0 VOLTS APPLICATION NOTES Capture range Under conditions when there is no RF input signal present, the SL1461SA may react to spurious radiation from the free running oscillator coupling into the RF inputs. Because of the constant phase error between the VCO input to the phase detector and the spuriously coupled signal via the RF input, the phase comparator will drive the control voltage to either the bottom or the top of the range. In such a case, the capture range will be asymmetrical about the VCO free running frequency, since any control voltage will only be able to tune the VCO in one direction if the tuning voltage is already at the max or min. This effect can be avoided by driving the RF input differentially or achieving good common mode rejection to the VCO signal. The lock range is independant of the above effects and will be symmetric about the centre of the phase detector S- curve provided the VCO is correctly aligned. EXAMPLE Loop out of lock Tuning voltage =4.3V (maximum) frequency =520MHz (maximum It is only possible to capture signals below this frequency since the VCO is already at its maximum frequency. Testing of capture range should be done with the device operating under normal conditions. An input signal of between -35dBm to -10dBm is suitable for such a measurement.

SP1461SA Advance Information Lock range Lock range should be symmetric about the centre of the S-curve. When the oscillator is sitting in the centre of the S-curve, the two video outputs will be at the same DC voltage. RF oscillator design The standard application circuit for the SL1461SA is shown in Fig.3 The layout of the VCO tank should follow normal good RF techniques - ie as compact as possible. This will minimise parasitics, thus giving improved VCO linearity and stability. The PCB layout used for testing purpose is shown in Fig. 10. Setting up of oscillator The VCO should be set up so that the desired input RF frequency is at the centre of the lock range. This will coincide with the centre of the S-curve and the point at which the AFC toggles when set to zero deadband. The easiest way to centralise the VCO is to input an RF carrier which is being modulated by a low frequency squarewave. The tuning coil(s) should be adjusted until the AFC voltage toggles between 0.2V and V CC-0.7V. The smaller the FM deviation of the squarewave used, the more accurate the setting will be. A pre-emphasised video input containing black to white transitions can also be used for this setting, since the DC content in a pre-emphased video is much less than that in non pre–emphasised video. This is important as any dc content in the input waveform will introduce an offset in the AFC transi- tion point. The setting can be confirmed by measuring the DC voltage on the two video outputs, the voltages should be the same when the oscillator is centred around the incoming frequency. This DC measurement must be carried out with an unmodulated carrier of the required frequency. Modulation must not be present, since by definition, the dc voltages would be changing, thus making accurate measurement difficult.

SL1461SAAdvance Information Fig.10 Layout of demo board with component locations

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