SKY72310-11

SKY72310-11 SKYWORKS | Alldatasheet

Document overview

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Technical content

Features

• Spur-free, fractional-N operation
• Operating frequency: 50 MHz to 2.1 GHz
• Normalized phase noise: -218 dBc/Hz
• Low power consumption:11 to 14 mW typical @ 3 V
• Ultra-fine step size, 100 Hz or less
• Software programmable power-down modes
• High-speed serial interface up to 100 Mbps
• Programmable division ratios on reference frequency
• Phase detector with programmable gain to provide a programmable loop bandwidth
• On-chip crystal oscillator
• Supply range: 2.7 to 3.3 V operation
• High ESD: 1 kV HBM
• MCM (24-pin, 4 x 4 mm) (MSL3, 260 °C per JEDEC J-STD-020) package
• Pin-compatible replacement to the SKY72310-362LF

Description

Skyworks SKY72310-11 fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 100 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer’s fine step size can compensate for crystal oscillator or intermediate frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The device’s fine step size can also be used for Doppler shift corrections. Reference crystals or oscillators up to 50 MHz can be used with the SKY72310-11. The crystal frequency is divided down by independent programmable dividers (1 to 32) for the synthesizer. The phase detector can operate at a maximum speed of 50 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 μs can be achieved. The lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications.

Figure 2. SKY72310-11 Pinout Table 1. SKY72310-11 Signal Descriptions 1 VCCecl/cml Power and ground ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump. 2 Fvco_main Input Main VCO single-ended input. 4 LD Digital output Lock detect output pin. Indicates phase detector out-of-lock as an active low.

7 N/C - No connection

8 Xtalacgnd/OSC Ground/input Reference crystal AC ground or external oscillator differential input. 9 Xtalin/OSC Input Reference crystal input or external oscillator differential input. 10 Xtalout/NC Input Reference crystal output or no connect. 11 VCCxtal Power and ground Crystal oscillator ECL/CML, 3 V. 12 GNDxtal Power and ground Crystal oscillator ground. 19 VCCdigital1 Power and ground Digital supply, 3 V. 20 Data Digital input Serial address and data input pin. Address bits are followed by data bits. CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. on the rising edge of Clock. 23 Mod_in Digital input Alternate serial modulation data input pin. Address bits are followed by data bits. serial data out, or testability signals. This pin can be tri-stated from the synthesizer registers. 1 Associated pairs of power and ground pins must be decoupled using 0.1 µF capacitors.

DATA SHEET • SKY72310-11: SPUR-FREE, 50 MHz TO 2.1 GHz SINGLE FRACTIONAL-N FREQUENCY SYNTHESIZER Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 203639K • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2022 4 Technical Description The SKY72310-11 is a fractional-N frequency synthesizer using a ∆Σ modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the SKY72310-11 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. Serial Interface The serial interface is a versatile three-wire interface consisting of three pin signals: Clock (serial clock), Data (serial input), and CS (chip select). It enables the SKY72310-11 to operate in a system where one or multiple masters and slaves are present. To perform a loopback test at startup and to check the integrity of the board and processor, the serial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. ∆Σ Modulator The SKY72310-11 provides fractionality through the use of a proprietary, configurable 10-bit or 18-bit ∆Σ modulator. The output from the modulator is combined with the divider ratio through its fractional units. VCO Prescaler The VCO prescaler provides low-noise signal conditioning of the VCO signal. It translates an off-chip, single-ended signal to an on-chip differential Current Mode Logic (CML) signal. VCO Divider The SKY72310-11 provides a programmable divider that controls the CML prescaler and supplies the required signal to the charge pump phase detector. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode and from 32 to 543 in integer-N mode. Reference Frequency Oscillator The SKY72310-11 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency divider. Reference Frequency Divider The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequency for the phase detector. The divide ratio is programmed using the Reference Frequency Dividers Register. NOTE: The divided crystal oscillator frequency (the internal reference frequency), f ref_main, is referred to as “reference frequency” throughout this document. Phase Detector and Charge Pump The SKY72310-11 uses a charge pump phase detector that provides a programmable gain from 0.125 to 1 mA/radian. The phase detector is programmed using the Phase Detector/Charge Pump Control Register (Register 6). Lock Detection The SKY72310-11 provides an active low LD signal at Pin 4 to indicate an out-of-lock condition. When the phase detector is locked, the LD signal is logic high. Power Down The SKY72310-11 supports a number of power-down modes through the serial interface. For more information, see the Register Descriptions section of this document. Serial Interface Operation The serial interface consists of three pins: Clock (pin 22), Data (Pin 20), and CS (pin 21). The Clock signal controls data on the two serial data lines (Data and CS). The Data pin shifts bits into a temporary register on the rising edge of Clock. The CS signal allows individual selection transfers that synchronize and sample the information of slave devices on the same bus. Figure 3 functionally depicts how a serial transfer takes place. A serial transfer is initiated when a microcontroller or microprocessor forces the CS signal to a low state. This is followed immediately by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented at the Clock pin. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the registers, 16 bits of address or data must be presented to the Data line with the LSB last while the CS signal is low. If the CS signal is low for more than 16 clock cycles, only the last address or data bits are used to load the registers.

Nfractional Desired VCO division ratio in fractional-N applications. integer Desired VCO division ratio in integer-N applications. step equal to fdiv_ref/210 Hz. where Nfractional must be between 37.5 and 537.5. Figure 3. Serial Transfer Timing Diagram

Where 00 0111 1101 is loaded in the Divdend MSB Register and 1001 1000 is loaded in the Dividend LSB Register. Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz. Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)

Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)

DATA SHEET • SKY72310-11: SPUR-FREE, 50 MHz TO 2.1 GHz SINGLE FRACTIONAL-N FREQUENCY SYNTHESIZER Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 203639K • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2022 8 Integer-N Applications. The desired division ratio for the synthesizer is given by: ref_div main_vco egerint f fN = where Ninteger is an integer number from 32 to 543. The value to be programmed in the Divider Register is given by: 32− =egerintreg N N When in integer mode, allowed values for Nreg are from 0 to 511. NOTE: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. Register Loading Order. In applications where the synthesizer is in 18-bit mode, the Dividend MSB Register holds the 10 MSBs of the dividend and the Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the synthesizer’s divide ratio are to be loaded in the following order:

• Divider Register
• Dividend LSB Register
• Dividend MSB Register (at which point the new divide ratio takes effect) In applications where the synthesizer is in 10-bit mode, the Dividend MSB Register holds the 10 bits of the dividend. The registers that control the synthesizer’s divide ratio are to be loaded in the following order:
• Divider Register
• Dividend MSB Register (at which point the new divide ratio takes effect) NOTE: When in integer mode, the new divide ratios take effect as soon as the Divider Register is loaded. Direct Digital Modulation The high fractionality and small step size of the SKY72310-11 allow the user to tune to practically any frequency in the VCO’s operating range. This allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is programmed by the Main Divider and MSB/LSB Dividend Registers, and the instantaneous frequency offset from the carrier is programmed by the Modulation Data Register. Direct Digital Modulation is only supported in unsigned mode. The Modulation Data Register can be accessed in three ways as defined in the following subsections. Normal Register Write. A normal 16-bit serial interface write occurs when the CS signal is 16 clock cycles wide. The corresponding 16-bit modulation data is simultaneously presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (f pd_main). Short CS Through Data Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly in the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are re- synchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (f pd_main). Short CS Through Mod_in Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented on the Mod_in pin, an alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This mode is selected through the Modulation Control Register. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are internally re-synchronized at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (f pd_main). Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2 m multiplication of frequency deviation. NOTE: The programmable range from 0 to less than 1 of the main ∆Σ modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to: 0625 . 1 ) dividendN ( 0625 . 0mod + ≤+ ≤ − When the sum of the dividend and modulation data lie outside this range, the value of N integer must be changed.

address 0x0, which is set to 0x006.

• Synthesizer Divider Index = 9-bit value for the integer portion of the synthesizer divider. Valid values for this register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N). The Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset from 0 to less than 1 to the main integer selected through the Divider Register. As shown in Figures 6 and 7, values to be loaded are:
• Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the synthesizer.
• Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the synthesizer. The Dividend Register MSB and LSB values are unsigned format. NOTE: When in 10-bit mode, the Dividend LSB Register is not required. The reference frequency divider provides the reference frequency to the phase detector by dividing the crystal oscillator frequency. Divide ratios from 1 to 32 are possible for the reference frequency divider (see Table 3). The Reference Frequency Dividers Register configures the reference frequency divider for the synthesizer. As shown in Figure 8, the values to be loaded are:
• Reference Frequency Divider Index = Desired oscillator frequency division ratio -1. Default value on power up is 0, signifying that the reference frequency is not divided for the phase detector.

Table 2. SKY72310-11 Register Map

0 Divider Register 12 4

1 Dividend MSB Register 12 4

2 Dividend LSB Register 12 4

3 Unused

4 Unused

5 Reference Frequency Dividers Register 12 4

6 Phase Detector/Charge Pump Control Register 12 4

7 Power Down/Multiplexer Output Select Control Register 12 4

8 Modulation Control Register 12 4

14 Delta Sigma 12 4

1 All registers are write only. 2 No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.

Table 4. Multiplexer Output Figure 11. Modulation Control Register (Write Only)

• Synthesizer Mode = One-bit flag to power down the ∆Σ modulator and fractional unit. When this bit is cleared, the synthesizer is in fractional-N mode. When this bit is set, the synthesizer is in integer-N mode.
• Synthesizer ∆Σ Fractionality = One-bit flag to configure the size of the ∆Σ modulator. This has a direct effect on power consumption, and on the level of fractionality and step size. When this bit is cleared, the ∆Σ modulator is 18-bit with a fractionality of 218 and a step size of fref_main/262144. When this bit is set, the ∆Σ modulator is 10-bit with a fractionality of 210 and a step size of fref_main/1024. NOTE: There are no special power-up sequences required for the SKY72310-11.
• Multiplexer Output Selection = Three-bit value that selects which internal signal is output to the Mux_out pin. The following internal signals are available on this pin: − Reference oscillator: f ref − Divided reference (post-reference frequency divider): fref_main − Phase detector frequency (post-frequency divider): fpd_main − Serial data out for loop-back and test purposes Refer to Table 4 for more information.
• Mux_out Pin Tri-State Enable = One-bit flag to tri-state the Mux_out pin. When this bit is cleared, the Mux_out pin is enabled. When this bit is set, the Mux_out pin is tri-stated. The Modulation Control Register is used to configure the modulation unit of the main synthesizer. The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS signal, can be from 2 to 12 bits wide to provide from 4 to 4096 selectable frequency offset steps. The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. As shown in Figure 11, the values to be loaded are:
• Modulation Data Magnitude Offset = Four-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a m multiplication of the modulation data sample.
• Modulation Data Input Select = One-bit flag to indicate the pin on which modulation data samples are serially input when the CS signal is between 2 and 12 bits long. When this bit is cleared, modulation data samples are to be presented on the Data pin. When this bit is set, modulation data samples are to be presented on the Mod_in pin.
• Modulation Address Disable = One-bit flag to indicate the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is cleared, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is set,

and electrical specifications are provided in Table 7. Table 5. SKY72310-11 Absolute Maximum Ratings1 at or below their nominal values. ESD HANDLING: Although this device is designed to be as robust as possible, electrostatic discharge (ESD) can damage this device. potentials of several kilovolts on the human body or equipment, which can discharge without detection. Industry-standard ESD handling precautions should be used at all times. Table 6. Recommended Operating Conditions

Table 7. SKY72310-11 Electrical Characteristics 1 A 5 V charge pump power supply on pin 5 results in higher power-down leakage current. 2 The minimum synthesizer frequency is 12 x fOSC, where FOSC is the frequency at the Xtalin/OSC pin.

performance of the SKY72310-11 Frequency Synthesizer. (BOM) for the Evaluation Board is listed in Table 8. Figure 14. SKY72310-11 Evaluation Board Schematic

DATA SHEET • SKY72310-11: SPUR-FREE, 50 MHz TO 2.1 GHz SINGLE FRACTIONAL-N FREQUENCY SYNTHESIZER Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 203639K • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2022 17 SKY72310-11 Evaluation Board Bill of Materials (BoM) Quantity Reference Designator Value Size

9 C9,C15,C25,C36,C64,C84,C90,C91,C92 1 uF 603

5 C10,C16,C26,C78,C95 100 pF 402

1 C18 50 Ω 402

1 C37 1 nF 402

2 C41,C42 4.7 pF 402

1 C46 1000 pF 402

1 C47 330 pF 402

1 C53 .022 uF 402 1 C74 .1 uF 402

5 C80,C81,C82,C83,C87 10 pF 402

1 C88 68 pF 402

1 JP22 HEADER5_1

2 JP23,JP24 HEADER1_1

2 J6,J11 J_SMA_EDGE_2_4GHz

1 J7 SKY72310

1 J8 8 HEADER

3 J9,J12,J13 3 HEADER

3 L3,L6,L10 BLM21A601S,Murata

1 OSC1 V614ME01-LF (1800 MHz) or

V580ME02-LF (900 MHz) 5 R1,R6,R9,R85,R90 4.7 kΩ 402

4 R16,R30,R40,R44 10 Ω 402

3 R47,R84,R94 0 Ω 402

1 R48 3.9 kΩ 402

1 R51 750 Ω 402

4 R95,R96,R99,R98 DNI 402

1 R97 1 kΩ 402

1 R100 47 kΩ 402

1 Y1 24 MHz - XTAL_CSM_7X

Figure 16. SKY72310-11 PCB Layout Footprint

Figure 17. SKY72310-11 Package Dimensions

Figure 18. SKY72310-11 Tape and Reel Dimensions

DATA SHEET • SKY72310-11: SPUR-FREE, 50 MHz TO 2.1 GHz SINGLE FRACTIONAL-N FREQUENCY SYNTHESIZER Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 203639K • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2022 22

Ordering Information

Part Number Product Description Evaluation Kit Part Number SKY72310-11 Spur-Free, 50 MHz to 2.1 GHz Single Fractional-N Frequency Synthesizer SKY72310-11EK1 (1800 MHz) SKY72310-11EK2 (900 MHz) Copyright © 2007-2008, 2015-2016, 2019-2022 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes. No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale. THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters. Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference.