SKT672-040-E

SKT672-040-E ONSEMI | Alldatasheet

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61108HKIM/52004TN(OT)/60200RM (OT) No. 5227-1/19 http://onsemi.com Semiconductor Components Industries, LLC, 2013 June, 2013 STK672-040-E Overview The STK672-040-E is a stepping motor driver hybrid IC that uses power MOSFETs in the output stage. It includes a built-in microstepping controller and is based on a unipolar constant-current PWM system. The STK672-040-E supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. It supports five excitation methods: 2 phase, 1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. It also allows the motor speed to be controlled with only a clock signal. The use of this hybrid IC allows designers to implement systems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive.

Applications

• Facsimile stepping motor drive (send and receive)
• Paper feed and optical system stepping motor drive in copiers
• Laser printer drum drive
• Printer carriage stepping motor drive
• X-Y plotter pen drive
• Other stepping motor applications Note*: Conditions: VCC1 = 24V, IOH = 1.5A, 2W1-2 excitation mode. Thick-Film Hybrid IC Unipolar Constant-current Chopper (external excitation PWM) Circuit with Built-in Microstepping Controller Stepping Motor Driver (sine wave drive) Output Current 1.5A (no heat sink*)

No. 5227-2/19

Features

• Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator. <Control Block Features>
• One of five drive types can be selected with the drive mode settings (M1, M2, and M3) 1) 2 phase excitation drive 2) 1-2 phase excitation drive 3) W1-2 phase excitation drive 4) 2W1-2 phase excitation drive 5) 4W1-2 phase excitation drive
• Provides four freely selectable modes for the vector locus during microstepping drive: circular mode, one inside mode, and two outside modes.
• Phase retention even if excitation is switched.
• The excitation phase state can be verified in real time using the MO1, MO2, and MOI signal output pins.
• The CLK input counter block can be selected to be one of the following by the high/low setting of the M3 input pin. 1) Rising edge only 2) Both rising and falling edges
• The CLK and RETURN input pins include built-in malfunction prevention circuits for external pulse noise.
• ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20kΩ (typical) pull-up resistors.
• No noise generation due to the difference between the A and B phase time constants during motor hold since external excitation is used.
• Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any value between 0V and 1/2VCC2. <Driver Block>
• External excitation PWM drive allows a wide operating supply voltage range (VCC1 = 10 to 45V) to be used.
• Current detection resistor (0.33Ω) built-in the hybrid IC itself.
• Power MOSFETs adopted for low drive loss.
• Provides a motor output drive current of IOH = 1.5A. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 V CC1 max No signal 52 V Maximum supply voltage 2 V CC2 max No signal -0.3 to +7.0 V Input voltage V IN max Logic input pins -0.3 to +7.0 V Output current I OH max 0.5s, 1 pulse, when VCC1 applied. Load: R = 5Ω, L = 10mH for each phase. 2.2 A Repeated avalanche capacity Ear max 38 mJ Allowable power dissipation Pd max θc-a = 0 12 W Operating substrate temperature Tc max 105 °C Junction temperature Tj max 150 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage 1 V CC1 With signals applied 10 to 45 V Supply voltage 2 V CC2 With signals applied 5 ± 5% V Input voltage V IH 0 to VCC2V Phase driver withstand voltage V DSS Tr1, 2, 3, and 4 (the A, A, B, and B outputs) 100 (min) V Output current I OH Duty 50% 1.5 A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No. 5227-3/19 Rating Parameters Symbols Conditions min typ max unit Control supply current I CC Pin 7, with ENABLE pin held low. 4.5 15 mA Output saturation voltage Vsat R L = 15Ω (I ≈ 1.5 A) 1.4 1.9 V Average output current Ioave Load: R = 3.5Ω / L = 3.8mH For each phase, Vref ≈ 1V 0.465 0.517 0.569 A FET diode forward voltage Vdf If = 1A 1.2 1.8 V [Control Inputs] VIH Except for the Vref pin 4 V Input voltage VIL Except for the Vref pin 1 V IIH Except for the Vref pin 0 1 10 μA Input current IIL Except for the Vref pin 125 250 510 μA [Vref Input Pin] Input voltage V I Pin 8 0 2.5 V Input current I I Pin 8 1 μA [Control Outputs] VOH I = –3mA, pins MOI, MO1, MO2 2.4 V Output voltage VOL I = +3mA, pins MOI, MO1, MO2 0.4 V [Current Distribution Ratio (A·B)] 2W1-2, W1-2, 1-2 Vref θ = 1/8 100 % 2W1-2, W1-2 Vref θ = 2/8 92 % 2W1-2 Vref θ = 3/8 83 % 2W1-2, W1-2, 1-2 Vref θ = 4/8 71 % 2W1-2 Vref θ = 5/8 55 % 2W1-2, W1-2 Vref θ = 6/8 40 % 2W1-2 Vref θ = 7/8 20 %

2 Vref 100 %

PWM frequency fc 37 47 57 kHz Note: A constant-voltage power supply must be used. The design target value is shown for the current distribution ratio. Package Dimensions unit:mm (typ) 4161 12 2 53.0 0.52.0 22.0 9.0 0.4 2.9 4.0 1.0 21 2=42

No. 5227-4/19 Internal Block Diagram 7 12 13 8 6 5 2 1 CWB CLK RETURN RESET MOI MO1 MO2 ENABLE SG SUB PG BBAAVrefM5M4VCC2 Excitation mode control Excitation state monitor Phase advance counter Current distribution ratio switching Pseudo-sine wave generator Rise detection RC oscillator ITF02366 PWM controlReference clock generation Phase excitation drive signal generation Rise/fall detection and switching

No. 5227-5/19 Test Circuit Diagrams Vsat Vdf IIH, IIL Ioave, I CC, fc When measuring Ioave: With SW1 set to ‘a’, Vref = 1V When measuring fc: With SW1 set to ‘b’, Vref = 0V When measuring ICC: Set ENABLE low 6 A 15Ω A B B VCC2 VCC2 STK672-040-E Start Vref=2.5V V VCC1 ITF02367 6 A A B B STK672-040-E V A ITF02368 VCC2 STK672-040-E ITF02369 10M2 11M3 12M4 13M5 1414CLK 15CWB 16RESET 17RETURN 18ENABLE 8Vref IIL IIH A 6 A a b a b A B SW2 SW1 B VCC2 VCC2 Vref=1V 0V 0VLow when measuring ICC VCC1 VCC1 STK672-040-E ITF02370 A A Start

No. 5227-6/19 Power-on Reset The application must perform a power-on reset operation when VCC2 power is first applied to this hybrid IC. Application circuit that used 2W1-2 phase excitation (microstepping operation) mode. Setting the Motor Current The motor current IOH is set by the Vref voltage on the hybrid IC pin 8. The following formula gives the relationship between IOH and Vref. IOH = × Vref/Rs, Rs: The hybrid IC internal current detection resistor (0.33Ω ±3%) Applications can use motor currents from the current (0.05 to 0.1A) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, IOH = 1.5A Function Table M2 0 0 1 1 M3 0 1 0 1 Phase switching clock edge timing 1 2 phase excitation 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation Rising edge only 0 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation 4W1-2 phase excitation Rising and falling edges Forward Reverse ENABLE Motor current is cut off when low CWB 0 1 RESET Active low A A B B MO1 1 0 0 1 MO2 0 0 1 1 6 A A 1413 VCC2=5V VCC2=5V SG 100μF or higher PG Vref VCC2=5V CLK 1kΩ ENABLE RET RESET MoI VCC1=10V to 45V Two-phase stepping motor STK672-040-E ITF02371 B B 20Mo1 21Mo2 Motor current waveform Ioave A12395 IOL IOH

No. 5227-7/19 Printed Circuit Board Design Recommendations This hybrid IC has two grounds, the PG pins (pins 3 and 4) and the SG pin (pin 22). These are connected internally in the hybrid IC. Two power supplies are required: a motor drive supply and a 5V supply for the hybrid IC itself. If the ground connections for these supplies are not good, the motor current waveforms may become unstable, motor noise may increase, and vibration levels may increase. Use appropriate wiring for these grounds. Here we present two methods for implementing these ground connections. If the grounds for the motor drive supply and the hybrid IC 5V supply are connected in the immediate vicinity of the power supplies:

• If PG and SG are shorted at the power supply, connect only the PG line to pins 3 and 4 on the hybrid IC. Also, be sure that no problems occur due to voltage drops due to common impedances. In the specifications, this must be VCC2 ±5%.
• The current waveforms will be more stable if the Vref ground is connected to pin 22.
• For initial values, use 100μF or over for C1 and 10μF or over for C2. Locate C1 as close to the hybrid IC as possible, and the capacitor ground line must be as short as possible. If the grounds for the motor drive supply and the hybrid IC 5V supply are separated:
• Insert a capacitor (C1) of 100μF or over as close as possible to the hybrid IC. The capacitor ground line must be as short as possible. The capacitor C2 may be included if necessary. Its ground line should also be as short as possible. SG 4 PG STK672-040-E VCC2 Vref CLK SG PG C1 + ITF02372 Motor drive power supply power supply 100μF or over Stepping motor 10μF or overOscillator circuit (CLK) SG 4 PG STK672-040-E VCC2 Vref CLK SG PG C1 + ITF02373 Separation Motor drive power supply power supply 100μF or over Stepping motor 10μF or overOscillator circuit (CLK)

No. 5227-8/19 Functional Description External Excitation Chopper Drive Block Description Driver Block Basic Circuit Structure Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required. When a high level is input to φA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be input, the Q output will go high, and the MOSFET will be turned on as its initial value. The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to the latch circuit set pin occurs. In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when the motor is locked. Input Pin Functions Pin No. Symbol Function Pin circuit type

14 CLK Phase switching clock Built-in pull-up resistor CMOS Schmitt trigger input

15 CWB Rotation direction setting (CW/CCW) Built-in pull-up resistor CMOS Schmitt trigger input

17 RETURN Forced phase origin return Built-in pull-up resistor CMOS Schmitt trigger input

18 ENABLE Output cutoff Built-in pull-up resistor CMOS Schmitt trigger input

9, 10, 11 M1, M2, M3 Excitation mode setting Built-in pull-up resistor CMOS Schmitt trigger input 12, 13 M4, M5 Vector locus setting Built-in pull-up resistor CMOS Schmitt trigger input

16 RESET System reset Built-in pull-up resistor CMOS Schmitt trigger input

8 Vref Current setting Operational amplifier input

φA φA MOSFET AND Q S R 800kHz 45kHz Latch circuit Noise filter CR oscillatorDivider Current divider M4 M5 Vref A=1 Enable φA (control signal)ION

No. 5227-9/19 Input Signal Functions and Timing

• CLK (phase switching clock) 1) Input frequency range: DC to 50kHz 2) Minimum pulse width: 10μs 3) Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.) 4) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 5) Built-in multi-stage noise rejection circuit 6) Function: - When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge. - When M3 is low: The phase is advanced one step by both rising and falling edges, for a total of two steps per cycle. CLK Input Acquisition Timing (M3 = Low)
• CWB (Method for setting the rotation direction) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When CWB is low: The motor turns in the clockwise direction. - When CWB is high: The motor turns in the counterclockwise direction. 3) Notes: When M3 is low, the CWB input must not be changed for about 6.25μs before or after a rising or falling edge on the CLK input.
• RETURN (Forcible return to the origin for the currently excited phase) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Built-in noise rejection circuit 3) Notes: The currently excited (driven) phase can be forcibly moved to the origin by switching this input from low to high. Normally, if this input is unused, it must be left open or connected to VCC2.
• ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold as the internal state of this hybrid IC.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - When ENABLE is high or open: Normal operating state - When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the reset input have any effect on the hybrid IC state. Excitation counter up/down Control output switching timing CLK input System clock Phase excitation counter clock Control output timing A06845

No. 5227-10/19

• M1, M2, and M3 (Excitation mode and CLK input edge timing selection) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: M2 0 0 1 1 M3 0 1 0 1 Phase switching clock edge timing 1 2 phase excitation 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation Rising edge only 0 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation 4W1-2 phase excitation Rising and falling edges 3) Valid mode setting timing: Applications must not change the mode in the period 5μs before or after a CLK signal rising or falling edge. Mode Setting Acquisition Timing
• M4 and M5 (Microstepping mode rotation vector locus setting) M4 1 0 1 0 M5 1 0 0 1 Mode Circular See page 11 for details on the current division ratio.
• RESET (Resets all parts of the system.) 1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure 2) Function: - All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at least 10μs.) At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to about 71% after the reset is released. 3) Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must apply a power on reset when the VCC2 power supply is first applied.
• Vref (Sets the current level used as the reference for constant-current detection.) 1) Pin circuit type: Analog input structure 2) Function: - Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage VCC2 minus 2.5V. - Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5V as the upper limit. Mode switching timing Excitation counter up/down CLK input System clock Mode setting M1 to M3 Mode switching clock Hybrid IC internal setting state Phase excitation clock A06846 Phase B Phase A Circular ITF02273 2 1 3

No. 5227-11/19 Output Pin Functions Pin No. Symbol Function Pin circuit type

19 MOI Phase excitation origin monitor Standard CMOS structure

20, 21 MO1, MO2 Phase excitation sta te monitor Standard CMOS structure Output Signal Functions and Timing

• A, A, B, and B (Motor phase excitation outputs) 1) Function: - In the 4 phase and 2 phase excitation modes, a 3.75μs (typical) interval is set up between the A and A and B and B output signal transition times.
• MO1, MO2, and MOI (Phase excitation state monitors) 1) Pin circuit type: Standard CMOS structure 1) Function: - Output of the current phase excitation output state. Phase coordinate Phase A Phase B Phase A Phase B MO1 1 0 0 1 MO2 0 1 0 1 MOI outputs a 0 when each phase is at the origin, and outputs a 1 otherwise.
• Current division ratios set by M3, M4, and M5 ········· Values provided for reference purposes. Mode Circular M4 = 1 M4 = 0 M4 = 1 M4 = 1 Setting M3 = 0 M3 = 1 M5 = 1 M5 = 0 M5 = 0 M5 = 1 Units Number of steps 14 15 15 13 1/16 2W1-2 20 25 23 19 1/8 2/16 31 34 33 28 3/16 2W1-2 40 44 42 39 2/8 4/16 48 51 49 45 5/16 2W1-2 55 62 57 54 3/8 6/16 65 69 65 62 7/16 2W1-2 71 77 71 69 4/8 8/16 77 82 77 74 9/16 2W1-2 83 88 85 82 5/8 10/16 88 92 89 85 11/16 2W1-2 92 95 95 92 6/8 12/16 97 98 98 94 13/16 Current division ratio 4W1-2 2W1-2 100 100 100 100 7/8 14/16 [Load conditions] VCC1 = 24V, VCC2 = 5V, R/L = 3.5/3.8mH 21 3

No. 5227-12/19 Phase States During Excitation Switching

• Excitation phases before and after excitation mode switching <clockwise direction> B2 4 2 4 3 4 151619 A A A 1617 A A B B B2 4 282930 31 0 1 2 3 1213141516171819 2830 0 2 46 12141618 A A BB8 428 20 20 28 0 4 B2 4 A A A 1618 28 4 12 20 28 40 1618 29 31 1 923 22 8 20 10 18 1216 14 2830 420 1121 1319 1517 28 0 1216 30 0 B B A B A B 30 2 26 6 A B A B A B A B B A A B 428 2W1-2 phase → 2 phase 2W1-2 phase → 1-2 phase 2W1-2 phase → W1-2 phase W1-2 phase → 2 phase W1-2 phase → 1-2 phase W1-2 phase → 2W1-2 phase 1-2 phase → 2 phase 1-2 phase → W1-2 phase 1-2 phase → 2W1-2 phase 2 phase → 1-2 phase 2 phase → W1-2 phase 2 phase → 2W1-2 phase 28 4 1220 28 4 A B A B 29 1 28 0 4 1216 A B A B 1220 A B A B Excitation phase immediately before setting the excitation mode Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 and M2) A12399

No. 5227-13/19

• Excitation phases before and after excitation mode switching <counterclockwise direction> B2 4 0 1 1617 A A A 16 15 A A B B B2 4 282930 31 0 1 2 3 1213141516171819 2830 0 2 46 12141618 A A BB8 428 20 20 28 0 4 B2 4 A A A 28 4 0 4 1618 29 31 1 923 22 8 20 10 18 1216 14 2830 420 1121 1319 1517 28 0 1216 30 0 2 B B A B A B 30 2 26 6 A B A B A B A B B A A B 428 2W1-2 phase → 2 phase 2W1-2 phase → 1-2 phase 2W1-2 phase → W1-2 phase W1-2 phase → 2 phase W1-2 phase → 1-2 phase W1-2 phase → 2W1-2 phase 1-2 phase → 2 phase 1-2 phase → W1-2 phase 1-2 phase → 2W1-2 phase 2 phase →1-2 phase 2 phase → W1-2 phase 2 phase → 2W1-2 phase 28 4 1220 28 4 1220 28 4 A B A B 28 0 4 1216 A B A B A B A B A12400

No. 5227-14/19 Excitation Time and Timing Charts

• CLK rising edge operation CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 100% Vref A 71% 100% Vref B

2 Phase Excitation Timing Chart (M3 = 1)

Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 100% Vref A 71% 100% Vref B 1-2 Phase Excitation Timing Chart (M3 = 1) CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 100% Vref A 71% 100% Vref B W1-2 Phase Excitation Timing Chart (M3 = 1) 40% 40% 92% 92% CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 55% 100% Vref A 71% 100% Vref B 2W1-2 Phase Excitation Timing Chart (M3 = 1) 40% 20% 40% 92% 92% 83% 55% 20% 83% ITF02376

No. 5227-15/19

• CLK rising and falling edge operation CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 100% Vref A 71% 100% Vref B 1-2 Phase Excitation Timing Chart (M3 = 0) CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 100% Vref A 71% 100% Vref B W1-2 Phase Excitation Timing Chart (M3 = 0) 40% 40% 92% 92% CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI 71% 55% 100% Vref A 71% 100% Vref B 2W1-2 Phase Excitation Timing Chart (M3 = 0) 40% 20% 40% 92% 92% 83% 55% 20% 83% CLK CWB MOSFET gate signal Comparator reference voltage RESET A A B B MO1 MO2 MOI Vref A Vref B 4W1-2 Phase Excitation Timing Chart (M3 = 0) 71% 55% 65% 100% 40% 48% 20% 31% 92% 83%77% 14% 97% 88% 71% 55% 65% 100% 40% 48% 20% 31% 92% 83%77% 14% 97% 88% ITF02377

No. 5227-16/19 Thermal Design <Hybrid IC Average Internal Power Loss Pd> The main elements internal to this hybrid IC with large average power losses are the current control devices, the regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2 phase excitation. The losses in the various excitation modes are as follows. 2 phase excitation Pd 2EX = (Vsat+Vdf) · · IOH · t2 + · (Vsat · t1+Vdf · t3) 1-2 phase excitation Pd 1-2EX = 0.64 · {(Vsat+Vdf) · · IOH · t2 + · (Vsat · t1+Vdf · t3)} W1-2 phase excitation Pd W1-2EX = 0.64 · {(Vsat+Vdf) · ·IOH · t2 + · (Vsat · t1+Vdf · t3)} 2W1-2 phase excitation Pd2W1-2EX = 0.64 · {(Vsat+Vdf) · ·IOH · t2 + · (Vsat · t1+Vdf · t3)} 4W1-2 phase excitation Pd4W1-2EX = 0.64 · {(Vsat+Vdf) · ·IOH · t2 + · (Vsat · t1+Vdf · t3)} Here, t1 and t3 can be determined from the same formulas for all excitation methods. However, the formula for t2 differs with the excitation method. 2 phase excitation t2 = – (t1+t3) 1-2 phase excitation t2 = – t1 W1-2 phase excitation t2 = – t1 2W1-2 phase excitation t2 = – t1 4W1-2 phase excitation Motor Phase Current Model Figure (2 Phase Excitation) fclock : CLK input frequency (Hz) Vsat : The voltage drop of the power MOSFET and the current detection resistor (V) Vdf : The voltage drop of the body diode and the current detection resistor (V) IOH : Phase current peak value (A) t1 : Phase current rise time (s) V CC1 : Supply voltage applied to the motor (V) t2 : Constant-current operating time (s) L : Motor inductance (H) t3 : Phase switching current regeneration time (s) R : Motor winding resistance ( Ω) fclock fclockOHI · fclock fclockOHI · fclock fclockOHI · fclock fclockOHI · fclock fclockOHI · 0.88R L 1CCV 0.88R + R 0.881CCV·ROHI 0.881CCV fclock fclock fclock fclock t3 t1 t2 IOH A12401

No. 5227-17/19 <Determining the Size of the Hybrid IC Heat Sink> Determine θc-a for the heat sink from the average power loss determined in the previous item. Tc max: Hybrid IC substrate temperature ( °C) θc-a = [°C/W] Ta: Application internal temperature ( °C) Pd EX: Hybrid IC internal average loss (W) Determine θc-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below. The ambient temperature of the device will vary greatly according to the air flow conditions within the application. Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum plate side) will never exceed a Tc max of 105°C, whatever the operating conditions are. Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss from the thermal resistance of the hybrid IC substrate, namely 23°C/W. For a Tc max of 105°C at an ambient temperature of 50°C Pd EX = = 2.3W For a Tc max of 105°C at an ambient temperature of 40°C Pd EX = = 2.8W This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (See ΔTc – Pd curve in the graph on page 19.) <Hybrid IC internal power element (MOSFET) junction temperature calculation> The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal resistance θj-c. Tj = Tc + θj-c × Pds (°C) Here, we determine Pds, the loss for each transistor, by determining PdEX in each excitation mode. Pds = PdEX/4 The steady-state thermal resistance θj-c of a power MOSFET is 9.5°C/W. EXPd Ta-max Tc 50-105 40-105 IC internal average power loss, Pd - W θc-a - Pd Heat sink thermal resistance, θc-a - °C/W ITF02378 Heat sink surface area, S - cm2 θc-a - S Heat sink thermal resistance, θc-a - °C/W ITF02389 02468 1 0 1 2 1 4 1 6 40°C60°C Guaranteed ambient temperature θc-a= Tc max -- Ta (°C/W) Tc max=105°C Pd No. Fin 23.0 (°C/W) 50°C 1.0 10 23 5 7 100 23 5 No. Fin 23.0 (°C/W) 2 mm Al plate (no surface finish) (flat black surface finish) Vertical standing type Natural convection air cooling

No. 5227-18/19 ITF02380 0 4.5 5.0 5.5 6.0 Tc = 25°C fc - VCC2 PWM frequency, fc - kHz Supply voltage, VCC2 - V ITF02381 ITF02382 ITF02383 ITF02385ITF02384 ITF02386 ITF02387 0 20 40 60 80 100 120 140 VCC2 = 5V (fixed) fc - Tc PWM frequency, fc - kHz Substrate temperature, Tc - °C 0 1.0 2.0 3.0 Vsat - IOH Output saturation voltage, Vsat - V Tc = 105°C Tc = 25°C Phase output current, IOH -A 0 1.0 2.0 3.0 VCC2 = 5V (fixed) Tc=105°C Tc=25°C IOH - Vdf Phase output current, IOH - A FET diode forward voltage, Vdf - V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 03 04 05 0 Tc = 25°C 1.5A 1.0A 0.5A Vref=0V Test motor: PK244-01B IOH -V CC1 Motor output current, IOH -A Supply voltage, VCC1 - V 0.4 0.6 0.2 0.8 1.0 1.2 1.4 1.6 1.8 0 20 40 60 80 100 120 140 1.5A 1.0A 0.5A Vref=0V Test motor: PK244-01B VCC1 = 24V VCC2 = 5V IOH -T c Phase output current, IOH - A Substrate temperature, Tc - °C 100 1k 10k 50k 1-2EX 2W1-2EX, 4W1-2EX 2EX 2EX(VCC=46V IOH=1.0A) VCC1 = 24V, VCC2 = 5V Test motor: PK244-01B (R = 3.3Ω/L = 3mH) With IOH set at 1.0A ΔTc - PPS Substrate temperature increase, ΔTc - °C Input PPS - Hz W 1-2EX 0.4 0.2 0.6 0.8 1.0 1.2 10 20 30 40 50 IOH=1.0A IOH=0.5A Tc = 25°C, VCC2 = 5V PK244-01B Motor common pin current With one phase held. IM - VCC1 Motor COM current, IM - A Supply voltage, VCC1 - V VCC2 = 5V (fixed)

No. 5227-19/19 PS Motor output current, IOH, IOL, Ioave - A Vref - I Motor current setting voltage, Vref - V ITF02388 Power loss, Pd - W ΔTc - Pd(typ) Substrate temperature increase, ΔTc - °C ITF02389 0.2 0.4 0.6 1.2 0.8 1.0 1.4 1.6 0 0.5 1.0 1.5 2.0 loave IOL IOH 02 14 5 36 Self cooling for the independent (free standing) IC With no heat sink Tc = 25°C VCC1 = 24V VCC2 = 5V PK244-01B In hold mode ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.