SK10LVE111 SEMTECH | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 6

Technical content

Features

  • 200 ps Part-to-Part Skew
  • 50 ps Output-to-Output Skew
  • Differential Design BB Output
  • Voltage and Temperature Compensated Outputs
  • Low Voltage V EE Range of –3,0 to –3.8V
  • 75K Ω Internal Pulldown Resistors
  • Fully Compatible with Motorola MC100LVE111
  • Specified Over Industrial Temperature Range: –40˚C to 85˚C
  • ESD Protection of >2000V
  • Available in 28-pin PLCC Package

Description

The SK100LVE is a low skew 1-to-9 differential driver designed with clock distribution in mind. The SK100LVE111’s function and performance are similar to the SK100E111, with the added feature of low voltage operation. It accepts one signal input which can be either differential or single-ended if the V BB output is used. The signal is fanned out to 9 identical differential outputs. The device is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω , even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. October 6, 1999

28 Pin

This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Low Voltage 1:9 Differential ECL / PECL Clock Driver The SK100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE111 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage.

T oday's Results...T omorrow's Vision SK10LVE111 SK100LVE111 Low Voltage 1:9 Differential ECL/ PECL Clock Driver niP noitcnuF *NI,NI *0Q,0Q − *8Q,8Q BBV riaPtupnIlaitnereffiD stuptuOlaitnereffiD tuptuOBBV Q0* Q1* Q2* Q3* Q4* Q5* Q6* Q7* Q8* IN IN* VBB Q3* VCC0 Q4* Q5* VEE N/C IN VCC IN* VBB N/C Q8* VCC0 Q7* Q6* Q0* VCC0 Q1* Q2* 25 24 23 22 21 20 19 56 789 1 0 1 1

28 Lead PLCC

(Top View) lobmyS retemaraP gnitaR tinU V EE )V0=CCV(ylppuSrewoP5 .4-0 otV VI )V0=CCV(egatloVtupnIo t00 .4-V I TUO :tnerruCtuptuO suounitnoC egruS 001 Am Am TA egnaRerutarepmeTgnitarepO- 5 8+ot04 oC V EE )4eton(e gnaRgnitarepO8 .3-o t0 .3-V T erots egnaRerutarepmeTegarotS- 0 51+ot56 oC Absolute Maximum Ratings (Note 3)

T oday's Results...T omorrow's Vision SK10LVE111 SK100LVE111 Low Voltage 1:9 Differential ECL/ PECL Clock Driver lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU V HO egatloVHGIHtuptuO- 5 3110 98-0 801-0 48-0 201-0 18-0 19-0 27-V m V LO egatloVWOLtuptuO0 591-0 561-0 591-0 361-0 591-0 361-0 591-5 951-V m V HI egatloVHGIHtupnI0 321-0 98-0 711-0 48-0 311-0 18-0 601-0 27-V m V LI egatloVWOLtupnI0 591-0 051-0 591-0 841-0 591-0 841-0 591-5 441-V m IHI tnerruCHGIHtupnI0 510 510 510 51A µ ILI tnerruCWOLtupnI5 .05 .05 .03 .0A µ I EE tnerruCylppuSrewoP5 35 65 35 65 35 65 35 6A m TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU V HO egatloVHGIHtuptuO 7 56120 1230 2220 2420 8220 9420 9320 852V m V LO egatloVWOLtuptuO 7 05310 5610 5310 7610 5310 7610 5315 071V m V HI egatloVHGIHtupnI 7 07620 1420 3120 6420 7120 1420 4220 852V m V LI egatloVWOLtupnI 7 05310 0810 5310 2810 5310 2810 5315 581V m IHI tnerruCHGIHtupnI0 510 510 510 51V µ ILI tnerruCWOLtupnI5 .05 .05 .03 .0A µ I EE tnerruCylppuSrewoP6 66 66 66 6A m TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C (VEE = VEE (min) to VEE (max); VCC = GND) (Notes 1 and 4) (VCC = VCC (min) to VCC (max); VEE = GND) (Notes 1 and 4)

T oday's Results...T omorrow's Vision SK10LVE111 SK100LVE111 Low Voltage 1:9 Differential ECL/ PECL Clock Driver lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU IHI tnerruCHGIHtupnI0 510 510 510 51A µ I EE tnerruCylppuSrewoP5 56 65 56 65 56 65 68 7A m TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU IHI tnerruCHGIHtupnI0 510 510 510 51A µ I EE tnerruCylppuSrewoP5 56 65 56 65 56 65 68 7A m TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C (VEE = VEE (min) to VEE (max); VCC = GND) (Notes 2 and 4) (VCC = VCC (min) to VCC (max); VEE = GND) (Notes 2 and 4)

T oday's Results...T omorrow's Vision SK10LVE111 SK100LVE111 Low Voltage 1:9 Differential ECL/ PECL Clock Driver AC Characteristics (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) (Note 4) -04 oC 0oC 52 oC 58 oC lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU dnoC t HLP t LHP otyaleDnoitagaporP tuptuO )laitnereffiD(NI )dednE-elgniS(NI 004 053 056 007 534 583 526 576 044 093 036 086 544 593 536 586 sp t weks wekSeciveD-nihtiW )ffiD(wekStraP-ot-traP 052 052 052 052 sp .01 V PP gniwStupnImuminiM0 050 050 050 05V m. 11 tr t, f emiTllaF/esiR %08ot%02 0020 060 020 060 020 060 020 06s p% 02- % 08 1. 10LVE circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. Outputs are termionated through a 50Ω resistor to –2.0V. 2. The same DC parameter values apply across the full VEE range of –3.0 to –3.8V. Outputs are terminated through a 50 Ω resistor to –2.0V. 100LVE circuits are designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. Absolute maximum rating, beyond which device life may be impaired unless otherwise specificed on an individual data sheet. 4. Parametric values specified at: 10LVE Series: –3.0 to –3.8V 5. Guaranteed HIGH signal for all inputs. 6. Guaranteed LOW signal for all inputs. 7. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC. 8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of theoutp ut signal. 10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 11. V PP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output. 12. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min).

T oday's Results...T omorrow's Vision SK10LVE111 SK100LVE111 Low Voltage 1:9 Differential ECL/ PECL Clock Driver

Package Information

–L– –M– –N– 28 1 V W Y BRK D D Z X U B 0.007 (0.180) T L – M NM S S 0.007 (0.180) T L – M NM S S 0.010 (0.250) T L – M NSS S K H F 0.007 (0.180) T L – M NM S S 0.007 (0.180) T L – M NM S S MID NIM XAM NIM XAM A5 84.05 94.02 3.217 5.21 B5 84.05 94.02 3.217 5.21 C5 61.00 81.00 2.47 5.4 E0 90.00 11.09 2.29 7.2 F3 10.09 10.03 3.08 4.0 G0 50.0C SB7 2.1C SB H6 20.02 30.06 6.01 8.0 J0 20.0- -1 5.0- - K5 20.0- -4 6.0- - R0 54.06 54.03 4.118 5.11 U0 54.06 54.03 4.118 5.11 V2 40.08 40.07 0.11 2.1 W2 40.08 40.07 0.11 2.1 X2 40.06 50.07 0.12 4.1 Y- -0 20.0- -0 5.0 Z2 o 01 o 2o 01 o 1G0 14.00 34.02 4.012 9.01 MILLIMETERSINCHES Z 0.007 (0.180) T L – M NM S S 0.007 (0.180) T L – M NM S S J 0.010 (0.250) T L – M NSS S A R E C G 0.004 (0.100) –T– SEATING PLANE VIEW S VIEW S VIEW D-D NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash is 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom by up to 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch betweeen the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension to be smaller than 0.025 (0.635).