SHF-0589

SHF-0589 SIRENZA | Alldatasheet

Document overview

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Technical content

1 EDS-101242 Rev F

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for i naccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 0123456 SHF-0589 0.05-3 GHz, 2 Watt GaAs HFET Product Features

• High Linearity Performance at 1.96 GHz +33.4 dBm P1dB +46.5 dBm OIP3 +26 dBm IS-95 Channel Power +11.5 dB Gain
• +23.7 dBm W-CDMA Channel Power
• High Drain Efficiency (>50% at P1dB)

Applications

• Analog and Digital Wireless Systems
• 3G, Cellular, PCS
• Fixed Wireless, Pager Systems Sirenza Microdevices’ SHF-0589 is a high performance AlGaAs/ GaAs Heterostructure FET (HFET) housed in a low-cost sur- face-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression is +33.4 dBm when biased for Class AB operation at 7V,345mA at 1.96 GHz. The +46.5 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. lobmyS scitsiretcarahCeciveD C52,snoitidnoCtseT V SD I,V7= QD Am543= )detonesiwrehtosselnu( tseT ycneuqerF stinU niM pyT xaM xamGn iaGelbaliavAmumixaMZ S Z= S Z,* L Z= L* zHG09.0 zHG69.1 zHG41.2 Bd Bd Bd 9.22 4.71 6.61 S 12 niaGnoitresnI ]1[ ZS Z= L smhO05=z HG09.0B d1 .417 .513 .71 niaGn iaGrewoP ]2[ tiucriCnoitacilppAz HG69.1m Bd3 .015 .117 .21 3PIOt nioPtpecretnIredrOdrihTtuptuO ]2[ tiucriCnoitacilppAz HG69.1m Bd4 45 .64- Bd1Pt nioPnoisserpmoCBd1tuptuO ]2[ tiucriCnoitacilppAz HG69.1m Bd9 .134 .33- P NAHC )RPCAcBd54-(rewoPlennahC59-SIt iucriCnoitacilppAz HG69.1m Bd- 2 .62- FNe rugiFesioN ]2[ tiucriCnoitacilppAz HG69.1B d- 7 .3- I SSD tnerruCniarDdetarutaSV SD V= PSD V, SG V0=A m6 186 7116 351 gm ecnatcudnocnarTV SD V= PSD V, SG V52.0-=S m6 752 978 001 VB SG egatloVnwodkaerBecruoS-etaG ]1[ I SG neponiard,Am8.4=V - 7 1-5 1- VB DG egatloVnwodkaerBniarD-etaG ]1[ I DG V,Am8.4= SG V0.5-=V - 2 2-7 1- htRe cnatsiseRlamrehTd ael-ot-noitcnuj o W/C- 3 2- V SD egatloVgnitarepO ]3[ ecruos-niardV - - 0 .8 I QD tnerruCgnitarepO ]3[ tnecseiuq,ecruos-niardA m- - 0 84 P SSID noitapissiDrewoP ]3[ C- - 4 .2 [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain T J<140C at TL=85C. VDS * IDQ< 2.4W is recommended for continuous reliable operation. Typical Gain Performance (7V,345mA) Gain, Gmax (dB) Frequency (GHz) Gmax Gain NOT RECOMMENDED FOR NEW DESIGN

2 EDS-101242 Rev F

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com Absolute Maximum Ratings retemaraPl obmySe ulaVt inU niarDt nerruCI SD 046A m etaGdrawroFt nerruCI FSG 8.4A m tnerruCetaGesreveRI RSG 8.4A m ecruoS-ot-niarDe gatloVV SD 0.9V ecruoS-ot-etaGe gatloVV SG 0>ro5-<V rewoPtupnIFRP NI 008W m gnitarepOd aeLe rutarepmeTT L hparGeeSC ° egnaRerutarepmeTegarotST rots 1+ot04-5 6C ° noitapissiDrewoPP SIDS hparGeeSW erutarepmeTlennahCT J 561C ° esuacyamstimilesehtfoenoynadnoyebecivedsihtfonoitarepO ecivedeht,noitareposuounitnocelbailerroF.egamadtnenamrep seulavgnitarepomumixamehtdeecxetontsumtnerrucdnaegatlov .1egapnoelbatehtnideificeps MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: P DC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (°C) TL = Lead Temperature (pin 4) (°C) RTH = Thermal Resistance (°C/W) 1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-to- part precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is recommended to maintain acceptable performance (RF and thermal). 2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB). 3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance. Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each device to eliminate the effects of pinchoff process variation. 4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage should be increased to 8V to maximize P1dB. For small signal operation OIP3 may be improved by reducing the voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation limit (shown on page 1). Design Considerations and Trade-offs 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -10 20 50 80 110 140 170 Operational (Tj<140C) ABS MAX (Tj<165C) Lead Temperature (C) Total Dissipated Power (W) Power Derating Curve NOT RECOMMENDED FOR NEW DESIGN

3 EDS-101242 Rev F

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com 0123456 -40 -35 -30 -25 -20 -15 -10 0.2 0.4 0.6 0.8 1.2 02468 1 0 De-embedded S-Parameters (Z S=ZL=50 Ohms, V DS=7V, IDS=345mA, 25°°°°°C) S11, S22 vs Frequency Note: S-parameters are de-embedded to the device leads with Z S=ZL=50Ω . The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). VGS = -2.0 to 0V, 0.2V steps T=25°°°°°C DC-IV Curves VDS (V) IDS (A) Frequency (GHz) Gain, Gmax (dB) Isolation (dB) Gain & Isolation Gmax Isolation Gain qerF )zHM( V SD )V( I QD )Am( Bd1P )mBd( cBd54- lennahC rewoP )mBd( cBd55- lennahC rewoP )mBd( 3PIO ]6[ )mBd( niaG )Bd( 11S )Bd( 22S )Bd( FN )Bd( Typical Performance - Engineering Application Circuits [4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW) [5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW) [6] P OUT= +15dBm per tone, 1MHz tone spacing

3 GHz

2 GHz

6 GHz

5 GHz

4 GHz

0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0

50 MHz

1 GHz

NOT RECOMMENDED FOR NEW DESIGN

4 EDS-101242 Rev F

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com Part Number Ordering Information Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. rebmuNtraPe ziSleeRl eeR/seciveD 9850-FHS" 70 001 The part will be symbolized with the “H5” designator and a dot signifying pin 1 on the top surface of the package. Part Symbolization #niPn oitcnuFn oitpircseD 1e taGt upnIFR 2e cruoSd aelecuderotselohaivesU.dnuorgotnoitcennoC .elbissopsasdaeldnuorgotesolcsasaivecalP.ecnatcudni 3n iarDt uptuOFR 4e cruoS2 niPsaemaS Pin Description Mounting and Thermal Considerations It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple plated-through vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [CRITICAL] 4. Use 2 ounce copper to improve the PCB’s heat spreading capability. [CRITICAL] 5. Thermal transfer paste should be used between the PCB and the mounting plate to improve heat spreading capability. [RECOMMENDED] Recommended Mounting Configuration for Optimum RF and Thermal Performance SHF-0x89 Machine Screws Plated Thru Holes (0.020" DIA) Ground Plane .016 .118.019 .096 .041 .177 .068 .059 .015 .161 321 DIMENSIONS ARE IN INCHES Package Dimensions NOT RECOMMENDED FOR NEW DESIGN