SHF-0289 SIRENZA | Alldatasheet

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Technical content

1 EDS-101241 Rev E

303 S. Technology Court, Broomfield, CO 80021 Phone: ( 800) SMI-MM http://www.sirenza.com The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for i naccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices doe s not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 0123456 SHF-0289 SHF-0289Z Pb RoHS Compliant & Packag eGreen 0.05 - 6 GHz, 1.0 Watt GaAs HFET Product Features

  • Now available in Lead Free, RoHS Compliant, & Green Packaging
  • High Linearity Performance at 1.96 GHz +30 dBm P1dB +43 dBm OIP3 +23.7 dBm IS-95 Channel Power +14.6 dB Gain
  • +21.7 dBm W-CDMA Channel Power
  • High Drain Efficiency (>50% at P1dB)
  • See App Note AN-032 for circuit details

Applications

  • Analog and Digital Wireless Systems
  • 3G, Cellular, PCS
  • Fixed Wireless, Pager Systems Sirenza Microdevices’ SHF-0289 is a high performance AlGaAs/GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression for the SHF-0289 is +30dBm when biased for Class AB operation at 7V,200mA. The +43 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. The matte tin finish on Sirenza’s lead-free package utilizes a post anneal- ing process to mitigate tin whisker formation and is RoHS compliant per EU Directive 2002/95. This package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retar- dants. Symbol Devi ce C har act eri st i cs T e s t C o n d itio n s , 2 5 C V DS =7V, I DQ =200m A ( unl ess ot her wi se not ed) Test Fr equency Uni t s Mi n Typ Max Gmax Max i mu m Av ai l abl e Gai n Z S =Z S *, Z L =Z L * 0. 90 GHz 1. 96 GHz 2. 14 GHz dB dB dB 19. 5 S 21 In s e r ti o n G a i n [1 ] Z S =Z L = 50 Ohms 0. 90 GHz dB 16. 7 18. 5 20. 3 Gai n Power Gai n [2 ] Appl i cat i on Ci r cui t 1. 96 GHz dBm 13. 1 14. 6 16. 1 O IP 3 O utp ut T hird O rd e r Inte rc e p t P o int [2 ] Appl i cat i on Ci r cui t 1. 96 GHz dBm 40. 5 43. 0 - P1dB Out put 1dB Compr essi on Poi nt [2 ] Appl i cat i on Ci r cui t 1. 96 GHz dBm 28. 7 30. 2 - P CHAN I S- 95 Channel Power ( - 45dBc AC PR) Appl i cat i on Ci r cui t 1. 96 GHz dBm - 23. 7 - NF Noi se Fi gu r e [2 ] Appl i cat i on Ci r cui t 1. 96 GHz dB - 4. 0 - IDSS S a tura te d D ra in C urre nt V DS = V DSP , V GS = 0V mA 408 588 768 g m Tranconductance V DS = V DSP , V GS = - 0. 25V mS 288 396 504 BV GS Gat e- Sour ce Br eakdown Vol t age [1 ] IGS = 2. 4mA, dr ai n open V - - 17 - 15 BV GD Gat e- Dr ai n Br eakdown Vol t age [1 ] IGD = 2. 4m A, V GS = - 5. 0V V - - 22 - 17 Rt h Ther mal Resi st ance j unct i on- t o- l ead o C/ W - 41 - V DS Oper at i ng Vol t age [3 ] dr ai n- sour ce V - - 8. 0 IDQ Oper at i ng Cur r ent [3 ] dr ai n- sour ce, qui escent mA - - 280 P DI SS Power D i ssi pat i on [3 ] C- - 1 . 4 [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain T J<140C at TL=85C. VDS * IDQ< 1.4W is recommended for continuous reliable operation. Typical Gain Performance (7V,200mA) Gain, Gmax (dB) Gmax Gain Frequency (GHz)

2 EDS-101241 Rev E

303 S. Technology Court , Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -10 20 50 80 110 140 170 Operational (Tj<140C) ABS MAX (Tj<165C) Absolute Maximum Ratings Parameter Symbol Value Unit Drain Current I DS 400 mA Forward Gate Current I GSF 2.4 mA Reverse Gate Current I GSR 2.4 mA Drain-to-Source Voltage V DS +9.0 V Gate-to-Source Voltage V GS <-5 or >0 V RF Input Power P IN 400 mW Operating Lead T emperature T L See Graph °C Storage T emperature Range T stor -40 to +165 °C Power Dissipation P DISS See Graph W Channel T emperature T J +165 °C Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: P DC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (°C) TL = Lead Temperature (pin 4) (°C) RTH = Thermal Resistance (°C/W) MTTF @ TJ=150C exceeds 1E7 hours 1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-to- part precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is recommended to maintain acceptable performance (RF and thermal). 2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB). 3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance. Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each device to eliminate the effects of pinchoff process variation. 4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage should be increased to 8V to maximize P1dB. For small signal operation the OIP3 may be improved by reducing the voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipa- tion limit (shown on page 1). Design Considerations and Trade-offs Lead Temperature (C) Total Dissipated Power (W) Power Derating Curve

3 EDS-101241 Rev E

303 S. Technology Court , Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com 0123456 -40 -35 -30 -25 -20 -15 -10 De-embedded S-Parameters (Z S=ZL=50 Ohms, V DS=7V, IDS=200mA, 25°°°°°C) S11, S22 vs Frequency Note: S-parameters are de-embedded to the device leads with Z S=ZL=50Ω. The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). VGS = -2.0 to 0V, 0.2V steps T=25°°°°° C DC-IV Curves VDS (V) IDS (A) Frequency (GHz) Gain, Gmax (dB) Isolation (dB) Gain & Isolation Gmax Isolation Gain Freq (MHz) VDS (V) IDQ (mA) P1dB (dBm) -45dBc Channel Power (dBm) -55dBc Channel Power (dBm) OIP3[6] (dBm) Gain (dB) S11 (dB) S22 (dB) NF (dB) Typical Performance - Engineering Application Circuits (See App Note AN-032) [4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW) [5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW) [6] P OUT= +13dBm per tone, 1MHz tone spacing 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0

3 GHz

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50 MHz

1 GHz

0.1 0.2 0.3 0.4 0.5 0.6 0.7 012345678

4 EDS-101241 Rev E

303 S. Technology Court , Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com Part Number Ordering Information Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. The part will be symbolized with the “H2” designator and a dot signifying pin 1 on the top surface of the package. Part Symbolization Pin # Function Description

1 Gate RF Input

2 Source Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. 3D r a i n R F O u t p u t

4 Source Same as Pin 2

Mounting and Thermal Considerations It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple plated- through vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [CRITICAL] 4. Use 2 ounce copper to improve the PCB’s heat spreading capability. [RECOMMENDED] Recommended Mounting Configuration for Optimum RF and Thermal Performance SHF-0x89 Machine Screws Plated Thru Holes (0.020" DIA) Ground Plane .016 .118.019 .096 .041 .177 .068 .059 .015 .161 321 DIMENSIONS ARE IN INCHES Package Dimensions Part Number Reel Size Devices/Reel SHF-0289 7" 1000 SHF-0289Z 7" 1000 3123 H2Z 3123