SHC804

SHC804 BURR-BROWN | Alldatasheet

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Technical content

©1983 Burr-Brown Corporation PDS-512E Printed in U.S.A. March, 1998 Switch Drive Sample/Hold Analog Input Sample/ Hold Output Hold Analog Common 1000Ω 1000Ω CH International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 High Speed SAMPLE/HOLD AMPLIFIER

FEATURES

G 350ns max ACQUISITION TIME G ±0.01% THROUGHPUT NONLINEARITY G 150ns max SAMPLE-TO-HOLD SETTLING TIME G 24-PIN HERMETICALLY-SEALED METAL PACKAGE The ±25ps maximum aperture uncertainty of the SHC804 permits sampling (to ±0.01% of Full Scale Range) of signals with rates of change of up to 100V/µs. This component is capable of accurately digitizing fast changing signals at sample rates as high as 500k samples per second. The digital inputs (HOLD and HOLD) are TTL- compatible. Power supply requirements are ±15V and +5V and the specification temperature range is –25°C to +85°C. The SHC804 is packaged in a 24-pin dual- in-line hermetic metal package. SHC804 is pin-com- patible with other sample/holds on the market with similar performance characteristics.

DESCRIPTION

The SHC804 is a high speed sample/hold amplifier designed for use in fast 12-bit data acquisition systems and signal processing systems. The SHC804 acquires a 10V signal change in less than 350ns to ±1/2LSB at 12 bits. Throughput nonlinearity error is guaranteed to be within ±1/2LSB for 12-bit systems. Stability over temperature is excellent, with only ±5ppm/°C of gain drift and ±4ppm of FSR/°C of charge offset drift over the –25 to +85°C temperature range. SHC804

At +25°C, rated power supplies and a 1kΩ output load, unless otherwise specified. SHC804BM SHC804CM PARAMETER MIN TYP MAX MIN TYP MAX UNITS SAMPLE/HOLD INPUTS (without Input Buffer) ANALOG Voltage Range ±10.25 ±11 V RIN 1.00 kΩ DIGITAL (HOLD, HOLD) VIH +2.0 V VIL +0.8 V IIH, VIN = +2.7V +60 µA IIL, VIN = +0.4V –1.2 mA SAMPLE/HOLD TRANSFER CHARACTERISTICS (without Input Buffer) ACCURACY Sample Mode Gain V/V Gain Error ±0.1 Temperature Coefficient ±10 ppm/°C Linearity Error ±0.001 ±0.005 % of FSR(1) Zero Offset ±0.5 mV Temperature Coefficient ±2.5 ±0.5 ±1.5 ppm of FSR/°C Hold Mode Charge Offset ±10 mV Temperature Coefficient ±10 ppm of FSR/°C Droop Rate: at +25°C ±0.5 µV/µs +85°C ±0.5 ±0.1 mV/µs Throughput Nonlinearity ±0.01 % of FSR Power Supply Sensitivity(2): ±VCC ±0.002 % of FSR/%VCC VDD ±0.003 % of FSR/%VDD DYNAMIC CHARACTERISTICS Acquisition Time (with 10V Step) to within: ±0.1% (±10mV) 220 ns ±0.01% (±1mV) 250 350 ns Sample-to-Hold Settling Time to within ±0.01% (±1mV) 100 150 ns Sample-to-Hold Transient Amplitude 150 mVPEAK Aperture Delay TIme(3) ns Aperture Uncertainty ±10 ±25 ps Sample Mode: Output Slew Rate 160 V/µs Full Power Bandwidth MHz Small Signal Bandwidth MHz Hold Mode Feedthrough Rejection (10V Square Wave Input) ±0.03 ±0.005 SAMPLE/HOLD OUTPUT Voltage Range ±10.25 ±11 V Output Current ±50 mA Short Circuit Protection Indefinite to Common Output Impedance (at DC) 0.01 0.1 Ω POWER SUPPLY REQUIREMENTS Rated Voltage: ±VCC ±13.5 ±15 ±16.5 V VDD +4.75 +5.00 +5.25 V Quiescent Current (No Load) SHC804: +VCC mA –VCC mA VDD mA SHC803: +VCC mA –VCC mA VDD mA Power Dissipation: SHC804 700 875 mW TEMPERATURE RANGE Specification –25 +85 Storage –55 +125 6 Specification same as SHC804BM. NOTES: (1) FSR means Full Scale Range and is 20V for SHC804. (2) Sensitivity of offset plus charge offset. (3) With respect to HOLD. For HOLD add 5ns typical. (4) With buffer connected to the sample/hold amplifier.

ABSOLUTE MAXIMUM RATINGS(1)

PACKAGE INFORMATION

NUMBER(1) SHC804BM 24-Pin 037 SHC804CM 24-Pin 037 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. CONNECTION DIAGRAMS Analog Output NC NC NC NC NC NC NC VDD DCOM Hold Hold +VCC VCC COM –VCC COM NC NC NC NC NC COM S/H In Digital Power Supply COM Analog Power Supply +15V COM –15V 1µF 1µF Signal Source VOUT SHC804CM, BM +5V NC The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN NAME Logic “1” = HOLD HOLD Logic “0” = HOLD S/H In SHC804 input NC Not connected COM Signal common NC Not connected NC Not connected NC Not connected NC Not connected NC Not connected COM Signal common –VCC –15V supply VCC COM Analog to power common, connected to case +VCC +15V supply PIN ASSIGNMENTS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

to 1µF tantalum bypass capacitors at each supply pin. present when the Hold command is given. be corrected by Offset and Gain adjustments. current and the input bias current of the output amplifier. output stops tracking the input. when the sample/hold is switched from Hold to Sample. the gate capacitance of the switching field effect transistor. This charge appears as an offset at the output. settling time of the transient are specified. low output impedance to external loads. to-digital converter following the sample/hold. FIGURE 1. Definition of Acquisition Time, Droop and

Care must be taken when loading the output of the SHC804 to avoid possible oscillations, current limiting and perfor- mance variations over temperature. The maximum capacitive load to avoid oscillations is about 300pF. Recommended resistive load is 500Ω or more, al- though values as low as 250Ω may be used. Acquisition and sample-to-hold settling times are relatively unaffected by resistive loads down to 250Ω in parallel with capacitive loads up to 100pF. Higher capacitances will affect acquisi- tion and settling times. ANALOG SIGNAL SOURCE CONSIDERATIONS The output impedance of the signal source driving the SHC804 will affect the accuracy of the sample and hold operation both statically (at DC) and dynamically. The output impedance of the signal source should be low and remain low over a wide bandwidth. A small capacitor at the driving source may help to improve the charge offset errors that are affected by dynamic source impedance.