SHC5320 BURR-BROWN | Alldatasheet
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1 SHC5320
FEATURES
l ACQUISITION TIME TO 0.01%: 1.5µs max l HOLD MODE SETTLING TIME: 350ns max l DROOP RATE AT +25 °C: 0.5µV/µs max l TTL COMPATIBLE l FULL DIFFERENTIAL INPUTS l INTERNAL HOLDING CAPACITOR l TWO TEMPERATURE RANGES: –40°C to +85°C (KH, KP, KU) –55°C to +125°C (SH) l PACKAGE OPTIONS: Ceramic and Plastic DIP-14, SO-16
DESCRIPTION
The SHC5320 is a bipolar, monolithic, sample/hold circuit designed for use in precision, high-speed, data- acquisition applications. The circuit employs an input transconductance ampli- fier capable of providing large amounts of charging current to the holding capacitor, thus enabling fast acquisition times. It also incorporates a low leakage analog switch and an output integrating amplifier with input bias current optimized to assure low droop rates. Since the analog switch always drives into a load at virtual ground, charge injection into the holding ca- pacitor is constant over the entire input voltage range. As a result, the charge offset (pedestal voltage) result- ing from this charge injection can be adjusted to zero by use of the offset adjustment capability. The device includes an internal holding capacitor to simplify ease of application; however, provision is also made to add additional external capacitance to improve the output voltage droop rate. The SHC5320 is manufactured using a dielectric iso- lation process which minimizes stray capacitance (en- abling higher-speed operation), and eliminates latch- up associated with substrate SCRs. The SHC5320KH, KP, and KU feature fully specified operation over the extended industrial temperature range of –40°C to +85°C, while the SHC5320SH operates over the tem- perature range of –55°C to +125°C. The device re- quires ±15V supplies for operation, and is packaged in a reliable 14-pin ceramic or plastic dual-in-line pack- age, as well as a 16-pin surface mount plastic package. FPO
APPLICATIONS
l PRECISION DATA ACQUISITION SYSTEMS l DIGITAL-TO-ANALOG CONVERTER DEGLITCHER l AUTO ZERO CIRCUITS l PEAK DETECTORS 100pF Output Bandwidth Control Reference Common External Hold Capacitor Offset Adjust –Input +Input Mode Control High-Speed, Bipolar, Monolithic SAMPLE/HOLD AMPLIFIER © 1985 Burr-Brown Corporation PDS-585G Printed in U.S.A. April, 2000 For most current data sheet and other product information, visit www.burr-brown.com International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
At +25°C, rated power supplies, gain = +1, and with internal holding capacitor, unless otherwise noted. SHC5320KH, KP, KU SHC5320SH PARAMETERS MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS ANALOG Voltage Range ±10 [ V Common-Mode Range ±10 [ V Input Resistance 1 5 [[ M Ω Input Capacitance 3 [ pF Bias Current ±100 ±300 ±70 ±200 nA Bias Current Over Temperature Range ±300 ±200 nA Offset Current ±30 ±300 [ ±100 nA Offset Current Over Temperature Range ±300 ±100 nA DIGITAL (Over Temperature Range) V IH (Logic “1”) 2.0 [ V VIL (Logic “0”) 0.8 [ V IIH (VI = +5V) 0.1 [ µA IIL (VI = 0V) 4 [ µA Logic “0” = SAMPLE Logic “1” = HOLD OUTPUT CHARACTERISTICS Voltage Range ±10 [ V Current ±10 [ mA Output Impedance (Hold Mode) 1 [ Ω Noise, DC to 10MHz: Sample Hold 125 200 [[ µVrms Hold Mode 125 200 [[ µVrms DC ACCURACY/STABILITY Gain, Open Loop, DC 3 x 10 5 2 x 106 106 [ V/V Input Offset Voltage ±0.5 ±0.2 mV Input Offset Voltage Over Temperature Range ±1.5 ±2m V Input Offset Voltage Drift ±5 ±20 [ ±15 µV/°C CMRR (1) 72 90 80 [ dB Power Supply Rejection(2):+ VCC 80 [ dB –VCC 65 [ dB HOLD-TO-SAMPLE MODE DYNAMIC CHARACTERISTICS Acquisition Time, A = –1, 10V Step(3): SAMPLE MODE Gain-Bandwidth Product (Gain = +1)(4): C H = 100pF 2 [ MHz C H = 1000pF 180 [ kHz Full Power Bandwidth(5) 600 [ kHz Slew Rate(6) 45 [ V/µs Rise Time(4) 100 [ ns Overshoot(4) 15 [ % SAMPLE-TO-HOLD MODE DYNAMIC CHARACTERISTICS Aperture Time(7) 25 [ ns Effective Aperture Time –50 –25 0 [[[ ns Aperture Uncertainty (Aperture Jitter) 0.3 [ ns Charge Offset (Pedestal)(8) (Adjustable to Zero) 1 5 [[ mV Charge Transfer(8) 0.1 0.5 [[ pC Sample-to-Hold Transient Settling Time to ±0.01% of FSR 165 350 [[ ns HOLD MODE Droop(9) 0.08 0.5 [[ µV/µs Droop at Maximum Temperature(9) 1.2 100 17 [ µV/µs Drift Current(9) 85 0 [[ pA Drift Current at Maximum Temperature(9) 0.12 10 1.7 [ nA Feedthrough, 10Vp-p, 100kHz Sinewave 2 [ mV The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
3 SHC5320
–Input +Input Offset Adjustment Offset Adjustment CC Reference Common Output Mode Control Supply Common NC External Hold Capacitor NC CC Bandwidth Control SHC5320KH, KP SHC5320KU –Input +Input Offset Adjustment Offset Adjustment NC CC Reference Common Output Mode Control Supply Common NC NC External Hold Capacitor NC CC Bandwidth Control PIN CONNECTIONS A < +150°C CAUTION: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. NOTES: (1) Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. Absolute maximum ratings apply to both dice and package parts, unless otherwise noted. (2) Internal power dissipation may limit output current to less than +20mA. (3) WARNING: This device cannot withstand even a momentary short circuit to either supply. ABSOLUTE MAXIMUM RATINGS (1) Top View SO SPECIFICATIONS (Cont.) At +25°C, rated power supplies, gain = +1, and with internal holding capacitor, unless otherwise noted. SHC5320KH, KP, KU SHC5320SH PARAMETERS MIN TYP MAX MIN TYP MAX UNITS POWER SUPPLIES +ICC (+VCC = 15V)(9) 11 13 [[ mA –ICC (–VCC = 15V)(9) –11 –13 [[ mA TEMPERATURE Specification –40 +85 –55 +125 °C Storage –65 +150 [[ °C PACKAGE Hermetic Ceramic, Plastic DIP, SO [ Specification the same as SCH5320KH, KP, KU. NOTES: (1) VCM = ±5VDC. (2) Based on a ±0.5V swing for each supply with all other supplies held constant. (3) VO = 10V step, RL = 2kΩ , CL = 50pF. (4) VO = 200mVp-p, R L = 2kΩ , CL = 50pF. (5) VIN = 20Vp-p, RL = 2kΩ , CL = 50pF, unattenuated output. (6) VO = 20V step, RL = 2kΩ , CL = 50pF. (7) Simulated only, not tested. (8) VIN = 0V, VIH = +3.5V, tR < 20ns (VIL to VIH). (9) Specified for zero differential input voltage between pins 1 and 2. Supply current will increase with differential input (as may occur in the Hold mode) to approximately ±28mA average at 20V differential. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA SHC5320KH CERDIP-14 163 –40 °C to +85°C SHC5320KH SHC5320KH Rail SHC5320KP DIP-14 010 –40 °C to +85°C SHC5320KP SHC5320KP Rail SHC5320KU SO-16 211 –40 °C to +85°C SHC5320KU SHC5320KU Rail "" " " SHC5320KU SHC5320KU/1K Tape and Reel SHC5320SH CERDIP-14 163 –55 °C to +125°C SHC5320SH SHC5320SH Rail NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “SHC5320KU/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL PERFORMANCE CURVES ±VCC = 15V. TYPICAL SAMPLE/HOLD PERFORMANCE AS FUNCTION OF HOLDING CAPACITOR 100 1000 10 100 1M 1.0 0.5 0.1 0.05 0.01 Charge Offset Error (mV) Voltage Droop (mV/100ms) during Hold Mode Acquisition Time (µs) for 10V Step to ±0.01% C Value (pF) H CHARGE OFFSET vs MODE CONTROL (V ) VOLTAGEIH 2.0 1.5 1.0 0.5 Hold Step Voltage (mV) 12345 +25°C +75°C C = 100pFH Logic Level High (V) OPEN-LOOP GAIN AND PHASE RESPONSE 120 100 Gain (dB) Frequency (Hz) 10 100 1k 10k 100k 1M 10M C H = 1100pF C H = 100pFG G θ –45 135 180 225 Phase (degrees) DRIFT CURRENT vs TEMPERATURE 10k 100 –50 Temperature (°C) –25 0 25 50 75 100 125 C = 100pFH I (pA)DRIFT
5 SHC5320
FIGURE 2. Illustration of Sample/Hold Specifications. changing very rapidly when the Hold mode is initiated. signal by the amount of the effective aperture delay time. of the input at the precise time the Hold mode is initiated. signal, MFE would be 0.000122V/V. cally in Figure 2, and in the Typical Performance Curves. FIGURE 1. Ideal Sample/Hold Amplifier.
Charge Offset (pedestal) is the output voltage change that results from charge transfer into the hold capacitor through stray capacitance when the Hold mode command is given. This charge appears as an offset voltage at the output, and in some sample/hold amplifiers may be a function of the input voltage. Charge offset is specified for the SHC5320 using only the internal holding capacitor. When an external capacitor is added, charge offset is calculated as Charge Transfer (pC) divided by total hold capacitance. Charge Transfer is also specified for the SHC5320, and total hold capacitance is the sum of the internal hold capacitor value (100pF) and the external hold capacitor. Since charge transfer is not a func- tion of analog input voltage for the SHC5320, this error may be removed by means of the offset adjustment capability of the amplifier. Droop Rate is the change in output voltage over time during the Hold mode as a result of hold capacitor leakage, switch leakage, and bias current of the output amplifier. Droop rate varies with temperature and the quality of the external holding capacitor, if used. Careful circuit layout is also required to minimize droop. Drift Current is the net leakage current affecting the hold capacitor during the Hold mode. With knowledge of the drift current, droop can be calculated as: Droop (V/s) = I D (pA)/CH (pF) Hold Mode Feedthrough is the fraction of the input signal which appears at the output while in the Hold mode. It is primarily a function of switch capacitance, but may also be increased by poor layout practices. Hold Mode Settling Time is the time required for the sample- to-hold transient to settle within a specified error band. OPERATING INSTRUCTIONS (Developed Around 14-Pin Package) OFFSET ADJUSTMENT The offset should be adjusted with the input grounded. During the adjustment, the sample/hold should be switching continuously between the Sample and the Hold modes. The offset should then be adjusted to zero output for the periods when the amplifier is in the Hold mode. In this way, the effects of both amplifier offset and charge offset will be accounted for. SAMPLE/HOLD CONTROL A TTL logic “0” applied to pin 14 switches the SHC5320 into the Sample (track) mode. In this mode, the device acts as an amplifier which exhibits normal operational amplifier behavior, with the relationship of output to input signal depending upon the circuit configuration selected (see the Installation section below). Application of a logic “1” to pin 14 switches the SHC5320 into the Hold mode, with the output voltage held constant at the value present when the hold command is given. Pin 14 presents less than one LSTTL load to the driving circuit throughout the full oper- ating temperature range. ADDITION OF AN EXTERNAL CAPACITOR The SHC5320 contains an internal 100pF MOS holding capacitor, sufficient for most high-speed applications. If improved droop performance is desired (with increased acquisition time), additional capacitance may be added be- tween pins 7 and 11. If an external holding capacitor C H is used, then a noise-bandwidth capacitor with a value 0.1CH should be connected from pin 8 to ground. The exact value and type of this bandwidth capacitor are not critical. Capacitors with high insulation resistance and low dielectric absorption, such as Teflon ® or polystyrene units, should be used as storage elements (polystyrene should not be used above +85°C). Care should be taken in the printed circuit layout to minimize leakage currents from the capacitor to minimize droop errors. The value of the external capacitor determines the droop, charge offset, and acquisition time of the sample/hold. Both droop and charge offset will vary linearly with total hold capacitance from the values given in the specification table for the internal 100pF capacitor. The behavior of acquisition time versus total hold capacitance is shown in the Typical Performance Curves. OUTPUT PROTECTION In order to optimize high-frequency performance of this device, output protection is not included. This high fre- quency performance is mandatory for a good sample/hold, which must absorb high-frequency changes in load current when driving a successive-approximation A/D converter. Due to the lack of output protection, the output circuit will not tolerate an indefinite short to common, but a momentary short is permissible. The output should never be shorted to a supply. INSTALLATION (Developed Around 14-Pin Package) LAYOUT PRECAUTIONS Since the holding capacitor is connected to virtual ground at one end (pin 11) and to a low-impedance voltage source at the other (pin 7), the SHC5320 does not require the use of guard rings and other careful layout techniques which are required by many sample/hold circuits. However, normal good layout practice should be observed, minimizing the possibility of leakage paths across the holding capacitor. As in all digital-analog circuits, analog signal lines on the circuit board should cross digital signal paths at right angles whenever possible. GROUNDING AND BYPASSING Pin 6 (Reference Common) should be connected to the system analog signal common as close to the unit as pos- sible. Likewise, pin 13 (Supply Common) should be con- nected to the system supply common. If the system design prevents running these two common lines separately, they should be connected together close to the unit, preferably to Teflon® Du Pont Corporation
7 SHC5320
ply terminal of the device to pin 13 (Supply Common). a 10kΩ , 10-turn potentiometer as illustrated in Figure 3. FIGURE 5. Noninverting Configuration with Gain = 1 + R2/R1. nected to act as an inverting amplifier, as shown in Figure 6. FIGURE 6. Inverting Configuration with Gain = –(R2/R1). FIGURE 3. Connection of Offset Adjustment Potentiometer. FIGURE 4. Noninverting Unity-Gain Connections. non-inverting mode equal that of the inverting mode.
9 SHC5320
FIGURE 10. PAM Output. voltages to different loads (see Figure 11). or MPC507A) may be required in front of the sample/hold. overlapped mode with the sample/holds. FIGURE 11. Typical Data Distribution Configuration.
FIGURE 12. Typical Overlapped Sample/Hold Configuration.