SH7243

SH7280 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 SH7286, SH7285, and SH7243 Features
• 1.2 Block Diagram
• 1.3 Pin Assignment
• 1.4 Pin Functions
• 2.1 Register Configuration
• 2.1.1 General Registers
• 2.1.2 Control Registers
• 2.1.3 System Registers
• 2.1.4 Register Banks
• 2.1.5 Initial Values of Registers
• 2.2 Data Formats
• 2.2.1 Data Format in Registers
• 2.2.2 Data Formats in Memory
• 2.2.3 Immediate Data Format
• 2.3 Instruction Features
• 2.3.1 RISC-Type Instruction Set
• 2.3.2 Addressing Modes
• 2.3.3 Instruction Format
• 2.4 Instruction Set
• 2.4.1 Instruction Set by Classification
• 2.4.2 Data Transfer Instructions
• 2.4.3 Arithmetic Operation Instructions
• 2.4.4 Logic Operation Instructions
• 2.4.5 Shift Instructions
• 2.4.6 Branch Instructions
• 2.4.7 System Control Instructions
• 2.4.8 Bit Manipulation Instructions
• 2.5 Processing States
• 3.1 Selection of Operating Modes
• 3.2 Input/Output Pins

Revision Date: Jun. 26, 2008

32 Hardware Manual

Renesas 32-Bit RISC Microcomputer SuperH TM RISC engine family Rev. 1.00 REJ09B0393-0100 SH7280 Group

Rev. 1.00 Jun. 26, 2008 Page ii of xxx

Rev. 1.00 Jun. 26, 2008 Page iii of xxx 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev. 1.00 Jun. 26, 2008 Page iv of xxx General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

Rev. 1.00 Jun. 26, 2008 Page v of xxx How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the SH7280 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Contents Document Title Document No. Data Sheet Overview of hardware and electrical characteristics   Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation SH7280 Group Hardware Manual This manual Software Manual Detailed descriptions of the CPU and instruction set SH-2A, SH2A-FPU Software Manual REJ09B0051 Application Note Exampl es of applications and sample programs Renesas Technical Update Preliminary report on the specifications of a product, document, etc. The latest versions are available from our web site.

Rev. 1.00 Jun. 26, 2008 Page vi of xxx 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (1) Overall notation (2) Register notation Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4) (3) (2) Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (3) Number notation An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. (4) Notation for active-low When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.

Rev. 1.00 Jun. 26, 2008 Page vii of xxx 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (1) Bit (2) Bit name Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (3) Initial value For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: R/(W): The bit or field is readable and writable. The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) R/W Describes the function of the bit or field and specifies the values for writing. (5) Description Bit 13 to 11 All 0 R R/W R R Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. ASID2 to ASID0 Bit Name Initial Value R/WDescription [Bit Chart] [Table of Bits] 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000001000000000 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W  ASID2  ACMP2Q IFE ASID1 ASID0 ACMP1 ACMP0 − 0 R Reserved These bits are always read as 0.

Rev. 1.00 Jun. 26, 2008 Page viii of xxx 4. Description of Abbreviations The abbreviations used in this manual are listed below.

• Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller SCI Serial communication interface WDT Watchdog timer
• Abbreviations other than those listed above Abbreviation Description ACIA Asynchronous communication interface adapter bps Bits per second CRC Cyclic redundancy check DMA Direct memory access DMAC Direct memory access controller GSM Global System for Mobile Communications Hi-Z High impedance IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) I/O Input/output IrDA Infrared Data Association LSB Least significant bit MSB Most significant bit NC No connection PLL Phase-locked loop PWM Pulse width modulation SFR Special function register SIM Subscriber Identity Module UART Universal asynchronous receiver/transmitter VCO Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners.

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4.8.3 Handling of pins when a Ceramic Resonator is not Connected

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6.3.1 Interrupt Priority Registers 01, 02, 05 to 18

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6.9.1 Handling Interrupt Request Signals as DTC Activating Sources

6.9.2 Handling Interrupt Request Signals as DMAC Activating Sources

6.9.3 Handling Interrupt Request Signals as DTC Activating Sources

6.9.4 Handling Interrupt Request Signals as CPU Interrupt Sources

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8.9.5 Transfer Information Start Address, Source Address, and Destination Address242

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11.3.11 Timer A/D Converter Start Request Cycle Set Registers

11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers

Rev. 1.00 Jun. 26, 2008 Page xvii of xxx 11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection .. 641

11.7.19 Cautions on Transition from Normal Operation

11.7.20 Output Level in Complementary PWM Mode

11.8.4 Overview of Initialization Procedures and Mode Transitions

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16.7.5 Receive Data Sampling Timing and Receive Margin

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17.6.6 Receive Data Sampling Timing and Receive Margin

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20.3.4 A/D Analog Input Channel Select Registers 0 to 2

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23.1.3 Port A Pull-Up MOS Control Registers H and L

23.1.5 Port B Control Registers H1 and L1 to L4

23.1.11 Port D Control Registers H1 to H4 and L1 to L4

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26.8.1 Specifications of the Standard Serial Communications Interface

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30.1 Register Addresses

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Rev. 1.00 Jun. 26, 2008 Page 1 of 1692 REJ09B0393-0100 Section 1 Overview

1.1 SH7286, SH7285, and SH7243 Features

This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set and uses a superscalar architecture and a Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high- functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a large-capacity ROM, a ROM cache, a RAM, a direct memory access controller (DMAC), a data transfer controller (DTC), multi-function timer pulse units 2 (MTU2 and MTU2S), a serial communication interface with FIFO (SCIF), a serial communication interface (SCI), a synchronous serial communication interface (SSU), an A/D converter, a D/A converter, an interrupt controller (INTC), I/O ports, I C bus interface 3 (IIC3), a universal serial bus (USB), and a controller area network (RCAN-ET). This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. The features of this LSI are listed in table 1.1.

Rev. 1.00 Jun. 26, 2008 Page 2 of 1692 REJ09B0393-0100 Table 1.1 SH7286, SH7285, and SH7243 Features Items Specification CPU • Renesas Technology original SuperH architecture

• Compatible with SH-1 and SH-2 at object code level
• 32-bit internal data bus
• Support of an abundant register-set  Sixteen 32-bit general registers  Four 32-bit control registers  Four 32-bit system registers  Register bank for high-speed response to interrupts
• RISC-type instruction set (upward compatible with SH series)  Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability  Load/store architecture  Delayed branch instructions  Instruction set based on C language
• Superscalar architecture to execute two instructions at one time
• Instruction execution time: Up to two instructions/cycle
• Address space: 4 Gbytes
• Internal multiplier
• Five-stage pipeline Operating modes • Operating modes Extended ROM enabled mode Single-chip mode
• Processing states Program execution state Exception handling state Bus mastership release state
• Power-down modes Sleep mode Software standby mode Module standby mode

Rev. 1.00 Jun. 26, 2008 Page 3 of 1692 REJ09B0393-0100 Items Specification ROM cache • Instruction/data separation system

• Instruction prefetch cache: Full/set associative
• Instruction prefetch miss cache: Full/set associative
• Data cache: Full/set associative
• Line size: 16 bytes
• Hardware prefetch function (continuous/branch prefetch) Interrupt controller (INTC)
• Nine external interrupt pins (NMI and IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt processing Bus state controller (BSC)
• Address space divided into eight areas (0 to 7), each a maximum of 64 Mbytes
• External bus: 8, 16, or 32 bits (32-bit bus available only in SH7286)
• The following features settable for each area independently  Supports both big endian and little endian for data access  Bus size (8, 16, or 32 bits): Available sizes depend on the area.  Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas)  Idle wait cycle insertion (between same area access cycles or different area access cycles)
• SDRAM refresh Auto refresh or self refresh mode selectable
• SDRAM burst access Direct memory access controller (DMAC)
• Eight channels; external request available for four (SH7286) and two (SH7285 and SH7243) of them
• Can be activated by on-chip peripheral modules
• Burst mode and cycle steal mode
• Intermittent mode available (16 and 64 cycles supported)
• Transfer information can be automatically reloaded

Rev. 1.00 Jun. 26, 2008 Page 4 of 1692 REJ09B0393-0100 Items Specification Data transfer controller (DTC)

• Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU. A CPU interrupt can be requested after one data transfer completion.
• A CPU interrupt can be requested after all specified data transfer completion. Clock pulse generator (CPG)
• Clock mode: Input clock can be selected from external input (EXTAL) or crystal resonator
• Input clock can be multiplied by 8 (max.) by the internal PLL circuit
• Five types of clocks generated:  CPU clock: Maximum 100 MHz  Bus clock: Maximum 50 MHz  Peripheral clock: Maximum 50 MHz  Timer clock: Maximum 100 MHz  AD clock: Maximum 50 MHz Watchdog timer (WDT)
• On-chip one-channel watchdog timer
• A counter overflow can reset the LSI Power-down modes • Three power-down modes provided to reduce the current consumption in this LSI  Sleep mode  Software standby mode  Module standby mode

Rev. 1.00 Jun. 26, 2008 Page 5 of 1692 REJ09B0393-0100 Items Specification Multi-function timer pulse unit 2 (MTU2)

• Maximum 16 lines of pulse input/output and 3 lines of pulse input based on six channels of 16-bit timers
• 21 output compare and input capture registers
• Input capture function
• Pulse output modes Toggle, PWM, and complementary PWM
• Synchronization of multiple counters
• Complementary PWM output mode  Non-overlapping waveforms output for 3-phase inverter control  Automatic dead time setting  0% to 100% PWM duty value specifiable  A/D conversion delaying function  Interrupt skipping at crest or trough
• Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value
• Phase counting mode Two-phase encoder pulse counting available Multi-function timer pulse unit 2S (MTU2S)
• Subset of MTU2, included in channels 3 to 5
• Operating at 100 MHz max. Port output enable 2 (POE2)
• High-impedance control of high-current pins at a falling edge or low- level input on the POE pin Compare match timer (CMT)
• Two-channel 16-bit counters
• Four types of clock can be selected (Pφ/8, Pφ/32, Pφ/128, and Pφ/512)
• DMA transfer request or interrupt request can be issued when a compare match occurs Serial communication interface (SCI)
• Four channels (SH7285 and SH7286) Two channels (SH7243)
• Clocked synchronous or asynchronous mode selectable
• Simultaneous transmission and reception (full-duplex communication) supported
• Dedicated baud rate generator

Rev. 1.00 Jun. 26, 2008 Page 6 of 1692 REJ09B0393-0100 Items Specification Serial communication interface with FIFO (SCIF)

• One channel
• Clocked synchronous or asynchronous mode selectable
• Simultaneous transmission and reception (full-duplex communication) supported
• Dedicated baud rate generator
• Separate 16-byte FIFO registers for transmission and reception Synchronous serial communication unit (SSU) (only in SH7285 and SH7286)
• One channel
• Master mode or slave mode selectable
• Standard mode or bidirectional mode selectable
• Transmit/receive data length can be selected from 8, 16, and 32 bits.
• Simultaneous transmission and reception (full-duplex communication) supported
• Consecutive serial communication Universal serial bus (USB) (only in SH7285 and SH7286)
• USB 2.0 full-speed mode (12 Mbps) supported
• Internal bus transceiver available
• Standard commands automatically processed by hardware
• Three transfer modes (control transfer, balk transfer, and interrupt transfer)
• 16 types of interrupt sources available
• DMA transfer interface Controller area network (RCAN-ET) (only in SH7286)
• CAN version: Bosch 2.0B active is supported
• Buffer size: 15 buffers for transmission/reception and one buffer for reception only
• One channel I C bus interface 3 (IIC3) (only in SH7285 and SH7286)
• One channel
• Master mode and slave mode supported I/O ports • Input or output can be selected for each bit

Rev. 1.00 Jun. 26, 2008 Page 7 of 1692 REJ09B0393-0100 Items Specification A/D converter • Three modules (SH7286) Two modules (SH7285 and SH7243)

• 12-bit resolution
• Eight input channels (SH7285 and SH7243) and twelve input channels (SH7286)
• Sampling can be carried out simultaneously on three channels.
• A/D conversion request by the external trigger or timer trigger D/A converter (only in SH7286)
• 8-bit resolution
• Two output channels ASE break controller (ABC)
• Ten break channels
• The cycle of the internal bus can be set as break conditions User break controller (UBC)
• Four break channels
• Addresses, data values, type of access, and data size can all be set as break conditions User debugging interface (H-UDI)
• E10A emulator support
• JTAG-standard pin assignment
• Realtime branch trace Advanced user debugger (AUD)
• Six input/output pins
• Branch source address/destination address trace
• Window data trace
• Full trace All trace data can be output by interrupting CPU operation
• Realtime trace Trace data can be output within the range where CPU operation is not interrupted On-chip ROM • 256 Kbytes, 512 Kbytes, 768 Kbytes, or 1 Mbyte On-chip RAM • Four pages
• 32 Kbytes (SH7286, SH7285)
• 24 Kbytes (SH7286, SH7285)
• 12 Kbytes (SH7243)
• 8 Kbytes (SH7243) Power supply voltage • VCC: 3.0 to 3.6 V or 4.5 to 5.5 V
• AVCC: 4.5 to 5.5 V

Rev. 1.00 Jun. 26, 2008 Page 8 of 1692 REJ09B0393-0100 Items Specification

• LQFP2424-176 (0.5 pitch): R5F72867, R5F72866, R5F72865
• LQFP2020-176 (0.4 pitch): R5F72867, R5F72866, R5F72865
• LQFP1414-100 (0.5 pitch): R5F72434, R5F72433

Rev. 1.00 Jun. 26, 2008 Page 9 of 1692 REJ09B0393-0100

1.2 Block Diagram

controller (UBC) Bus state controller (BSC) Peripheral bus controller Direct memory access controller (DMAC) Pin function controller (PFC) I/O ports Clock pulse generator (CPG) Interrupt controller (INTC) Multi-function timer pulse unit 2S (MTU2S) Multi-function timer pulse unit 2 (MTU2) Port output enable 2 (POE2) Compare match timer (CMT) Internal bus (B clock) Peripheral bus (P clock) Watchdog timer (WDT) Serial communication interface (SCI) Synchronous serial communication interface (SSU) Serial communication interface with FIFO (SCIF) I2C bus interface 3 (IIC3) 12-bit A/D converter (ADC) Power-down mode control User debugging interface (H-UDI) CPU instruction fetch bus (F bus) CPU bus (C bus) (I clock)CPU memory access bus (M bus) Data transfer controller (DTC) Controller area network (RCAN-ET) D/A converter (DAC) Universal serial bus (USB) *1*2 *1*2 Notes: 1. Only in SH7286 and SH7285 2. Only in SH7286 Figure 1.1 Block Diagram

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1.3 Pin Assignment

(Top view) PE14/DACK0/TIOC4C/AH PE15/DACK1/TIOC4D/IRQOUT VCC VCL VSS PA23/CKE/TIC5W/POE0/IRQ1/AH PA22/CASU/CASL/TIC5V/POE4/IRQ2 PA21/RASU/RASL/TIC5U/POE8/IRQ3 PC0/A0/POE0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 VCC VSS PC13/A13/IRQ0 PC14/A14/IRQ1 PC15/A15/IRQ2 PB0/A16/IRQ3 PB1/A17/REFOUT/ADTRG/IRQ4 PB2/SCL/POE1/IRQ0 PB3/SDA/POE2/IRQ1 PB6/A18/BACK/POE3/IRQ5/RXD0 PB7/A19/BREQ/POE4/IRQ6/TXD0 PB8/A20/WAIT/POE8/IRQ7/SCK0 VCC VSS PD0/D0 PD1/D1 PD2/D2/TIC5U PD3/D3/TIC5V PD4/D4/TIC5W PD5/D5/TIC5US PD6/D6/TIC5VS PD7/D7/TIC5WS VCC PB13/CTx0 PB12/TXD2/CS7/CS1/IRQ1/CS3 PB11/RXD2/CS6/CS0/IRQ0/CS VSS VCC PE6/TIOC2A/TIOC3DS/SCK3 PE5/TIOC1B/TIOC3BS/TXD3 PE4/TIOC1A/RXD3 PE3/TIOC0D/TIOC4DS/TEND1 PE2/TIOC0C/TIOC4CS/DREQ1 PE1/TIOC0B/TIOC4BS/TEND0 PE0/TIOC0A/TIOC4AS/DREQ0 VCL PLLVSS VSS NMI EXTAL VCC XTAL VSS PB10 DrVss USD- USD+ DrVCC VBUS PB9/USPND USBEXTAL USBXTAL VSS VCC PB19/RASU/A25/DREQ2 PB18/RASL/A24/DACK2 PB17/CASU/A23/DREQ3 PB16/CASL/A22/DACK3 PB15/CKE/A21 VSS VCC TRST TMS TCK TDO TDI RES FWE/ASEBRKAK/ASEBRK ASEMD0 AVSS AVCC PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVREF AVREFVSS AVCC AVSS PF8/AN8 PF9/AN9 PF10/AN10 PF11/AN11 AVREF AVREFVSS AVCC AVSS DA0 DA1 MD0 MD1 WDTOVF PA0/RXD0/CS0 PA1/TXD0/CS1 PA2/SCK0/SCS/CS2 PA3/RXD1/SSI/CS3 PA4/TXD1/SSO/CS4 PA5/SCK1/SSCK/CS5 PE7/TIOC2B/RXD2/BS/UBCTRG VSS PE8/TIOC3A/SCK2 PE10/TIOC3C/TXD2 PE9/TIOC3B/FRAME PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES VSS VCC PA6/RASL/TCLKA PA7/CASL/TCLKB/SCK3 PA8/TCLKC/TXD3/RDWR PA9/CKE/TCLKD/RXD3 PA10/WRHL/DQMUL PA11/WRHH/DQMUU/AH PA12/WRH/DQMLU/POE8 PA13/WRL/DQMLL PA14/RD PA15/CK VSS VCC PD31/D31/TIOC3AS/ADTRG PD30/D30/TIOC3CS/IRQOUT PD29/D29/TIOC3BS PD28/D28/TIOC3DS PD27/D27/TIOC4AS/DACK0 PD26/D26/TIOC4BS/DACK1 PD25/D25/TIOC4CS/DREQ1 VSS VCC PD24/D24/DREQ0/TIOC4DS/AUDCK PD23/D23 PD22/D22/IRQ6/TIC5US/RXD4/AUDSYNC PD21/D21/IRQ5/TIC5VS/TXD4 PD20/D20/IRQ4/TIC5WS/SCK4//POE8 PD19/D19/IRQ3/POE7/RXD3/CS0/AUDATA3 PD18/D18/IRQ2/POE6/TXD3/CS1/AUDATA2 PD17/D17/IRQ1/POE5/SCK3/CS2/AUDATA1 PD16/D16/IRQ0/CS3/AUDATA0 VSS VCC VCL PD15/D15/TIOC4DS PD14/D14/TIOC4CS PD13/D13/TIOC4BS PD12/D12/TIOC4AS PD11/D11/TIOC3DS PD10/D10/TIOC3BS PD9/D9/TIOC3CS PD8/D8/TIOC3AS VSS 109110111112113114115116117118119120121122123124125126127128129130131132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 1 0 1 11 21 31 41 5 1 61 7 1 81 92 02 12 22 32 42 52 62 7 2 82 93 03 13 23 33 43 53 6 108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89 4443424140393837 PB14/CRx0 Figure 1.2 SH7286 Pin Assignment

Rev. 1.00 Jun. 26, 2008 Page 11 of 1692 REJ09B0393-0100 LQFP-144 (Top view) PE14/DACK0/TIOC4C/AH PE15/DACK1/TIOC4D/IRQOUT VCC VCL VSS PA23/TIC5W/POE0/IRQ1/AH/CKE PA22/TIC5V/CASU/POE4/IRQ2/CASL PA21/TIC5U/RASU/POE8/IRQ3/RASL PC0/A0/POE0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 VCC VSS PC13/A13/IRQ0 PC14/A14/IRQ1 PC15/A15/IRQ2 PB0/A16/IRQ3 PB1/A17/REFOUT/ADTRG/IRQ4 PB2/SCL/POE1/IRQ0 PB3/SDA/POE2/IRQ1 PB6/A18/BACK/POE3/IRQ5/RXD0 PB7/A19/BREQ/POE4/IRQ6/TXD0 PB8/A20/WAIT/POE8/IRQ7/SCK0 VCC VSS PD0/D0 PE6/TIOC2A/TIOC3DS/SCK3 PE5/TIOC1B/TIOC3BS/TXD3 PE4/TIOC1A/RXD3 PE3/TIOC0D/TIOC4DS/TEND1 PE2/TIOC0C/TIOC4CS/DREQ1 PE1/TIOC0B/TIOC4BS/TEND0 PE0/TIOC0A/TIOC4AS/DREQ0 VCL PLLVSS VSS NMI EXTAL VCC XTAL VSS PB10 DrVSS USD- USD+ DrVCC VBUS PB9/USPND USBEXTAL USBXTAL VSS PA6/TCLKA/RASL PA7/TCLKB/SCK3/CASL PA8/TCLKC/TXD3/RDWR PA9/TCLKD/RXD3/CKE PA12/WRH/DQMLU/POE8 PA13/WRL/DQMLL PA14/RD PA15/CK VSS VCC PD31/TIOC3AS/ADTRG VCC VSS PB11/RXD2/CS6/CS2/CS0/IRQ0 PB12/TXD2/CS7/CS3/CS1/IRQ1 RES FWE/ASEBRKAK/ASEBRK ASEMD0 AVSS AVCC PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVREF AVREFVSS MD0 MD1 WDTOVF PA0/RXD0/CS0/TDI PA1/TXD0/CS1/TDO PA2/SCK0/SCS/CS2/TCK PA3/RXD1/SSI/CS3/TMS PA4/TXD1/SSO/CS4/TRST PA5/SCK1/SSCK/CS5 PE7/TIOC2B/RXD2/BS/UBCTRG VSS PE8/TIOC3A/SCK2 PE10/TIOC3C/TXD2 PE9/TIOC3B PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PD30/TIOC3CS/IRQOUT PD29/TIOC3BS PD28/TIOC3DS PD27/TIOC4AS/DACK0 PD26/TIOC4BS/DACK1 PD25/TIOC4CS/DREQ1 VSS VCC PD24/DREQ0/TIOC4DS/AUDCK PD22/IRQ6/TIC5US/RXD4/AUDSYNC PD21/IRQ5/TIC5VS/TXD4 PD20/IRQ4/TIC5WS/SCK4/POE8 PD19/IRQ3/POE7/RXD3/CS0/AUDATA3 PD18/IRQ2/POE6/TXD3/CS1/AUDATA2 PD17/IRQ1/POE5/SCK3/CS2/AUDATA1 PD16/IRQ0/CS3/AUDATA0 VSS VCC VCL PD15/D15/TIOC4DS PD14/D14/TIOC4CS PD13/D13/TIOC4BS PD12/D12/TIOC4AS PD11/D11/TIOC3DS PD10/D10/TIOC3BS PD9/D9/TIOC3CS PD8/D8/TIOC3AS VSS VCC PD7/D7/TIC5WS PD6/D6/TIC5VS PD5/D5/TIC5US PD4/D4/TIC5W PD3/D3/TIC5V PD2/D2/TIC5U PD1/D1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 12 3456 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Figure 1.3 SH7285 Pin Assignment

Rev. 1.00 Jun. 26, 2008 Page 12 of 1692 REJ09B0393-0100 LQFP-100 (Top view) PE14/DACK0/TIOC4C PE15/DACK1/TIOC4D/IRQOUT VCC VCL VSS PC0/A0/POE0/TDI PC1/A1/TDO PC2/A2/TCK PC3/A3/TMS PC4/A4/TRST PC5/A5 PC6/A6 PC7/A7 VCC VSS PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13/IRQ0 PC14/A14/IRQ1 PC15/A15/IRQ2 VCC VSS VSS VCC PB12/TXD2/CS7/CS1/IRQ1/CS3 PB11/RXD2/CS6/CS0/IRQ0/CS PE6/TIOC2A/TIOC3DS/SCK3 PE5/TIOC1B/TIOC3BS/TXD3 PE4/TIOC1A/RXD3 PE3/TIOC0D/TIOC4DS/TEND1 PE2/TIOC0C/TIOC4CS/DREQ1 PE1/TIOC0B/TIOC4BS/TEND0 PE0/TIOC0A/TIOC4AS/DREQ0 VCL PLLVSS NMI EXTAL VCC XTAL VSS PA6/TCLKA/RASL PA7/TCLKB/SCK3/CASL PA8/TCLKC/TXD3/RDWR PA9/TCLKD/RXD3/CKE PA12/WRH/DQMLU/POE8 PA13/WRL/DQMLL PA14/RD RES FWE/ASEBRKAK/ASEBRK ASEMD0 AVSS AVCC PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVREF AVREFVSS MD0 MD1 WDTOVF PE7/TIOC2B/RXD2/BS/UBCTRG PE8/TIOC3A/SCK2 PE10/TIOC3C/TXD2 PE9/TIOC3B PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES 100 12 3456 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA15/CK VSS PD15/D15/TIOC4DS PD14/D14/TIOC4CS PD13/D13/TIOC4BS PD12/D12/TIOC4AS PD11/D11/TIOC3DS PD10/D10/TIOC3BS PD9/D9/TIOC3CS PD8/D8/TIOC3AS/AUDCK VSS VCC PD7/D7/TIC5WS/AUDATA3 PD6/D6/TIC5VS/AUDATA2 PD5/D5/TIC5US/AUDATA1 PD4/D4/TIC5W/AUDATA0 PD3/D3/TIC5V/AUDSYNC PD2/D2/TIC5U PD1/D1 PD0/D0 PB8/A20/WAIT/POE8/IRQ7/SCK0 PB7/A19/BREQ/POE4/IRQ6/TXD0 PB6/A18/BACK/POE3/IRQ5/RXD0 PB1/A17/ADTRG/REFOUT/IRQ4 PB0/A16/IRQ3 Figure 1.4 SH7243 Pin Assignment

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1.4 Pin Functions

Table 1.2 lists functions of each pin. Table 1.2 Pin Functions Classification Symbol I/O Name Function VCC Input Power supply Power supply pins. All the VCC pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. VSS Input Ground Ground pins. All the VSS pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. VCL Input Internal step- down power supply External capacitance pins for internal step-down power supply. All the VCL pins must be connected to VSS via a 0.47-µF capacitor (should be placed close to the pins). Power supply PLLVSS Input Ground for PLL Ground pin for the on-chip PLL oscillator. EXTAL Input External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. XTAL Output Crystal Connect ed to a crystal resonator. USBEXTAL Input Crystal for USB Connec ted to a resonator for the USB. USBXTAL Output Crystal for USB Conn ected to a resonator for the USB. Clock CK Output System clock Supplies the system clock to external devices.

Rev. 1.00 Jun. 26, 2008 Page 14 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function MD1, MD0 Input Mode set Sets the operating mode. Do not change the signal levels on these pins during operation. ASEMD0 Input Debugging mode Enables the E10A-USB emulator functions. Input a high level to operate the LSI in normal mode (not in debugging mode). To operate it in debugging mode, apply a low level to this pin on the user system board. Operating mode control FWE Input Flash memory write enable Pin for flash memory. Flash memory can be protected against writing or erasure through this pin. RES Input Power-on reset This LSI enters the power-on reset state when this signal goes low. MRES Input Manual reset This LS I enters the manual reset state when this signal goes low. WDTOVF Output Watchdog timer overflow Outputs an overflow signal from the WDT. BREQ Input Bus-mastership request A low level is input to this pin when an external device requests the release of the bus mastership. System control BACK Output Bus-mastership request acknowledge Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus.

Rev. 1.00 Jun. 26, 2008 Page 15 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function NMI Input Non-maskable interrupt Non-maskable interrupt request pin. Fix it high when not in use. IRQ7 to IRQ0 Input Interrupt requests 7 to 0 Maskable interrupt request pins. Level-input or edge-input detection can be selected. When the edge-input detection is selected, the rising edge, falling edge, or both edges can also be selected. Interrupts IRQOUT Output Interrupt request output Indicates that an interrupt has occurred, enabling external devices to be informed of an interrupt occurrence even while the bus mastership is released. Address bus A25 to A0 Output Address bus Outputs addresses. (A25 to A21 are available only in the SH7286.) Data bus D31 to D0 I/O Data bus Bi directional data bus. (D31 to D16 are available only in the SH7286.) Bus control CS7 to CS0 Output Chip select 7 to 0 Chip-select signals for external memory or devices. RD Output Read Indicates that data is read from an external device. RD/ WR Output Read/write Read/write signal. BS Output Bus start Bus-cycle start signal. AH Output Address hold Address hold timing signal for the device that uses the address/data- multiplexed bus. FRAME Output Frame signal In burst MPX-I/O interface mode, negated before the last bus cycle to indicate that the next bus cycle is the last access (only in SH7286) WAIT Input Wait Input signal for inserting a wait cycle into the bus cycles during access to the external space. WRHH Output Write to HH byte Indicates a write access to bits 31 to 24 of data of external memory or device (only in SH7286). WRHL Output Write to HL byte Indicates a write access to bits 23 to 16 of data of external memory or device (only in SH7286).

Rev. 1.00 Jun. 26, 2008 Page 16 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function WRH Output Write to upper byte Indicates a write access to bits 15 to 8 of data of external memory or device. WRL Output Write to lower byte Indicates a write access to bits 7 to 0 of data of external memory or device. DQMUU Output HH byte selection Selects bits D31 to D24 when SDRAM is connected (only in SH7286). DQMUL Output HL byte selection Selects bits D23 to D16 when SDRAM is connected (only in SH7286). DQMLU Output Upper byte selection Selects bits D15 to D8 when SDRAM is connected. DQMLL Output Lower byte selection Selects bits D7 to D0 when SDRAM is connected. RASU Output RAS Connected to the RAS pin when SDRAM is connected (only in SH7286). CASU Output CAS Connected to the CAS pin when SDRAM is connected (only in SH7286). RASL Output RAS Connected to the RAS pin when SDRAM is connected. CASL Output CAS Connected to the CAS pin when SDRAM is connected. CKE Output CK enable Connected to the CKE pin when SDRAM is connected. Bus control REFOUT Output Refresh request output Request signal output for refresh execution while the bus mastership is released. DREQ0 to DREQ3 Input DMA-transfer request Input pins to receive external requests for DMA transfer (DREQ2 and DREQ3 are only in SH7286). DACK0 to DACK3 Output DMA-transfer request accept Output pins for signals indicating acceptance of external requests from external devices (DACK2 and DACK3 are only in SH7286). Direct memory access controller (DMAC) TEND1, TEND0 Output DMA-transfer end output Output pins for DMA transfer end.

Rev. 1.00 Jun. 26, 2008 Page 17 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function TCLKA, TCLKB, TCLKC, TCLKD Input MTU2 timer clock input External clock input pins for the timer. TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A, TIOC1B I/O MTU2 input capture/output compare (channel 1) The TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TIOC2A, TIOC2B I/O MTU2 input capture/output compare (channel 2) The TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O MTU2 input capture/output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O MTU2 input capture/output compare (channel 4) The TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. Multi-function timer pulse unit 2 (MTU2) TIC5U, TIC5V, TIC5W Input MTU2 input capture (channel 5) The TGRU_5, TGRV_5, and TGRW_5 input capture input/dead time compensation input pins. Port output enable (POE) POE8 to POE0 Input Port output control Request signal input to place the MTU2 and MTU2S waveform output pin in the high impedance state (SH7243 has only POE8, POE4, POE3, and POE0).

Rev. 1.00 Jun. 26, 2008 Page 18 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function TIOC3AS, TIOC3BS, TIOC3CS, TIOC3DS I/O MTU2S input capture/output compare (channel 3) The TGRA_3S to TGRD_3S input capture input/output compare output/PWM output pins. TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS I/O MTU2S input capture/output compare (channel 4) The TGRA_4S and TGRB_4S input capture input/output compare output/PWM output pins. Multi-function timer pulse unit 2S (MTU2S) TIOC5US, TIOC5VS, TIOC5WS Input MTU2S input capture (channel 5) The TGRU_5S, TGRV_5S, and TGRW_5S input capture input/dead time compensation input pins. TXD4, TXD2 to TXD0 Output Transmit data Data output pins. Only TXD2 and TXD0 are available in the SH7243. RXD4, RXD2 to RXD0 Input Receive data Data input pins. Only RXD2 and RXD0 are available in the SH7243. Serial communication interface (SCI) SCK4, SCK2 to SCK0 I/O Serial clock Clock input/output pins. Only SCK2 and SCK0 are available in the SH7243. TXD3 Output Transmit data Data output pin. RXD3 Input Receive data Data input pin. Serial communication interface with FIFO (SCIF) SCK3 I/O Serial clock Clock input/output pin. SSO I/O Data Data input/output pin. SSI I/O Data Data input/output pin. SSCK I/O Clock Clock input/output pin. Synchronous serial communication unit (SSU) (only in SH7285 and SH7286) SCS I/O Chip select Chip select input/output pin.

Rev. 1.00 Jun. 26, 2008 Page 19 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function DrVCC Input USB power supply Power supply pin for the internal transceiver. Connect it to the 3.3-V power supply. DrVSS Input USB ground Ground pin for the internal transceiver. USD+, USD− I/O USB data USB data input/output pins. VBUS Input Cable connection monitor USB cable connection monitor input pin. Universal serial bus (USB) (only in SH7285 and SH7286) USPND Output Suspend state output Outputs a high level when the suspend state is entered. CTx0 Output Transmit data Transmit data pin for CAN bus. Controller area network (RCAN-ET) (only in SH7286) CRx0 Input Receive data Receive data pin for CAN bus. SCL I/O Serial clock pin Seri al clock input/output pin. I C bus interface 3 (IIC3) (only in SH7285 and SH7286) SDA I/O Serial data pin Seri al data input/output pin. AN11 to AN0 Input Analog input pins Analog input pins. Only AN7 to AN0 are available in the SH7285 and SH7243. ADTRG Input A/D conversion trigger input External trigger input pin for starting A/D conversion. AVCC Input Analog power supply Power supply pin for the A/D converter. Connect this pin to the system power supply (VCC) when the A/D converter is not used. AVREF Input Analog reference power supply Reference voltage pin for the A/D converter. AVSS Input Analog ground Ground pi n for the A/D converter. Connect this pin to the system power supply (VSS) when the A/D converter is not used. A/D converter AVREFVSS Input Analog reference ground Reference ground pin for the A/D converter. Connect this pin to the system power supply (VSS) when the A/D converter is not used.

Rev. 1.00 Jun. 26, 2008 Page 20 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function D/A converter (only in SH7286) DA1, DA0 Output Analog output pins Analog output pins. PA23 to PA21, PA15 to PA0 I/O General port 19-bit general input/output port pins. Only PA23 to PA21, PA15 to PA12, and PA9 to PA0 are available in the SH7285. Only PA15 to PA12 and PA9 to PA6 are available in the SH7243. PB19 to PB6, PB3 to PB0 I/O General port 16-bit general input/output port pins. Only PB12 to PB6 and PB3 to PB0 are available in the SH7285. Only PB12, PB11, PB8 to PB6, PB1, and PB0 are available in the SH7243. PC15 to PC0 I/O General port 16-bit general input/output port pins. PD31 to PD0 I/O General port 32-bit general input/output port pins. Only PD31 to PD24 and PD22 to PD0 are available in the SH7285. Only PD15 to PD0 are available in the SH7243 PE15 to PE0 I/O General port 16-bit general input/output port pins. I/O ports PF11 to PF0 Input General port 12-bit general input port pins. Only PF7 to PF0 are available in the SH7285 and SH7243. TCK Input Test clock Test-clock input pin. TMS Input Test mode select Test -mode select signal input pin. TDI Input Test data input Serial input pin for instructions and data. TDO Output Test data output Serial output pin for instructions and data. User debugging interface (H-UDI) TRST Input Test reset Initializat ion-signal input pin. Input a low level when not using the H-UDI.

Rev. 1.00 Jun. 26, 2008 Page 21 of 1692 REJ09B0393-0100 Classification Symbol I/O Name Function AUDATA3 to AUDATA0 Output AUD data Branch dest ination/source address output pin AUDCK Output AUD clock Sync clock output pin Advanced user debugger (AUD) AUDSYNC Output AUD sync signal Data start-position acknowledge- signal output pin ASEBRKAK Output Break mode acknowledge Indicates that the E10A-USB emulator has entered its break mode. Emulator interface ASEBRK Input Break request E10A-U SB emulator break input pin. User break controller (UBC) UBCTRG Output User break trigger output Trigger output pin for UBC condition match.

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Rev. 1.00 Jun. 26, 2008 Page 23 of 1692 REJ09B0393-0100 Section 2 CPU

2.1 Register Configuration

The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers.

2.1.1 General Registers

Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15. 31 0 R0*1 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer) Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers

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2.1.2 Control Registers

The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 0 1 TS 23456789 I[3:0]QM 1314 CSBO Status register (SR) 31 0 GBR Global base register (GBR) VBR Vector base register (VBR) TBR Jump table base register (TBR) Figure 2.2 Control Registers (1) Status Register (SR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 RRRRRRRRRRRRRRRR 000000- -111100- - R R/W R/W R R R R/W R/W R/W R/W R/W R/W R R R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: - BO CS - - - M Q I[3:0] - - S T

Rev. 1.00 Jun. 26, 2008 Page 25 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 31 to 15 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

14 BO 0 R/W BO Bit

Indicates that a register bank has overflowed.

13 CS 0 R/W CS Bit

Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value. 12 to 10 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 M — R/W

8 Q — R/W

Used by the DIV0S, DIV0U, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W Interrupt Mask Level 3, 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 S — R/W S Bit

Specifies a saturation operation for a MAC instruction.

0 T — R/W T Bit

True/false condition or carry/borrow bit (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR) VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR) TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.

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2.1.3 System Registers

The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC indicates the program address being executed and controls the flow of the processing. 31 0 31 0 PC PR MACL MACH Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations. Procedure register (PR): Stores the return address from a subroutine procedure. Program counter (PC): Indicates the four bytes ahead of the current instruction. Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL) MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction. (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC indicates the address of the instruction being executed.

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2.1.4 Register Banks

For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. For details, refer to section 6.8, Register Banks, and the SH-2A, SH2A-FPU Software Manual.

2.1.5 Initial Values of Registers

Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Classification Register Initial Value R0 to R14 Undefined General registers R15 (SP) Value of the sta ck pointer in the vector address table SR Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined GBR, TBR Undefined Control registers VBR H'00000000 MACH, MACL, PR Undefined System registers PC Value of the program counter in the vector address table

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2.2 Data Formats

2.2.1 Data Format in Registers

Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 Longword Figure 2.4 Data Format in Registers

2.2.2 Data Formats in Memory

Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5. 31 01523 7 Byte Byte Byte Byte WordWordAddress 2n Address 4n Longword Address m Address m + 2 Address m + 1 Address m + 3 Figure 2.5 Data Formats in Memory

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2.2.3 Immediate Data Format

Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data.

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2.3 Instruction Features

2.3.1 RISC-Type Instruction Set

Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2 Sign Extension of Word Data SH2-A CPU Description Example of Other CPU MOV.W @(disp,PC),R1 ADD R1,R0 .DATA.W H'1234 Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. ADD.W #H'1234,R0 Note: @(disp, PC) accesses the immediate data. (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory.

Rev. 1.00 Jun. 26, 2008 Page 31 of 1692 REJ09B0393-0100 (6) Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction → delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3 Delayed Branch Instructions SH-2A CPU Description Example of Other CPU BRA TRGET ADD R1,R0 Executes the ADD before branching to TRGET. ADD.W R1,R0 BRA TRGET (7) Unconditional Branch Instructions with No Delay Slot The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations 16-bit × 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four cycles. (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed.

Rev. 1.00 Jun. 26, 2008 Page 32 of 1692 REJ09B0393-0100 Table 2.4 T Bit SH-2A CPU Description Example of Other CPU CMP/GE R1,R0 BT TRGET0 BF TRGET1 T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 < R1. CMP.W R1,R0 BGE TRGET0 BLT TRGET1 ADD #−1,R0 CMP/EQ #0,R0 BT TRGET T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. SUB.W #1,R0 BEQ TRGET (10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediat e Data Accessing Classification SH-2A CPU Example of Other CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOVI20 #H'1234,R0 MOV.W #H'1234,R0 20-bit immediate MOVI20 #H'12345,R0 MOV.L #H'12345,R0 28-bit immediate MOVI20S #H'12345,R0 OR #H'67,R0 MOV.L #H'1234567,R0 32-bit immediate MOV.L @(disp,PC),R0 .DATA.L H'12345678 MOV.L #H'12345678,R0 Note: @(disp, PC) accesses the immediate data.

Rev. 1.00 Jun. 26, 2008 Page 33 of 1692 REJ09B0393-0100 (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing Classification SH-2A CPU Example of Other CPU Up to 20 bits MOVI20 #H'12345,R1 MOV.B @R1,R0 MOV.B @H'12345,R0 21 to 28 bits MOVI20S #H'12345,R1 OR #H'67,R1 MOV.B @R1,R0 MOV.B @H'1234567,R0 29 bits or more MOV.L @(disp,PC),R1 MOV.B @R1,R0 .DATA.L H'12345678 MOV.B @H'12345678,R0 (12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing Classification SH-2A CPU Example of Other CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 .DATA.W H'1234 MOV.W @(H'1234,R1),R2

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2.3.2 Addressing Modes

Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Equation Register direct Rn The effective address is register Rn. (The operand is the contents of register Rn.) Register indirect @Rn The effective address is the contents of register Rn. Rn Rn Rn Register indirect with post- increment @Rn+ The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn 1/2/4 +Rn + 1/2/4 Rn (After instruction execution) Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Register indirect with pre- decrement @-Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction is executed with Rn after this calculation)

Rev. 1.00 Jun. 26, 2008 Page 35 of 1692 REJ09B0393-0100 Addressing Mode Instruction Format Effective Address Calculation Equation Register indirect with displacement @(disp:4, Rn) The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zero- extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn Rn + disp × 1/2/4+ 1/2/4 disp (zero-extended) Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Register indirect with displacement @(disp:12, Rn) The effective address is the sum of Rn and a 12- bit displacement (disp). The value of disp is zero- extended. Rn disp (zero-extended) Rn + disp Byte: Rn + disp Word: Rn + disp Longword: Rn + disp Indexed register indirect @(R0,Rn) The effective address is the sum of Rn and R0. Rn Rn + R0+ Rn + R0 GBR indirect with displacement @(disp:8, GBR) The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR 1/2/4 GBR + disp × 1/2/4+ disp (zero-extended) Byte: GBR + disp Word: GBR + disp × Longword: GBR + disp ×

Rev. 1.00 Jun. 26, 2008 Page 36 of 1692 REJ09B0393-0100 Addressing Mode Instruction Format Effective Address Calculation Equation Indexed GBR indirect @(R0, GBR) The effective address is the sum of GBR value and R0. GBR GBR + R0+ GBR + R0 TBR duplicate indirect with displacement (disp:8, TBR) The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4. TBR TBR + disp × 4 (TBR + disp × 4)4 +disp (zero-extended) Contents of address (TBR + disp × 4) PC indirect with displacement @(disp:8, PC) The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC H'FFFFFFFC PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 & (for longword) disp (zero-extended) Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4

Rev. 1.00 Jun. 26, 2008 Page 37 of 1692 REJ09B0393-0100 Addressing Mode Instruction Format Effective Address Calculation Equation PC relative disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the sign- extended 8-bit displacement (disp). PC disp (sign-extended) PC + disp × 2 PC + disp × 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the sign- extended 12-bit displacement (disp). PC disp (sign-extended) PC + disp × 2 PC + disp × 2 Rn The effective address is the sum of PC value and Rn. PC Rn PC + Rn+ PC + Rn

Rev. 1.00 Jun. 26, 2008 Page 38 of 1692 REJ09B0393-0100 Addressing Mode Instruction Format Effective Address Calculation Equation The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended. Sign- extended imm (20 bits) 31 19 0 — Immediate #imm:20 The 20-bit immediate data (imm) for the MOVI20S instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero. Sign-extended imm (20 bits) 00000000 31 27 8 0 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. #imm:3 The 3-bit immediate data (imm) for the BAND, BOR, BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location.

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2.3.3 Instruction Format

The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows:

• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement Table 2.9 Instruction Formats Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxxxxxx 15 0 — — NOP — nnnn: Register direct MOVT Rn Control register or system register nnnn: Register direct STS MACH,Rn R0 (Register direct) nnnn: Register direct DIVU R0,Rn Control register or system register nnnn: Register indirect with pre- decrement STC.L SR,@-Rn mmmm: Register direct R15 (Register indirect with pre- decrement) MOVMU.L Rm,@-R15 R15 (Register indirect with post- increment) nnnn: Register direct MOVMU.L @R15+,Rn n format xxxx xxxx xxxxnnnn 15 0 R0 (Register direct) nnnn: (Register indirect with post- increment) MOV.L R0,@Rn+

Rev. 1.00 Jun. 26, 2008 Page 40 of 1692 REJ09B0393-0100 Instruction Formats Source Operand Destination Operand Example mmmm: Register direct Control register or system register LDC Rm,SR mmmm: Register indirect with post- increment Control register or system register LDC.L @Rm+,SR mmmm: Register indirect — JMP @Rm mmmm: Register indirect with pre- decrement R0 (Register direct) MOV.L @-Rm,R0 m format xxxxmmmmxxxx xxxx 15 0 mmmm: PC relative using Rm — BRAF Rm mmmm: Register direct nnnn: Register direct ADD Rm,Rn mmmm: Register direct nnnn: Register indirect MOV.L Rm,@Rn mmmm: Register indirect with post- increment (multiply- and-accumulate) nnnn*: Register indirect with post- increment (multiply- and-accumulate) MACH, MACL MAC.W @Rm+,@Rn+ mmmm: Register indirect with post- increment nnnn: Register direct MOV.L @Rm+,Rn mmmm: Register direct nnnn: Register indirect with pre- decrement MOV.L Rm,@-Rn nm format nnnnxxxx xxxx 15 0 mmmm mmmm: Register direct nnnn: Indexed register indirect MOV.L Rm,@(R0,Rn) md format xxxx dddd 15 0 mmmmxxxx mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rm),R0

Rev. 1.00 Jun. 26, 2008 Page 41 of 1692 REJ09B0393-0100 Instruction Formats Source Operand Destination Operand Example nd4 format xxxxxxxx dddd 15 0 nnnn R0 (Register direct) nnnndddd: Register indirect with displacement MOV.B R0,@(disp,Rn) mmmm: Register direct nnnndddd: Register indirect with displacement MOV.L Rm,@(disp,Rn) nmd format nnnnxxxx dddd 15 0 mmmm mmmmdddd: Register indirect with displacement nnnn: Register direct MOV.L @(disp,Rm),Rn mmmm: Register direct nnnndddd: Register indirect with displacement MOV.L Rm,@(disp12,Rn) nmd12 format xxxx dddd dddddddd 15 0 xxxx mmmm xxxxnnnn 32 16 mmmmdddd: Register indirect with displacement nnnn: Register direct MOV.L @(disp12,Rm),Rn dddddddd: GBR indirect with displacement R0 (Register direct) MOV.L @(disp,GBR),R0 R0 (Register direct) dddddddd: GBR indirect with displacement MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (Register direct) MOVA @(disp,PC),R0 dddddddd: TBR duplicate indirect with displacement — JSR/N @@(disp8,TBR) d format ddddxxxx 15 0 xxxx dddd dddddddd: PC relative — BF label d12 format ddddxxxx 15 0 dddd dddd dddddddddddd: PC relative — BRA label (label = disp + PC) nd8 format ddddnnnnxxxx 15 0 dddd dddddddd: PC relative with displacement nnnn: Register direct MOV.L @(disp,PC),Rn

Rev. 1.00 Jun. 26, 2008 Page 42 of 1692 REJ09B0393-0100 Instruction Formats Source Operand Destination Operand Example iiiiiiii: Immediate Indexed GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Register direct) AND #imm,R0 i format xxxxxxxx iiii 15 0 iiii iiiiiiii: Immediate — TRAPA #imm ni format nnnn iiiixxxx 15 0 iiii iiiiiiii: Immediate nnnn: Register direct ADD #imm,Rn nnnn: Register direct iii: Immediate — BLD #imm3,Rn ni3 format xxxx nnnnxxxx 15 0 iiix — nnnn: Register direct iii: Immediate BST #imm3,Rn ni20 format iiii iiii iiiiiiii 15 0 xxxx iiii xxxxnnnn 32 16 iiiiiiiiiiiiiiiiiiii: Immediate nnnn: Register direct MOVI20 #imm20, Rn nnnndddddddddddd: Register indirect with displacement iii: Immediate — BLD.B #imm3,@(disp12,Rn nid format xxxx dddd dddddddd 15 0 xxxx xiii xxxxnnnn 32 16 — nnnndddddddddddd: Register indirect with displacement iii: Immediate BST.B #imm3,@(disp12,Rn Note: * In multiply-and-accumula te instructions, nnnn is the source register.

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2.4 Instruction Set

2.4.1 Instruction Set by Classification

Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Operation Code Function No. of Instructions MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA Effective address transfer MOVI20 20-bit immediate data transfer MOVI20S 20-bit immediate data transfer 8-bit left-shit MOVML R0 –Rn register save/restore MOVMU Rn –R14 and PR register save/restore MOVRT T bit inversion and transfer to Rn MOVT T bit transfer MOVU Unsigned data transfer NOTT T bit inversion PREF Prefetch to operand cache SWAP Swap of upper and lower bytes Data transfer 13 XTRCT Extraction of the middl e of registers connected

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26 ADD Binary addition 40

ADDC Binary addition with carry ADDV Binary addition with overflow check CMP/cond Comparison CLIPS Signed saturation value comparison CLIPU Unsigned saturation value comparison DIVS Signed division (32 ÷ 32) DIVU Unsigned division (32 ÷ 32) DIV1 One-step division Arithmetic operations DIV0S Initialization of signed one-step division DIV0U Initialization of unsigned one-step division DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double-precision multiply-and-accumulate operation MUL Double-precision multiply operation MULR Signed multiplication with result storage in Rn MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow

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6 AND Logical AND 14

TAS Memory test and bit set TST Logical AND and T bit set Logic operations XOR Exclusive OR Shift 12 ROTL One-bit left rotation 16 ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAD Dynamic arithmetic shift SHAL One-bit arithmetic left shift SHAR One-bit arithmetic right shift SHLD Dynamic logical shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift Branch 10 BF Conditional branch, conditional delayed branch (branch when T = 0) BT Conditional branch, conditional delayed branch (branch when T = 1) BRA Unconditional delayed branch BRAF Unconditional delayed branch BSR Delayed branch to subroutine procedure BSRF Delayed branch to subroutine procedure JMP Unconditional delayed branch JSR Branch to subroutine procedure Delayed branch to subroutine procedure RTS Return from subroutine procedure Delayed return from subroutine procedure RTV/N Return from subroutine procedure with Rm → R0 transfer

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14 CLRT T bit clear 36

LDBANK Register restoration from specified register bank entry LDC Load to control register LDS Load to system register NOP No operation RESBANK Register restoration from register bank RTE Return from exception handling SETT T bit set SLEEP Transition to power-down mode STBANK Register save to specified register bank entry STC Store control register data STS Store system register data TRAPA Trap exception handling

10 BAND Bit AND 14 Bit

manipulation BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit set BST Bit store BXOR Bit exclusive OR BANDNOT Bit NOT AND BORNOT Bit NOT OR BLDNOT Bit NOT load Total: 91 197

Rev. 1.00 Jun. 26, 2008 Page 47 of 1692 REJ09B0393-0100 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Instruction Code Operation Execution States T Bit Indicated by mnemonic. [Legend] Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement * Indicated in MSB ↔ LSB order. [Legend] mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Indicates summary of operation. [Legend] →, ←: Transfer direction (xx): Memory operand M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit ~: Logical NOT of each bit <<n: n-bit left shift >>n: n-bit right shift Value when no wait states are inserted.* Value of T bit after instruction is executed. Explanation of Symbols —: No change Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory → register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details, refer to the SH-2A, SH2A-FPU Software Manual.

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2.4.2 Data Transfer Instructions

Table 2.11 Data Transfer Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A MOV #imm,Rn 1110nnnniiiiiiii imm → sign extension → Rn 1  Yes Yes Yes MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → sign extension → Rn 1  Yes Yes Yes MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1  Yes Yes Yes MOV Rm,Rn 0110nnnnmmmm0011 Rm → Rn 1  Yes Yes Yes MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1  Yes Yes Yes MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1  Yes Yes Yes MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1  Yes Yes Yes MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) → sign extension → Rn 1  Yes Yes Yes MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) → sign extension → Rn 1  Yes Yes Yes MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) → Rn 1  Yes Yes Yes MOV.B Rm,@-Rn 0010nnnnmmmm0100 Rn-1 → Rn, Rm → (Rn) 1  Yes Yes Yes MOV.W Rm,@-Rn 0010nnnnmmmm0101 Rn-2 → Rn, Rm → (Rn) 1  Yes Yes Yes MOV.L Rm,@-Rn 0010nnnnmmmm0110 Rn-4 → Rn, Rm → (Rn) 1  Yes Yes Yes MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) → sign extension → Rn, Rm + 1 → Rm 1  Yes Yes Yes MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → sign extension → Rn, Rm + 2 → Rm 1  Yes Yes Yes MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) → Rn, Rm + 4 → Rm 1  Yes Yes Yes MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 → (disp + Rn) 1  Yes Yes Yes MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 1  Yes Yes Yes MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 1  Yes Yes Yes MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) → sign extension → R0 1  Yes Yes Yes MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → sign extension → R0 1  Yes Yes Yes MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 1  Yes Yes Yes MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) 1  Yes Yes Yes

Rev. 1.00 Jun. 26, 2008 Page 49 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1  Yes Yes Yes MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1  Yes Yes Yes MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → sign extension → Rn 1  Yes Yes Yes MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → sign extension → Rn 1  Yes Yes Yes MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1  Yes Yes Yes MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1  Yes Yes Yes MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1  Yes Yes Yes MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 1  Yes Yes Yes MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → sign extension → R0 1  Yes Yes Yes MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → sign extension → R0 1  Yes Yes Yes MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 1  Yes Yes Yes MOV.B R0,@Rn+ 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn 1  Yes MOV.W R0,@Rn+ 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn 1  Yes MOV.L R0,@Rn+ 0100nnnn10101011 R0 → Rn), Rn + 4 → Rn 1  Yes MOV.B @-Rm,R0 0100mmmm11001011 Rm-1 → Rm, (Rm) → sign extension → R0 1  Yes MOV.W @-Rm,R0 0100mmmm11011011 Rm-2 → Rm, (Rm) → sign extension → R0 1  Yes MOV.L @-Rm,R0 0100mmmm11101011 Rm-4 → Rm, (Rm) → R0 1  Yes MOV.B Rm,@(disp12,Rn) 0011nnnnmmmm0001 0000dddddddddddd Rm → (disp + Rn) 1  Yes MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 0001dddddddddddd Rm → (disp × 2 + Rn) 1  Yes MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 0010dddddddddddd Rm → (disp × 4 + Rn) 1  Yes MOV.B @(disp12,Rm),Rn 0011nnnnmmmm0001 0100dddddddddddd (disp + Rm) → sign extension → Rn 1  Yes

Rev. 1.00 Jun. 26, 2008 Page 50 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 0101dddddddddddd (disp × 2 + Rm) → sign extension → Rn 1  Yes MOV.L @(disp12,Rm),Rn 0011nnnnmmmm0001 0110dddddddddddd (disp × 4 + Rm) → Rn 1  Yes MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0 1  Yes Yes Yes MOVI20 #imm20,Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn 1  Yes MOVI20S #imm20,Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii imm << 8 → sign extension → Rn 1  Yes MOVML.L Rm,@-R15 0100mmmm11110001 R15-4 → R15, Rm → (R15) Note: When Rm = R15, read Rm as PR 1 to 16  Yes MOVML.L @R15+,Rn 0100nnnn11110101 (R15) → R0, R15 + 4 → R15 (R15) → R1, R15 + 4 → R15 (R15) → Rn Note: When Rn = R15, read Rm as PR 1 to 16  Yes MOVMU.L Rm,@-R15 0100mmmm11110000 R15-4 → R15, PR → (R15) R15-4 → R15, R14 → (R15) Note: When Rm = R15, read Rm as PR 1 to 16  Yes MOVMU.L @R15+,Rn 0100nnnn11110100 (R15) → Rn, R15 + 4 → R15 R15 (R15) → R14, R15 + 4 → R15 (R15) → PR Note: When Rn = R15, read Rm as PR 1 to 16  Yes

Rev. 1.00 Jun. 26, 2008 Page 51 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A MOVRT Rn 0000nnnn00111001 ~T → Rn 1  Yes MOVT Rn 0000nnnn00101001 T → Rn 1  Yes Yes Yes MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 1000dddddddddddd (disp + Rm) → zero extension → Rn  Yes MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 1001dddddddddddd (disp × 2 + Rm) → zero extension → Rn  Yes NOTT 0000000001101000 ~T → T 1 Ope- ration result Yes PREF @Rn 0000nnnn10000011 (Rn) → operand cache 1  Yes Yes SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → swap lower 2 bytes → Rn 1  Yes Yes Yes SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → swap upper and lower words → Rn 1  Yes Yes Yes XTRCT Rm,Rn 0010nnnnmmmm1101 Middle 32 bits of Rm:Rn → Rn 1  Yes Yes Yes

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2.4.3 Arithmetic Operation Instructions

Table 2.12 Arithmetic Operation Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1  Yes Yes Yes ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1  Yes Yes Yes ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T → Rn, carry → T 1 Carry Yes Yes Yes ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm → Rn, overflow → T 1 Over- flow Yes Yes Yes CMP/EQ #imm,R0 10001000iiiiiiii When R0 = imm, 1 → T Otherwise, 0 → T

1 Com-

CMP/EQ Rm,Rn 0011nnnnmmmm0000 When Rn = Rm, 1 → T Otherwise, 0 → T CMP/HS Rm,Rn 0011nnnnmmmm0010 When Rn ≥ Rm (unsigned), 1 → T Otherwise, 0 → T CMP/GE Rm,Rn 0011nnnnmmmm0011 When Rn ≥ Rm (signed), 1 → T Otherwise, 0 → T CMP/HI Rm,Rn 0011nnnnmmmm0110 When Rn > Rm (unsigned), 1 → T Otherwise, 0 → T CMP/GT Rm,Rn 0011nnnnmmmm0111 When Rn > Rm (signed), 1 → T Otherwise, 0 → T CMP/PL Rn 0100nnnn00010101 When Rn > 0, 1 → T Otherwise, 0 → T CMP/PZ Rn 0100nnnn00010001 When Rn ≥ 0, 1 → T Otherwise, 0 → T CMP/STR Rm,Rn 0010nnnnmmmm1100 When any bytes are equal, 1 → T Otherwise, 0 → T

Rev. 1.00 Jun. 26, 2008 Page 53 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A CLIPS.B Rn 0100nnnn10010001 When Rn > (H'0000007F), (H'0000007F) → Rn, 1 → CS when Rn < (H'FFFFFF80), (H'FFFFFF80) → Rn, 1 → CS 1  Yes CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), (H'00007FFF) → Rn, 1 → CS When Rn < (H'FFFF8000), (H'FFFF8000) → Rn, 1 → CS 1  Yes CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), (H'000000FF) → Rn, 1 → CS 1  Yes CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), (H'0000FFFF) → Rn, 1 → CS 1  Yes DIV1 Rm,Rn 0011nnnnmmmm0100 1-step division (Rn ÷ Rm) 1 Calcu- lation result Yes Yes Yes DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → M, M ^ Q → T

1 Calcu-

DIV0U 0000000000011001 0 → M/Q/T 1 0 Yes Yes Yes DIVS R0,Rn 0100nnnn10010100 Signed operation of Rn ÷ R0 → Rn 32 ÷ 32 → 32 bits 36  Yes DIVU R0,Rn 0100nnnn10000100 Unsigned operation of Rn ÷ R0 → Rn 32 ÷ 32 → 32 bits 34  Yes DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits  Yes Yes Yes DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits  Yes Yes Yes DT Rn 0100nnnn00010000 Rn – 1 → Rn When Rn is 0, 1 → T When Rn is not 0, 0 → T

1 Compa-

EXTS.B Rm,Rn 0110nnnnmmmm1110 Byte in Rm is sign-extended → Rn 1  Yes Yes Yes EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended → Rn 1  Yes Yes Yes

Rev. 1.00 Jun. 26, 2008 Page 54 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A EXTU.B Rm,Rn 0110nnnnmmmm1100 Byte in Rm is zero-extended → Rn 1  Yes Yes Yes EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended → Rn 1  Yes Yes Yes MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits 4  Yes Yes Yes MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits  Yes Yes Yes MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL 32 × 32 → 32 bits 2  Yes Yes Yes MULR R0,Rn 0100nnnn10000000 R0 × Rn → Rn 32 × 32 → 32 bits

2 Yes

MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn × Rm → MACL 16 × 16 → 32 bits 1  Yes Yes Yes MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn × Rm → MACL 16 × 16 → 32 bits  Yes Yes Yes NEG Rm,Rn 0110nnnnmmmm1011 0-Rm → Rn 1  Yes Yes Yes NEGC Rm,Rn 0110nnnnmmmm1010 0-Rm-T → Rn, borrow → T 1 Borrow Yes Yes Yes SUB Rm,Rn 0011nnnnmmmm1000 Rn-Rm → Rn 1  Yes Yes Yes SUBC Rm,Rn 0011nnnnmmmm1010 Rn-Rm-T → Rn, borrow → T 1 Borrow Yes Yes Yes SUBV Rm,Rn 0011nnnnmmmm1011 Rn-Rm → Rn, underflow → T 1 Under- flow Yes Yes Yes

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2.4.4 Logic Operation Instructions

Table 2.13 Logic Operation Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1  Yes Yes Yes AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1  Yes Yes Yes AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → (R0 + GBR) 3  Yes Yes Yes NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1  Yes Yes Yes OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1  Yes Yes Yes OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1  Yes Yes Yes OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → (R0 + GBR) 3  Yes Yes Yes TAS.B @Rn 0100nnnn00011011 When (Rn) is 0, 1 → T Otherwise, 0 → T, 1 → MSB of(Rn)

3 Test

TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm When the result is 0, 1 → T Otherwise, 0 → T

1 Test

TST #imm,R0 11001000iiiiiiii R0 & imm When the result is 0, 1 → T Otherwise, 0 → T TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm When the result is 0, 1 → T Otherwise, 0 → T XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1  Yes Yes Yes XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1  Yes Yes Yes XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → (R0 + GBR) 3  Yes Yes Yes

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2.4.5 Shift Instructions

Table 2.14 Shift Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB Yes Yes Yes ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB Yes Yes Yes ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB Yes Yes Yes ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB Yes Yes Yes SHAD Rm,Rn 0100nnnnmmmm1100 When Rm ≥ 0, Rn << Rm → Rn [MSB → Rn] 1  Yes Yes SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB Yes Yes Yes SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB Yes Yes Yes SHLD Rm,Rn 0100nnnnmmmm1101 When Rm ≥ 0, Rn << Rm → Rn [0 → Rn] 1  Yes Yes SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB Yes Yes Yes SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB Yes Yes Yes SHLL2 Rn 0100nnnn00001000 Rn << 2 → Rn 1  Yes Yes Yes SHLR2 Rn 0100nnnn00001001 Rn >> 2 → Rn 1  Yes Yes Yes SHLL8 Rn 0100nnnn00011000 Rn << 8 → Rn 1  Yes Yes Yes SHLR8 Rn 0100nnnn00011001 Rn >> 8 → Rn 1  Yes Yes Yes SHLL16 Rn 0100nnnn00101000 Rn << 16 → Rn 1  Yes Yes Yes SHLR16 Rn 0100nnnn00101001 Rn >> 16 → Rn 1  Yes Yes Yes

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2.4.6 Branch Instructions

Table 2.15 Branch Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A BF label 10001011dddddddd When T = 0, disp × 2 + PC → PC, When T = 1, nop 3/1*  Yes Yes Yes BF/S label 10001111dddddddd Delayed branch When T = 0, disp × 2 + PC → PC, When T = 1, nop 2/1*  Yes Yes Yes BT label 10001001dddddddd When T = 1, disp × 2 + PC → PC, When T = 0, nop 3/1*  Yes Yes Yes BT/S label 10001101dddddddd Delayed branch When T = 1, disp × 2 + PC → PC, When T = 0, nop 2/1*  Yes Yes Yes BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 2  Yes Yes Yes BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC 2  Yes Yes Yes BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 2  Yes Yes Yes BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 2  Yes Yes Yes JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2  Yes Yes Yes JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 2  Yes Yes Yes JSR/N @Rm 0100mmmm01001011 PC-2 → PR, Rm → PC 3  Yes JSR/N @@(disp8,TBR) 10000011dddddddd PC-2 → PR, (disp × 4 + TBR) → PC 5  Yes RTS 0000000000001011 Delayed branch, PR → PC 2  Yes Yes Yes RTS/N 0000000001101011 PR → PC 3  Yes RTV/N Rm 0000mmmm01111011 Rm → R0, PR → PC 3  Yes Note: * One cycle when the program does not branch.

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2.4.7 System Control Instructions

Table 2.16 System Control Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A CLRT 0000000000001000 0 → T 1 0 Yes Yes Yes CLRMAC 0000000000101000 0 → MACH,MACL 1  Yes Yes Yes LDBANK @Rm,R0 0100mmmm11100101 (Specified register bank entry) → R0 6  Yes LDC Rm,SR 0100mmmm00001110 Rm → SR 3 LSB Yes Yes Yes LDC Rm,TBR 0100mmmm01001010 Rm → TBR 1  Yes LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1  Yes Yes Yes LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1  Yes Yes Yes LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 5 LSB Yes Yes Yes LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 1  Yes Yes Yes LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 1  Yes Yes Yes LDS Rm,MACH 0100mmmm00001010 Rm → MACH 1  Yes Yes Yes LDS Rm,MACL 0100mmmm00011010 Rm → MACL 1  Yes Yes Yes LDS Rm,PR 0100mmmm00101010 Rm → PR 1  Yes Yes Yes LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm 1  Yes Yes Yes LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm 1  Yes Yes Yes LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1  Yes Yes Yes NOP 0000000000001001 No operation 1  Yes Yes Yes RESBANK 0000000001011011 Bank → R0 to R14, GBR, MACH, MACL, PR 9*  Yes RTE 0000000000101011 Delayed branch, stack area → PC/SR 6  Yes Yes Yes SETT 0000000000011000 1 → T 1 1 Yes Yes Yes SLEEP 0000000000011011 Sleep 5  Yes Yes Yes STBANK R0,@Rn 0100nnnn11100001 R0 → (specified register bank entry) 7  Yes STC SR,Rn 0000nnnn00000010 SR → Rn 2  Yes Yes Yes STC TBR,Rn 0000nnnn01001010 TBR → Rn 1  Yes

Rev. 1.00 Jun. 26, 2008 Page 59 of 1692 REJ09B0393-0100 Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A STC GBR,Rn 0000nnnn00010010 GBR → Rn 1  Yes Yes Yes STC VBR,Rn 0000nnnn00100010 VBR → Rn 1  Yes Yes Yes STC.L SR,@-Rn 0100nnnn00000011 Rn-4 → Rn, SR → (Rn) 2  Yes Yes Yes STC.L GBR,@-Rn 0100nnnn00010011 Rn-4 → Rn, GBR → (Rn) 1  Yes Yes Yes STC.L VBR,@-Rn 0100nnnn00100011 Rn-4 → Rn, VBR → (Rn) 1  Yes Yes Yes STS MACH,Rn 0000nnnn00001010 MACH → Rn 1  Yes Yes Yes STS MACL,Rn 0000nnnn00011010 MACL → Rn 1  Yes Yes Yes STS PR,Rn 0000nnnn00101010 PR → Rn 1  Yes Yes Yes STS.L MACH,@-Rn 0100nnnn00000010 Rn-4 → Rn, MACH → (Rn) 1  Yes Yes Yes STS.L MACL,@-Rn 0100nnnn00010010 Rn-4 → Rn, MACL → (Rn) 1  Yes Yes Yes STS.L PR,@-Rn 0100nnnn00100010 Rn-4 → Rn, PR → (Rn) 1  Yes Yes Yes TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm × 4 + VBR) → PC 5  Yes Yes Yes Notes: Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory → register) is the same as the register used by the next instruction. * In the event of bank overflow , the number of cycles is 19.

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2.4.8 Bit Manipulation Instructions

Table 2.17 Bit Manipulation Instructions Compatibility Instruction Instruct ion Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH- BAND.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0100dddddddddddd (imm of (disp + Rn)) & T → 3 Ope- ration result Yes BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1100dddddddddddd ~(imm of (disp + Rn)) & T → T 3 Ope- ration result Yes BCLR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0000dddddddddddd 0 → (imm of (disp + Rn)) 3  Yes BCLR #imm3,Rn 10000110nnnn0iii 0 → imm of Rn 1  Yes BLD.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0011dddddddddddd (imm of (disp + Rn)) → 3 Ope- ration result Yes BLD #imm3,Rn 10000111nnnn1iii imm of Rn → T 1 Ope- ration result Yes BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1011dddddddddddd ~(imm of (disp + Rn)) → T

3 Ope-

BOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0101dddddddddddd ( imm of (disp + Rn)) | T → T 3 Ope- ration result Yes BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1101dddddddddddd ~( imm of (disp + Rn)) | T → T 3 Ope- ration result Yes BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0001dddddddddddd 1 → ( imm of (disp + Rn)) 3  Yes BSET #imm3,Rn 10000110nnnn1iii 1 → imm of Rn 1  Yes BST.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0010dddddddddddd T → (imm of (disp + Rn)) 3  Yes BST #imm3,Rn 10000111nnnn0iii T → imm of Rn 1  Yes BXOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0110dddddddddddd (imm of (disp + Rn)) ^ T → T 3 Ope- ration result Yes

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2.5 Processing States

The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Power-on reset from any state Manual reset from any state except software standby mode Power-on reset state Manual reset state Program execution state Bus-released state Sleep mode Software standby mode Exception handling state Exception handling source occurs Exception handling ends Bus request generated Bus request cleared STBY bit set for SLEEP instruction Power-down state Reset canceled STBY bit cleared for SLEEP instruction Reset state Bus request cleared Bus request cleared Bus request generated Bus request generated Interrupt source or DMA address error occurs Figure 2.6 Transitions between Processing States

Rev. 1.00 Jun. 26, 2008 Page 62 of 1692 REJ09B0393-0100 (1) Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU’s processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State In the program execution state, the CPU sequentially executes the program. (4) Power-Down State In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. (5) Bus-Released State In the bus-released state, the CPU releases bus to a device that has requested it.

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 63 of 1692 REJ09B0393-0100 Section 3 MCU Operating Modes

3.1 Selection of Operating Modes

This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings; do not set these pins in the other way than the shown combinations. When power is applied to the system, be sure to conduct power-on reset. The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user program mode which are on-chip programming modes are available. Table 3.1 Selection of Operating Modes Pin Setting Bus Width of CS0 Space Mode No. FWE MD1 MD0 Mode Name On-Chip ROM SH7286 SH7285 SH7284 Mode 0 0 0 0 MCU extension mode 0 Not active 32 16 16 Mode 1 0 0 1 MCU extension mode 1 Not active 16 8 8 Mode 2 0 1 0 MCU extension mode 2 Active Set by CS0BCR in BSC Mode 3 0 1 1 Single chip mode Active  Mode 4 1 0 0 Boot mode Active Set by CS0BCR in BSC Mode 5 1 0 1 User boot mode Active Set by CS0BCR in BSC Mode 6 1 1 0 User programming mode Active Set by CS0BCR in BSC Mode 7 *1*2 1 1 1 USB boot mode Active — Mode 7 *1*4 1 1 1 User Programming mode Active — Notes: 1. Flash memory programming mode. 2. Setting mode is prohibited in the SH7243. 3. When always FWE = 1, after the power has been on. 4. If FWE = 0 when power-on reset has been released, and if FWE = 1 when the MCU operation has been set, transition to the user programming mode is executed in a single chip state.

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 64 of 1692 REJ09B0393-0100

3.2 Input/Output Pins

Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output Function MD0 Input Designates operating mode through the level applied to this pin MD1 Input Designates operating mode through the level applied to this pin FWE Input Enables, by hardware, prog ramming/erasing of the on-chip flash memory

3.3 Operating Modes

3.3.1 Mode 0 (MCU Extension Mode 0)

In this mode, CS0 space becomes external memory spaces with 32-bit bus width (SH7286) or 16- bit bus width (SH7285 and SH7243).

3.3.2 Mode 1 (MCU Extension Mode 1)

In this mode, CS0 space becomes external memory spaces with 16-bit bus width (SH7286) 8-bit bus width (SH7285 and SH7243).

3.3.3 Mode 2 (MCU Extension Mode 2)

The on-chip ROM is active and CS0 space can be used in this mode.

3.3.4 Mode 3 (Single Chip Mode)

All ports can be used in this mode, however the external address cannot be used.

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 65 of 1692 REJ09B0393-0100

3.4 Address Map

The address map for the operating modes is shown in figure 3.1 to 3.7. On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space On-chip ROM (1024 Kbytes)On-chip ROM (1024 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'000F FFFF H'07FF FFFF H'0400 0000 H'0010 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'000F FFFF H'0010 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Reserved areaReserved area H'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (32 Kbytes) On-chip peripheral I/O registers Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode Figure 3.1 SH7286F (1 MB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 66 of 1692 REJ09B0393-0100 On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (768 Kbytes)On-chip ROM (768 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'000B FFFF H'07FF FFFF H'0400 0000 H'000C 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'000B FFFF H'000C 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Reserved area Reserved area H'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (32 Kbytes) On-chip peripheral I/O registers Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.2 SH7286F (768 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 67 of 1692 REJ09B0393-0100 On-chip RAM (24 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (24 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (512 Kbytes)On-chip ROM (512 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'0007 FFFF H'07FF FFFF H'0400 0000 H'0008 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'0007 FFFF H'0008 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Reserved area Reserved area H'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 5FFF H'FFF8 6000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (24 Kbytes) On-chip peripheral I/O registers Reserved area H'FFF8 5FFF H'FFF8 6000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.3 SH7286F (512 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 68 of 1692 REJ09B0393-0100 On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (32 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (768 Kbytes)On-chip ROM (768 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'000B FFFF H'07FF FFFF H'0400 0000 H'000C 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'000B FFFF H'000C 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Reserved area Reserved area Reserved areaH'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (32 Kbytes) On-chip peripheral I/O registers H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.4 SH7285F (768 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 69 of 1692 REJ09B0393-0100 On-chip RAM (24 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (24 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (512 Kbytes)On-chip ROM (512 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'0007 FFFF H'07FF FFFF H'0400 0000 H'0008 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'0007 FFFF H'0008 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 7FFF H'FFF8 8000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Reserved area Reserved area Reserved areaH'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 5FFF H'FFF8 6000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (24 Kbytes) On-chip peripheral I/O registers H'FFF8 5FFF H'FFF8 6000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.5 SH7285F (512 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 70 of 1692 REJ09B0393-0100 On-chip RAM (12 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (12 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (256 Kbytes)On-chip ROM (256 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'0003 FFFF H'07FF FFFF H'0400 0000 H'0004 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'0003 FFFF H'0004 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 2FFF H'FFF8 3000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF H'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 2FFF H'FFF8 3000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (12 Kbytes) On-chip peripheral I/O registers Reserved areaReserved area Reserved area H'FFF8 2FFF H'FFF8 3000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.6 SH7243F (256 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 71 of 1692 REJ09B0393-0100 On-chip RAM (8 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (8 Kbytes) On-chip peripheral I/O registers SDRAM mode setting space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space CS0 space CS1 space CS2 space CS3 space CS4 space CS5 space CS6 space CS7 space Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip ROM (128 Kbytes)On-chip ROM (128 Kbytes)H'0000 0000 H'0200 0000 H'01FF FFFF H'03FF FFFF H'0001 FFFF H'07FF FFFF H'0400 0000 H'0002 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'2000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H1FFF FFFF Reserved area Reserved area Reserved area H'0000 0000 H'0001 FFFF H'0002 0000 Reserved area H'FFFC FFFF Reserved area H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'0000 0000 H'03FF FFFF H'07FF FFFF H'0400 0000 H'0800 0000 H'0BFF FFFF H'0C00 0000 H'0FFF FFFF H'1000 0000 H'13FF FFFF H'1400 0000 H'17FF FFFF H'1800 0000 H'1BFF FFFF H'1C00 0000 H'1FFF FFFF H'2000 0000 Reserved area H'FFF8 2FFF H'FFF8 3000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF H'FFFC FFFF H'FFFD 0000 H'FFFB FFFF H'FFFC 0000 H'FFF8 1FFF H'FFF8 2000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF On-chip RAM (8 Kbytes) On-chip peripheral I/O registers Reserved areaReserved area Reserved area H'FFF8 1FFF H'FFF8 2000 H'FFF7 FFFF H'FFF8 0000 H'FFFD FFFF H'FFFE 0000 H'FFFF FFFF Figure 3.7 SH7243F (128 KB) Address Map for Each Operating Mode

Section 3 MCU Operating Modes Rev. 1.00 Jun. 26, 2008 Page 72 of 1692 REJ09B0393-0100

3.5 Initial State in This LSI

In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 28, Power-Down Modes.

3.6 Note on Changing Operating Mode

When changing operating mode while power is applied to this LSI, make sure to do it in the power-on reset state (that is, the low level is applied to the RES pin). Note: * See section 31.3.2, Control Signal Timing. tMDS* CK MD1, MD0 RES Figure 3.8 Reset Input Timing when Changing Operating Mode

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 73 of 1692 REJ09B0393-0100 Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists of a crystal oscillator, a PLL circuit, and a divider circuit.

4.1 Features

• Five clocks generated independently An internal clock (Iφ) for the CPU and cache, a peripheral clock (Pφ) for the peripheral modules, a bus clock (Bφ = CK) for the external bus interface, an MTU2S clock (Mφ) for the MTU2S module, and an AD clock (Aφ) for the ADC module can be generated independently.
• Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings.
• Power-down mode control The clock can be stopped for sleep mode and software standby mode, and specific modules can be stopped using the module standby function. For details on clock control in the power- down modes, see section 28, Power-Down Modes. Figure 4.1 shows a block diagram of the clock pulse generator.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 74 of 1692 REJ09B0393-0100 FRQCR: MCLKCR: ACLKCR: STBCR: STBCR2: [Legend] Frequency control register MTU2S clock frequency control register AD clock frequency control register Standby control register Standby control register 2 STBCR3: STBCR4: STBCR5: STBCR6: OSCCR: Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Oscillation stop detection control register FRQCR MCLKCR ACLKCR Bus interface CK CPG control unit Clock frequency control circuit Standby control circuit EXTAL XTAL PLL circuit (×8) Divider MTU2S clock (Mφ, Max. 100 MHz) AD clock (Aφ, Max. 50 MHz) Internal clock (Iφ, Max. 100 MHz) Peripheral clock (Pφ, Max. 50 MHz) Bus clock (Bφ = CK, Max. 50 MHz) OSCCR Crystal oscillator Oscillation stop detection circuit Oscillation stop detection On-chip oscillator HPB bus STBCR STBCR6STBCR2 STBCR3 STBCR4 STBCR5 ×1/2 ×1/4 ×1/8 OscillatorUSBXTAL* USBEXTAL* USB clock* (Uφ :48MHz) Note: * Not applied to the SH7243 Figure 4.1 Block Diagram of Clock Pulse Generator

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 75 of 1692 REJ09B0393-0100 The clock pulse generator blocks function as follows: (1) PLL Circuit The PLL circuit multiplies the input clock frequency from the crystal oscillator or EXTAL pin by (2) Crystal Oscillator The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating mode. (3) Divider The divider generates a clock signal at the operating frequency used by the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (Mφ), or AD clock (Aφ). The operating frequency can be 1, 1/2, 1/4, or 1/8 times the output frequency of the PLL circuit. The division ratio is set in the frequency control register (FRQCR). USB clock (Uφ) is set as fixed 1/2 and when generating USB clock with a divider, set the crystal resonator to 12 MHz. (4) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the frequency control register (FRQCR). (5) Standby Control Circuit The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or sleep or software standby mode. (6) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CK pin during software standby mode, and the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), and peripheral clock (Pφ). (7) MTU2S Clock Frequency Control Register (MCLKCR) The MTU2S clock frequency control register (MCLKCR) has control bits assigned for the following functions: MTU2S clock (Mφ) output/non-output and the frequency division ratio.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 76 of 1692 REJ09B0393-0100 (8) AD Clock Frequency Control Register (ACLKCR) The AD clock frequency control register (ACLKCR) has control bits assigned for the following functions: AD clock (Aφ) output/non-output and the frequency division ratio. (9) Standby Control Register The standby control register has bits for controlling the power-down modes and for selecting the USB clock. See section 28, Power-Down Modes, for more information. (10) Oscillation Stop Detection Control Register (OSCCR) The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output through an external pin. (11) USB-only oscillator (SH7285, SH7286) The oscillator for USB clock only that is connected to the resonator of 48 MHz.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 77 of 1692 REJ09B0393-0100

4.2 Input/Output Pins

Table 4.1 lists the clock pulse generator pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol I/O Function XTAL Output Connected to the crystal re sonator. (Leave this pin open when the crystal resonator is not in use.) Crystal input/output pins (clock input pins) EXTAL Input Connected to the crystal re sonator or used to input an external clock. Clock output pin CK Output Clock output pin. This pin can be placed in high-impedance state. USBXTAL Output Connected to the crystal resonator for USB (equivalent for CSTCZ48M0X11R). Leave this pin open when the crystal resonator is not in use. Crystal input/output pins for USB (clock input pins) USBEXTAL Input Connected to the crystal resonator for USB (equivalent for CSTCZ48M0X11R). Connect this pin to Vss when the crystal resonator is not in use. To use the clock output (CK) pin, appropriate settings may be needed in the pin function controller (PFC) in some cases. For details, refer to section 23, Pin Function Controller (PFC).

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 78 of 1692 REJ09B0393-0100

4.3 Clock Operating Modes

Table 4.2 shows the clock operating modes of this LSI. Table 4.2 Clock Operating Modes Clock I/O Mode Source Output PLL Circuit Input to Divider

1 EXTAL input or

CK* On ( × 8) × 8 Note: * To output the clock through the CK pin, appropriate settings should be made in the PFC. For details, refer to section 23, Pin Function Controller (PFC). The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before it is supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10 MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 100 MHz. Maximum operating frequencies: Iφ = 100 MHz, Bφ = 50 MHz, Pφ = 50 MHz, Mφ = 100 MHz, Aφ = 50 MHz Table 4.3 shows the frequency division ratios that can be specified with FRQCR.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 79 of 1692 REJ09B0393-0100 Table 4.3 Relationship between Clock Operating Mode and Frequency Range FRQCR/MCLKCR/ACLKCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio Iφ B φ P φ M φ A φ I φ B φ P φ M φ A φ Input Clock I φ B φ P φ M φ A φ 1/4 1/4 1/8 1/4 1/4 2 2 1 2 2 20 20 10 20 20 1/4 1/4 1/4 1/4 1/4 2 2 2 2 2 20 20 20 20 20 1/2 1/4 1/8 1/4 1/4 4 2 1 2 2 40 20 10 20 20 1/2 1/4 1/8 1/2 1/4 4 2 1 4 2 40 20 10 40 20 1/2 1/4 1/4 1/4 1/4 4 2 2 2 2 40 20 20 20 20 1/2 1/4 1/4 1/2 1/4 4 2 2 4 2 40 20 20 40 20 1/2 1/2 1/8 1/4 1/4 4 4 1 2 2 40 40 10 20 20 1/2 1/2 1/8 1/2 1/8 4 4 1 4 2 40 40 10 40 20 1/2 1/2 1/8 1/2 1/2 4 4 1 4 4 40 40 10 40 40 1/2 1/2 1/4 1/4 1/4 4 4 2 2 2 40 40 20 20 20 1/2 1/2 1/4 1/2 1/4 4 4 2 4 2 40 40 20 40 20 1/2 1/2 1/4 1/2 1/2 4 4 2 4 4 40 40 20 40 40 1/2 1/2 1/2 1/2 1/2 4 4 4 4 4 40 40 40 40 40 1/1 1/4 1/8 1/4 1/4 8 2 1 2 2 80 20 10 20 20 1/1 1/4 1/8 1/2 1/4 8 2 1 4 2 80 20 10 40 20 1/1 1/4 1/8 1/1 1/4 8 2 1 8 2 80 20 10 80 20 1/1 1/4 1/4 1/4 1/4 8 2 2 2 2 80 20 20 20 20 1/1 1/4 1/4 1/2 1/4 8 2 2 4 2 80 20 20 40 20 1/1 1/4 1/4 1/1 1/4 8 2 2 8 2 80 20 20 80 20 1/1 1/2 1/8 1/4 1/4 8 4 1 2 2 80 40 10 20 20 1/1 1/2 1/8 1/2 1/4 8 4 1 4 2 80 40 10 40 20 1/1 1/2 1/8 1/2 1/2 8 4 1 4 4 80 40 10 40 40 1/1 1/2 1/8 1/1 1/4 8 4 1 8 2 80 40 10 80 20 1/1 1/2 1/8 1/1 1/2 8 4 1 8 4 80 40 10 80 40 1/1 1/2 1/4 1/4 1/4 8 4 2 2 2 80 40 20 20 20 1/1 1/2 1/4 1/2 1/4 8 4 2 4 2 80 40 20 40 20 1/1 1/2 1/4 1/2 1/2 8 4 2 4 4 80 40 20 40 40 1/1 1/2 1/4 1/1 1/4 8 4 2 8 2 80 40 20 80 20 1/1 1/2 1/4 1/1 1/2 8 4 2 8 4 80 40 20 80 40 1/1 1/2 1/2 1/2 1/2 8 4 4 4 4 80 40 40 40 40 1/1 1/2 1/2 1/1 1/2 8 4 4 8 4 80 40 40 80 40

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 80 of 1692 REJ09B0393-0100 FRQCR/MCLKCR/ACLKCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio Iφ B φ P φ M φ A φ I φ B φ P φ M φ A φ Input Clock I φ B φ P φ M φ A φ 1/1 1/2 1/4 1/4 1/4 8 4 2 2 2 100 50 25 25 25 1/1 1/2 1/4 1/2 1/4 8 4 2 4 2 100 50 25 50 25 1/1 1/2 1/4 1/2 1/2 8 4 2 4 4 100 50 25 50 50 1/1 1/2 1/4 1/1 1/4 8 4 2 8 2 100 50 25 100 25 1/1 1/2 1/4 1/1 1/2 8 4 2 8 4 100 50 25 100 50 1/1 1/2 1/2 1/2 1/2 8 4 4 4 4 100 50 50 50 50 1/1 1/2 1/2 1/1 1/2 8 4 4 8 4 12.5 100 50 50 100 50 Notes: * Clock frequencies when the input clock fre quency is assumed to be the shown value. 1. The PLL multiplication ratio is fixed at ×8. T he division ratio can be selected from ×1, ×1/2, ×1/4, and ×1/8 for each clock by the setting in the frequency control register. 2. The output frequency of the PLL circuit is obtaine d by multiplication of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. This output frequency must be 100 MHz or lower. 3. The input to the divider is al ways the output from the PLL circuit. 4. The internal clock (I φ) frequency is obtained by multiplication of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency of the internal clock (Iφ) must not exceed 100 MHz (maximum operating frequency) or lower. 5. The bus clock (B φ) frequency is obtained by multiplication of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency of the bus clock (Bφ) must not exceed 50 MHz or the internal clock (Iφ) frequency. 6. The peripheral clock (P φ) frequency is obtained by multiplication of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency of the peripheral clock (Pφ) must not exceed 50 MHz or the bus clock (Bφ) frequency. 7. When using the MTU2S, the MTU2S clock (M φ) frequency must not exceed the internal clock (Iφ) frequency. The MTU2S clock (Mφ) frequency is obtained by multiplication of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. 8. The frequency of the CK pin output is always equal to the bus clock (B φ) frequency. 9. When using the AD, the AD clock (A φ) frequency must be equal to or higher than the peripheral clock (Pφ) frequency. 10. When using the USB, the peripheral clock (P φ) frequency must be 13 MHz or higher. 11. U φ must be fixed to 48 MHz. When generating Uφ from the divider, input the clock 12 MHz or connect the crystal resonator of 12MHz to the EXTAL or XTAL.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 81 of 1692 REJ09B0393-0100

4.4 Register Descriptions

The clock pulse generator has the following registers. Table 4.4 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Frequency control register FRQCR R/W H'0333 H'FFFE0010 16 MTU2S clock frequency control register MCLKCR R/W H'43 H'FFFE0410 8 AD clock frequency control register ACLKCR R/W H'43 H'FFFE0414 8 Oscillation stop detection control register OSCCR R/W H'00 H'FFFE001C 8

4.4.1 Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CK pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock (Iφ) and peripheral clock (Pφ). FRQCR can be accessed only in word units. After executing an instruction for modifying the FRQCR, be sure to execute 32 NOP instructions. Especially when writing/erasing to the flush memory, execute the NOP operation for 32Pφ clock after having confirmed the set value by reading the FRQCR. FRQCR is initialized to H'0333 only by a power-on reset. FRQCR retains its previous value by a manual reset or in software standby mode. The previous value is also retained when an internal reset is triggered by an overflow of the WDT. When switching the division ratio of bus clock frequency, the CK pin is fixed at low level for a cycle of an input clock so as to prevent a hazard of switching. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 000 00110011 011 RRR R R R/W R/W R/W R RR/W R/W R/W R/W R/W R/W --- - -- - IFC[2:0]STC[2:0] PFC[2:0]

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 82 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 STC[2:0] 011 R/W Bus Clock (B φ) Frequency Division Ratio These bits specify the frequency division ratio of the bus clock. 000: × 1 001: × 1/2 010: Setting prohibited 011: × 1/4 100: Setting prohibited 101: × 1/8 Others: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 IFC[2:0] 011 R/W Internal Clock (I φ) Frequency Division Ratio These bits specify the frequency division ratio of the internal clock. 000: × 1 001: × 1/2 010: Setting prohibited 011: × 1/4 100: Setting prohibited 101: × 1/8 Others: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 83 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 2 to 0 PFC[2:0] 011 R/W Peripheral Clock (P φ) Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock. 000: × 1 001: × 1/2 010: Setting prohibited 011: × 1/4 100: Setting prohibited 101: × 1/8 Others: Setting prohibited

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4.4.2 MTU2S Clock Frequency Control Register (MCLKCR)

MCLKCR is an 8-bit readable/writable register. MCLKCR can be accessed only in byte units. MCLKCR is initialized to H'43 only by a power-on reset. MCLKCR retains its previous value by a manual reset or in software standby mode. 7654321 0 01000011 R/W R/W R R R R R/W R/W Bit: Initial value: R/W: MSSCS[1:0] MSDIVS[1:0]---- Bit Bit Name Initial Value R/W Description 7, 6 MSSCS[1:0] 01 R/W Source Clock Select These bits select the source clock. 00: Clock stop 01: PLL output clock 10: Reserved (setting prohibited) 11: Reserved (setting prohibited) 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 MSDIVS[1:0] 11 R/W Division Ratio Select These bits specify the frequency division ratio of the source clock. Set these bits so that the output clock is

100 MHz or less, and also an integer multiple of the

peripheral clock frequency (Pφ). 00: × 1 01: × 1/2 10: Setting prohibited 11: × 1/4

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 85 of 1692 REJ09B0393-0100

4.4.3 AD Clock Frequency Control Register (ACLKCR)

ACLKCR is an 8-bit readable/writable register that can be accessed only in byte units. ACLKCR is initialized to H'43 only by a power-on reset, but retains its previous value by a manual reset or in software standby mode. 7654321 0 01000011 R/W R/W R R R R R/W R/W Bit: Initial value: R/W: ASSCS[1:0] ASDIVS[1:0]---- Bit Bit Name Initial Value R/W Description 7, 6 ASSCS[1:0] 01 R/W Source Clock Select These bits select the source clock. 00: Clock stoppage 01: PLL output clock 10: Reserved (setting prohibited) 11: Reserved (setting prohibited) 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 ASDIVS[1:0] 11 R/W Division Ratio Select These bits specify the frequency division ratio of the source clock. Set these bits so that the output clock is

50 MHz or less, and also an integer multiple of the

peripheral clock frequency (Pφ). 00: × 1 01: × 1/2 10: Setting prohibited 11: × 1/4

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4.4.4 Oscillation Stop Detection Control Register (OSCCR)

OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in byte units. 76543210Bit: Initial value: R/W: 0000 0 RR R RR RR R / W OSC ERS OSC STOP-- --- - Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 OSCSTOP 0 R/W Oscillation Stop Detection Flag

[Setting condition]

• When a stop in the clock input is detected during normal operation [Clearing condition]
• By a power-on reset input through the RES pin 1  0 R Reserved This bit is always read as 0. The write value should always be 0.

0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select

Selects whether to output the oscillation stop detection flag signal through the WDTOVF pin. 0: Outputs only the WDT overflow signal through the WDTOVF pin 1: Outputs the WDT overflow signal and oscillation stop detection flag signal through the WDTOVF pin

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4.5 Changing the Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock, bus clock, peripheral clock, and MTU2 clock under the software control through the frequency control register (FRQCR). The following describes how to specify the frequencies. 1. In the initial state, IFC2 to IFC0 = B'011 ( ×1/4), STC2 to STC0 = B'011 (×1/4), PFC2 to PFC0 = B'011 (×1/4), MSDIVS1 and MSDIVS0 = 11 (×1/4), and ASDIVS1 and ASDIVS 0 = 11 (×1/4). 2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM. 3. Set the desired values in bits IFC2 to IFC0, STC2 to STC0, PFC2 to PFC0, MSDIVS1, MSDIVS0, ASDIVS1, and ASDIVS 0. When specifying the frequencies, satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) ≥ peripheral clock (Pφ). When using the MTU2S clock, specify the frequencies to satisfy the following condition: internal clock (Iφ) ≥ MTU2S clock (MIφ) ≥ peripheral clock (Pφ). 4. The clock frequencies are immediately changed to the specified values after FRQCR setting is completed.

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4.6 Oscillator

The source of click supply can be selected from a connected crystal resonator or an external clock input through a pin.

4.6.1 Connecting Crystal Resonator

A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) shown in table 4.5. Use a crystal resonator that has a resonance frequency of 10 to 12.5 MHz. It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI. EXTAL XTAL CL1 = CL2 = 18 to 22 pF (reference value) CL1 CL2Rd Figure 4.2 Example of Crystal Resonator Connection Table 4.5 Damping Resistance Values (Reference Values) Frequency (MHz) 10 12.5 Rd (Ω) (reference value) 0 0 Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics shown in table 4.6. EXTALXTAL L CL RS Figure 4.3 Crystal Resonator Equivalent Circuit

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 89 of 1692 REJ09B0393-0100 Table 4.6 Crystal Resonator Characteristics Frequency (MHz) 10 12.5 Rs max. (Ω) (reference value) 60 50 C0 max. (pF) (reference value) 7 7

4.6.2 External Clock Input Method

Figure 4.4 shows an example of an external clock input connection. Drive the external clock high when it is stopped in software standby mode. During operation, input an external clock with a frequency of 10 to 12.5 MHz. Make sure the parasitic capacitance of the XTAL pin is 10 pF or less. Even when inputting an external clock, be sure to wait at least for the oscillation settling time in power-on sequence or in canceling software standby mode, in order to ensure the PLL settling time. EXTAL XTAL External clock input Open state Figure 4.4 Example of External Clock Connection

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 90 of 1692 REJ09B0393-0100

4.7 Oscillation Stop Detection

The CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin is canceled. If the OSCERS bit is 1 at this time, an oscillation stop detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (multiplexed pins to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2, the TIOC3BS, TIOC3DS, and TIOC4AS to TIOC4DS in the MTU2S are assigned) can be placed in high-impedance state regardless of the PFC setting. For details, refer to appendix A, Pin States. Even in software standby mode, these pins are placed in high-impedance state. For details, refer to appendix A, Pin States. Under an abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI operations other than the oscillation stop detection function become unpredictable. In this case, even after oscillation is restarted, LSI operations including the above high-current pins become unpredictable. Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and operating voltage).

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4.8 USB Operating Clock (48 MHz)

Connection of a ceramic resonator for USB, input of an external 48-MHz clock signal, and selection of the internal CPG are available as methods for supplying the USB operating clock.

4.8.1 Connecting a Ceramic Resonator

Figure 4.5 shows an example of the connections for a ceramic resonator. Rd Rf Ceramic resonator USBEXTAL USBXTAL Ceramic resonator: CSTCZ48M0X11R*-RD (Murata Manufacturing Co., Ltd.) Contact your Renesas Technology sales agency for detailes of Rf and Rd values. Ta = −30 to +85 °C Note: * represents a three-digit alphanumeric which express " Individual Specification". Since the frequency for USB requires high accuracy, the official product name will be decided to match the frequency after evaluation of oscillation on the board that is actually to be used. Please contact your Renesas Technology sales agency. Figure 4.5 Example of Connecting a Ceramic Resonator

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 92 of 1692 REJ09B0393-0100

4.8.2 Input of an External 48-MHz Clock Signal

Figure 4.6 shows an example of the connections for input of an external 48-MHz clock signal. The USBXTAL pin must be left open. USBEXTAL USBXTAL Open state Input external clock Figure 4.6 Example of Connecting an External 48-MHz Clock Table 4.7 shows the input conditions for the external 48-MHz clock. Table 4.7 Input Conditions for the External 48-MHz Clock Item Symbol Min. Max. Unit Reference Figure Frequency (48 MHz) t FREQ 47.88 48.12 MHz Clock rise time t R48 — 3 ns Clock fall time t F48 — 3 ns Duty (tHIGH/tFREQ) t DUTY 40 60 % Figure 4.7 90% 10% tR48 tF48 tHIGH tLOW tFREQ VCC×5USBEXTAL Figure 4.7 Input Timing of External 48-MHz Clock

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 93 of 1692 REJ09B0393-0100

4.8.3 Handling of pins when a Ceramic Resonator is not Connected (the Internal CPG is

Selected or the USB is Not in Use) When a ceramic resonator is not connected, connect the USBEXTAL pin to ground (Vss) and leave the USBEXTAL pin open-circuit as shown in Figure 4.8. Possible clock frequencies for input to EXTAL are fixed to 12 MHz. USBEXTAL USBXTAL Open state Figure 4.8 Handling of Pins when a Ceramic Resonator is not Connected

Section 4 Clock Pulse Generator (CPG) Rev. 1.00 Jun. 26, 2008 Page 94 of 1692 REJ09B0393-0100

4.9 Notes on Board Design

4.9.1 Note on Using an External Crystal Resonator

Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components. CL1 CL2 EXTAL XTAL Signal lines prohibited This LSI The values for CL1 and CL2 should be determined after consultation with the crystal resonator manufacturer. Note: Reference value CL1 = 20 pF CL2 = 20 pF Figure 4.9 Note on Using a Crystal Resonator A circuitry shown in figure 4.10 is recommended as an external circuitry around the PLL. PLLVss must be separated from Vcc and Vss at the board power supply source. Be sure to insert bypass capacitors CB and CPB close to the Vcc and Vss pins. PLLVSS VCL VCC VSS CPB = 0.1 µF* CB = 0.1 µF* Note: * CB and CPB are laminated ceramic capacitors. (Recommended values are shown.) Figure 4.10 Recommended External Circuitry around PLL

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 95 of 1692 REJ09B0393-0100 Section 5 Exception Handling

5.1 Overview

5.1.1 Types of Exception Handling and Priority

Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 5.1 Types of Exception Handling and Priority Order Type Exception Handling Priority Power-on reset Reset Manual reset CPU address error Address error DMAC address error Integer division exception (division by zero) Instruction Integer division exception (overflow) Bank underflow Register bank error Bank overflow NMI User break H-UDI IRQ A/D converter (ADC) Controller area network (RCAN-ET) Direct memory access controller (DMAC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) USB function module (USB) DTC transfer end Interrupt On-chip peripheral modules Multi-function timer pulse unit 2 (MTU2) High Low

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 96 of 1692 REJ09B0393-0100 Type Exception Handling Priority Interrupt On-chip peripheral modules Port output enable 2 (POE2): OEI1 and OEI2 interrupts Multi-function timer pulse unit 2S (MTU2S) Port output enable 2 (POE2): OEI3 interrupt USB function module (USB) USI0/USI1 I C bus interface 3 (IIC3) Synchronous serial communication unit (SSU) Serial communication interface (SCI) Serial communication interface with FIFO (SCIF) Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Instruction Slot illegal instructions (undefined code placed directly after a delayed branch instruction* , instructions that rewrite the PC* , 32-bit instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction) High Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.

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5.1.2 Exception Handling Operations

The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Timing of Source Detection and Start of Handling Power-on reset Starts when the RES pin changes from low to high, when the H-UDI reset negate command is set after the H-UDI reset assert command has been set, or when the WDT overflows. Reset Manual reset Starts when the MRES pin changes from low to high or when the WDT overflows. Address error Detected when instruct ion is decoded and starts when the previous executing instruction finishes executing. Interrupts Detected when instructi on is decoded and starts when the previous executing instruction finishes executing. Bank underflow Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. Register bank error Bank overflow In the state where sa ving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of undefined code anytime except immediately after a delayed branch instruction (delay slot). Slot illegal instructions Starts from the decoding of undefined code placed immediately after a delayed branch instruction (delay slot), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Instructions Integer division instructions Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 98 of 1692 REJ09B0393-0100 When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins running from the PC address fetched from the exception handling vector table. (2) Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts, and Instructions SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than NMI or UBC with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector number of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to an address error, register bank error, NMI interrupt, UBC interrupt, or instruction, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The start address is then fetched from the exception handling vector table and the program begins running from that address.

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5.1.3 Exception Handling Vector Table

Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Handling Vector Table Exception Sources Vector Numbers Vector Table Address Offset PC 0 H'00000000 to H'00000003 Power-on reset SP 1 H'00000004 to H'00000007 PC 2 H'00000008 to H'0000000B Manual reset SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved by system) 5 H'00000014 to H'00000017 Slot illegal instruction 6 H'00000018 to H'0000001B

7 H'0000001C to H'0000001F (Reserved by system)

8 H'00000020 to H'00000023

CPU address error 9 H'00000024 to H'00000027 DMAC address error 10 H'00000028 to H'0000002B NMI 11 H'0000002C to H'0000002F Interrupts User break 12 H'00000030 to H'00000033 (Reserved by system) 13 H'00000034 to H'00000037 H-UDI 14 H'00000038 to H'0000003B Bank overflow 15 H'0000003C to H'0000003F Bank underflow 16 H'00000040 to H'00000043

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 100 of 1692 REJ09B0393-0100 Exception Sources Vector Numbers Vector Table Address Offset Integer division exception (division by zero)

17 H'00000044 to H'00000047

Integer division exception (overflow) 18 H'00000048 to H'0000004B (Reserved by system) 19 H'0000004C to H'0000004F H'0000007C to H'0000007F Trap instruction (user vector) 32 H'00000080 to H'00000083 H'000000FC to H'000000FF External interrupts (IRQ), on-chip peripheral module interrupts* 511 H'00000100 to H'00000103 H'000007FC to H'000007FF Note: * The vector numbers and vector table addre ss offsets for each external interrupt and on- chip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) × 4 Address errors, register bank errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Notes: 1. Vector table add ress offset: See table 5.3. 2. Vector number: See table 5.3.

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5.2 Resets

5.2.1 Types of Reset

A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a manual reset. Table 5.5 Exception Source Detection and Exception Handling Start Timing Conditions for Transition to Reset State Internal States Type RES or MRES H-UDI Command WDT Overflow CPU On-Chip Peripheral Modules, I/O Port WRCSR of WDT, FRQCR of CPG Low — — Initialized Initialized Initialized High H-UDI reset assert command is set — Initialized Initialized Initialized Power-on reset High Command other than H-UDI reset assert is set Power-on reset Initialized Initialized Not initialized Low — — Initialized Not initialized * Not initialized Manual reset High — Manual reset Initialized Not initialized * Not initialized Note: * The BN bit in IBNR of the INTC is initialized.

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5.2.2 Power-On Reset

(1) Power-On Reset by Means of RES Pin When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20 tcyc when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. (2) Power-On Reset by Means of H-UDI Reset Assert Command When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time required between an H-UDI reset assert command and H-UDI reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin.

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 103 of 1692 REJ09B0393-0100 (3) Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT. If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the WDT, the CPU operates in the same way as when a power- on reset was caused by the RES pin.

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5.2.3 Manual Reset

(1) Manual Reset by Means of MRES Pin When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be kept at the low level for at least 20 tcyc. In the manual reset state, the CPU’s internal state is initialized, but all the on-chip peripheral module registers are not initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. (2) Manual Reset Initiated by WDT When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the manual reset state. When manual reset exception processing is started by the WDT, the CPU operates in the same way as when a manual reset was caused by the MRES pin. When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception handling is not executed.

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5.3 Address Errors

5.3.1 Address Error Sources

Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* None (normal) Instruction fetched from on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Address error occurs Instruction fetch CPU Instruction fetched from external memory space in single-chip mode Address error occurs Word data accessed from even address None (normal) Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Byte or word data accessed in on-chip peripheral module space* None (normal) Longword data accessed in 16-bit on-chip peripheral module space* None (normal) Longword data accessed in 8-bit on-chip peripheral module space* None (normal) Data read/write CPU, DMAC, or DTC External memory space accessed when in single chip mode Address error occurs Note: * See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module space and on-chip RAM space.

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5.3.2 Address Error Exception Handling

When an address error occurs, the bus cycle in which the address error occurred ends*. When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service routin e start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Note: * In the case of an address error caused by instruction fetching when data is read or written, if the bus cycle on which the address error occurred is not completed by the end of the operations described above operation 3, the CPU will recommence address error exception processing until the end of that bus cycle.

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5.4 Register Bank Errors

5.4.1 Register Bank Error Sources

(1) Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks.

5.4.2 Register Bank E rror Exception Handling

When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.

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5.5 Interrupts

5.5.1 Interrupt Sources

Table 5.7 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller (UBC) 1 H-UDI User debugging interface (H-UDI) 1 IRQ IRQ0 to IRQ7 pins (external input) 8 A/D converter (ADC) 3 Controller area network (RCAN-ET) 4 Direct memory access controller (DMAC) 16 Compare match timer (CMT) 2 Bus state controller (BSC) 1 Watchdog timer (WDT) 1 USB function module (USB) 4 Multi-function timer pulse unit 2 (MTU2) 28 Multi-function timer pulse unit 2S (MTU2S) 13 Port output enable 2 (POE2) 3 I C bus interface 3 (IIC3) 5 Synchronous serial communication unit (SSU) 3 Serial communication interface (SCI) 16 On-chip peripheral module Serial communication interface with FIFO (SCIF) 4 Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets.

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5.5.2 Interrupt Priority Level

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels of IRQ interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 05 to 18 (IPR01, IPR02, and IPR05 to IPR18) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18), for details of IPR01, IPR02, and IPR05 to IPR18. Table 5.8 Interrupt Priority Order Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. H-UDI 15 Fixed priority level. IRQ On-chip peripheral module 0 to 15 Set with interrupt priority registers 01, 02, and 05 to 18 (IPR01, IPR02, and IPR05 to IPR18).

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5.5.3 Interrupt Ex ception Handling

When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than NMI or UBC with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector number of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to an address error, NMI interrupt, UBC interrupt, or instruction, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception occurs. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 6.6, Operation, for further details of interrupt exception handling.

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5.6 Exceptions Triggered by Instructions

5.6.1 Types of Exceptions Triggered by Instructions

Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instruction TRAPA Slot illegal instructions Undefined code placed immediately after a delayed branch instruction (delay slot), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. General illegal instructions Undefined code anywhere besides in a delay slot Division by zero DIVU, DIVS Integer division exceptions Negative maximum value ÷ (−1) DIVS

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5.6.2 Trap Instructions

When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.

5.6.3 Slot Illegal Instructions

An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates as follows: 1. The exception service routine st art address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.

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5.6.4 General Illegal Instructions

When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however, the program counter value stored is the start address of the undefined code.

5.6.5 Integer Division Instructions

When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by −1. The CPU operates as follows: 1. The exception service routin e start address which corresponds to the integer division instruction exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.

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5.7 When Exception Sources Are Not Accepted

When an address error, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Address Error Register Bank Error (Overflow) Interrupt Immediately after a delayed branch instruction Not accepted Not accepted Not accepted Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF

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5.8 Stack Status after Exception Handling Ends

The status of the stack after exception handling ends is as shown in table 5.11. Table 5.11 Stack Status After Exception Handling Ends Exception Type Stack Status Address error 32 bits 32 bitsSR Address of instruction after executed instructionSP Interrupt 32 bits 32 bitsSR Address of instruction after executed instructionSP Register bank error (overflow) 32 bits 32 bitsSR Address of instruction after executed instructionSP Register bank error (underflow) 32 bits 32 bitsSR Start address of relevant RESBANK instructionSP Trap instruction 32 bits 32 bitsSR Address of instruction after TRAPA instructionSP Slot illegal instruction 32 bits 32 bitsSR Jump destination address of delayed branch instructionSP

Section 5 Exception Handling Rev. 1.00 Jun. 26, 2008 Page 116 of 1692 REJ09B0393-0100 Exception Type Stack Status General illegal instruction 32 bits 32 bitsSR Start address of general illegal instructionSP Integer division instruction 32 bits 32 bitsSR Start address of relevant integer division instructionSP

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5.9 Usage Notes

5.9.1 Value of Stack Pointer (SP)

The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling.

5.9.2 Value of Vector Base Register (VBR)

The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling.

5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling

When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined.

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Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 119 of 1692 REJ09B0393-0100 Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority.

6.1 Features

• 16 levels of interrupt priority can be set By setting the sixteen interrupt priority registers, the priority of IRQ interrupts and on-chip peripheral module interrupts can be selected from 16 levels for request sources.
• NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as the noise canceler function.
• Occurrence of interrupt can be reported externally (IRQOUT pin) For example, when this LSI has released the bus mastership, this LSI can inform the external bus master of occurrence of an on-chip peripheral module interrupt and request for the bus mastership.
• Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. Figure 6.1 shows a block diagram of the INTC.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 120 of 1692 REJ09B0393-0100 UBC UBC: H-UDI: DMAC: CMT: BSC: WDT: MTU2: MTU2S: POE2: ADC: IIC3: SCI: SCIF: SSU: USB: DTC: RCAN: User break controller User debugging interface Direct memory access controller Compare match timer Bus state controller Watchdog timer Multi-function timer pulse unit 2 Multi-function timer pulse unit 2S Port output enable 2 A/D converter I 2C bus interface 3*1 Serial communication interface Serial communication interface with FIFO Synchronous serial communication unit* USB function module*1 Data transfer controller Controller area network* ICR0: ICR1: ICR2: IRQRR: IBCR: IBNR: IPR01, IPR02, IPR05 to IPR18: Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register Bank control register Bank number register Interrupt priority registers 01, 02, 05 to 18 SR CPU I3 I2 I1 I0 (Interrupt request) IBCR IPR01, IPR02, IPR05 to IPR18 ICR0 ICR2 IBNR ICR1 IRQRR IRQ0 IRQ1 IRQ2 IRQ3 IRQ5 IRQ6 IRQ7 IRQ4 NMI IRQOUT IPR INTC DMAC DTC Priority identifier Control input DTCERA to DTCERE CHCR[11:8] H-UDI DMAC CMT MTU2 ADC SCI SCIF MTU2S IIC3 POE2 BSC USB RCAN WDT SSU Interrupt request Bus interfaceModule bus [Legend] Internal bus CPU/DTC interrupt request identifier Comparator (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU/DTC/DMAC interrupt request identifier Notes: 1. Only in SH7286 and SH7285 2. Only in SH7286 Figure 6.1 Block Diagram of INTC

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6.2 Input/Output Pins

Table 6.1 shows the pin configuration of the INTC. Table 6.1 Pin Configuration Pin Name Symbol I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt request input pins IRQ7 to IRQ0 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of signal to report occurrence of interrupt source

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6.3 Register Descriptions

The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 6.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Interrupt control register 0 ICR0 R/W * H'FFFE0800 16, 32 Interrupt control register 1 ICR1 R/W H'0000 H'FFFE0802 16, 32 IRQ interrupt request register IRQRR R/(W) * H'0000 H'FFFE0806 16, 32 Bank control register IB CR R/W H'0000 H'FFFE080C 16, 32 Bank number register IBNR R/W H'0000 H'FFFE080E 16, 32 Interrupt priority register 01 IPR01 R/W H'0000 H'FFFE0818 16, 32 Interrupt priority register 02 IPR02 R/W H'0000 H'FFFE081A 16, 32 Interrupt priority register 05 IPR05 R/W H'0000 H'FFFE0820 16, 32 Interrupt priority register 06 IPR06 R/W H'0000 H'FFFE0C00 16, 32 Interrupt priority register 07 IPR07 R/W H'0000 H'FFFE0C02 16, 32 Interrupt priority register 08 IPR08 R/W H'0000 H'FFFE0C04 16, 32 Interrupt priority register 09 IPR09 R/W H'0000 H'FFFE0C06 16, 32 Interrupt priority register 10 IPR10 R/W H'0000 H'FFFE0C08 16, 32 Interrupt priority register 11 IPR11 R/W H'0000 H'FFFE0C0A 16, 32 Interrupt priority register 12 IPR12 R/W H'0000 H'FFFE0C0C 16, 32 Interrupt priority register 13 IPR13 R/W H'0000 H'FFFE0C0E 16, 32 Interrupt priority register 14 IPR14 R/W H'0000 H'FFFE0C10 16, 32 Interrupt priority register 15 IPR15 R/W H'0000 H'FFFE0C12 16, 32 Interrupt priority register 16 IPR16 R/W H'0000 H'FFFE0C14 16, 32 Interrupt priority register 17 IPR17 R/W H'0000 H'FFFE0C16 16, 32 Interrupt priority register 18 IPR18 R/W H'0000 H'FFFE0C18 16, 32 USB-DTC transfer interrupt request register USDTENDRR R/(W) * H'0000 H'FFFE0C50 16, 32 Notes: Two access cycles are needed for word access, and four access cycles for longword access. 1. When the NMI pin is high, becomes H'8000; when low, becomes H'0000. 2. Only 0 can be written after reading 1, to clear the flag.

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6.3.1 Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18)

IPR01, IPR02, and IPR05 to IPR18 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts and on-chip peripheral module interrupts. Table 6.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05 to IPR18. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Table 6.3 Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR18 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Interrupt priority register 01 IRQ0 IRQ1 IRQ2 IRQ3 Interrupt priority register 02 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt priority register 05 Reserved Reserved ADI0 ADI1 Interrupt priority register 06 DMAC0 DMAC1 DMAC2 DMAC3 Interrupt priority register 07 DMAC4 DMAC5 DMAC6 DMAC7 Interrupt priority register 08 CMT0 CMT1 BSC WDT Interrupt priority register 09 MTU0 (TGI0A to TGI0D) MTU0 (TCI0V, TGI0E, TGI0F) MTU1 (TGI1A, TGI1B) MTU1 (TCI1V, TCI1U) Interrupt priority register 10 MTU2 (TGI2A, TGI2B) MTU2 (TCI2V, TCI2U) MTU3 (TGI3A to TGI3D) MTU3 (TCI3V) Interrupt priority register 11 MTU4 (TGI4A to TGI4D) MTU4 (TCI4V) MTU5 (TGI5U, TGI5V, TGI5W) POE2 (OEI1, OEI2) Interrupt priority register 12 MTU3S (TGI3A to TGI3D) MTU3S (TCI3V) MTU4S (TGI4A to TGI4D) MTU4S (TCI4V)

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 124 of 1692 REJ09B0393-0100 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Interrupt priority register 13 MTU5S (TGI5U, TGI5V, TGI5W) POE2 (OEI3) IIC3* Reserved Interrupt priority register 14 Reserved Reserved Reserved SCIF3 Interrupt priority register 15 Reserved Reserved Reserved Reserved Interrupt priority register 16 SCI0 SCI1 * SCI2 Reserved Interrupt priority register 17 SSU* SCI4 * ADI2 * Reserved Interrupt priority register 18 USB* RCAN * EP1-FIFO full DTC transfer end* EP2-FIFO empty DTC transfer end* Notes: 1. The setting value is invalid in the SH7243. B'1111 should be written to. 2. The setting value is invalid in the SH7243 and SH7285. B'1111 should be written to.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 125 of 1692 REJ09B0393-0100

6.3.2 Interrupt Contro l Register 0 (ICR0)

ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * 000000000000000 RRRRRRR R / W RRRRRRRR Bit: Initial value: R/W: Note: 1 when the NMI pin is high, and 0 when the NMI pin is low.* Bit Bit Name Initial Value R/W Description

15 NMIL * R NMI Input Level

Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 NMIE 0 R/W NMI Edge Select

Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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6.3.3 Interrupt Contro l Register 1 (ICR1)

ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Bit Bit Name Initial Value R/W Description

15 IRQ71S 0 R/W

14 IRQ70S 0 R/W

13 IRQ61S 0 R/W

12 IRQ60S 0 R/W

11 IRQ51S 0 R/W

10 IRQ50S 0 R/W

9 IRQ41S 0 R/W

8 IRQ40S 0 R/W

7 IRQ31S 0 R/W

6 IRQ30S 0 R/W

5 IRQ21S 0 R/W

4 IRQ20S 0 R/W

3 IRQ11S 0 R/W

2 IRQ10S 0 R/W

1 IRQ01S 0 R/W

0 IRQ00S 0 R/W

These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input [Legend] n = 7 to 0

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6.3.4 IRQ Interrupt Re quest Register (IRQRR)

IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. IRQRR is initialized by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 0 can be written to clear the flag after 1 is read.* Bit: Initial value: R/W: 00000000 RRRRRRRR - - - - - - - - IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 128 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

7 IRQ7F 0 R/(W) *

6 IRQ6F 0 R/(W) *

5 IRQ5F 0 R/(W) *

4 IRQ4F 0 R/(W) *

3 IRQ3F 0 R/(W) *

2 IRQ2F 0 R/(W) *

1 IRQ1F 0 R/(W) *

0 IRQ0F 0 R/(W) *

These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. Level detection: 0: IRQn interrupt request has not occurred [Clearing condition]

• IRQn input is high 1: IRQn interrupt has occurred [Setting condition]
• IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions]
• Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF
• Cleared by executing IRQn interrupt exception handling
• Cleared when DTC is activated by the IRQn interrupt, then the DISEL bit in MRB of DTC is set to 0. 1: IRQn interrupt request is detected [Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin [Legend] n = 7 to 0

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6.3.5 Bank Control Register (IBCR)

IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Bit: Initial value: R/W: E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 - Bit Bit Name Initial Value R/W Description

15 E15 0 R/W

14 E14 0 R/W

13 E13 0 R/W

12 E12 0 R/W

11 E11 0 R/W

10 E10 0 R/W

9 E9 0 R/W

8 E8 0 R/W

7 E7 0 R/W

6 E6 0 R/W

5 E5 0 R/W

4 E4 0 R/W

3 E3 0 R/W

2 E2 0 R/W

1 E1 0 R/W

These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of register banks is always disabled for the user break interrupts. 0: Use of register banks is disabled 1: Use of register banks is enabled 0  0 R Reserved This bit is always read as 0. The write value should always be 0.

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6.3.6 Bank Number Register (IBNR)

IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. IBNR is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R R R R R R R R R R R R R Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15, 14 BE[1:0] 00 R/W R egister Bank Enable These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR.

13 BOVE 0 R/W Register Bank Overflow Enable

Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled 12 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 131 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 3 to 0 BN[3:0] 0000 R Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed.

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6.3.7 USB-DTC Transfer Interrupt Request Register (USDTENDRR)

USDTENDRR is a 16-bit register that indicates USB-DTC transfer end interrupt requests, which are on-chip peripheral module interrupts. Writing 0 to the RXF or TXF bit after reading RXF = 1 or TXF = 1 cancels the retained interrupt. USDTENDRR is initialized by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 R/(W)* R/(W)* 00000000 RRRRRRRRRRRRRR Note: Only 0 can be written to clear the flag after 1 is read.* Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description

15 RXF 0 R/(W) * EP1-FIFO Full DTC Transfer End Interrupt Request

0: EP1-FIFO full DTC transfer end interrupt request has not occurred [Clearing conditions]

• Cleared by reading RFX = 1, then writing 0 to RFX
• Cleared by executing EP1-FIFO full DTC transfer end interrupt exception handling 1: EP1-FIFO full DTC transfer end interrupt request has occurred

14 TXF 0 R/(W) * EP2-FIFO Empty DTC Transfer End Interrupt Request

0: EP2-FIFO empty DTC transfer end interrupt request has not occurred [Clearing conditions]

• Cleared by reading TFX = 1, then writing 0 to TFX
• Cleared by executing EP2-FIFO empty DTC transfer end interrupt exception handling 1: EP2-FIFO empty DTC transfer end interrupt request has occurred 13 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 133 of 1692 REJ09B0393-0100

6.4 Interrupt Sources

There are five types of interrupt sources: NMI, user break, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times.

6.4.1 NMI Interrupt

The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.

6.4.2 User Break Interrupt

A user break interrupt which occurs when a break condition set in the user break controller (UBC) matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 7, User Break Controller (UBC).

6.4.3 H-UDI Interrupt

The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level 15. For H-UDI interrupts, see section 29, User Debugging Interface (H-UDI).

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 134 of 1692 REJ09B0393-0100

6.4.4 IRQ Interrupts

IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level setting for IRQ interrupts, an interrupt request signal is sent to the INTC while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 135 of 1692 REJ09B0393-0100

6.4.5 On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:

• A/D converter (ADC)
• Controller area network (RCAN-ET)
• Direct memory access controller (DMAC)
• Compare match timer (CMT)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• USB function module (USB)
• Multi-function timer pulse unit 2 (MTU2)
• Multi-function timer pulse unit 2S (MTU2S)
• Port output enable 2 (POE2)
• I C bus interface 3 (IIC3)
• Synchronous serial communication unit (SSU)
• Serial communication interface (SCI)
• Serial communication interface with FIFO (SCIF) As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 18 can be set for each module by interrupt priority registers 05 to 18 (IPR05 to IPR18). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 136 of 1692 REJ09B0393-0100

6.5 Interrupt Exception Handling Vector Table and Priority

Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the interrupt exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 5.4 in section 5, Exception Handling. The priorities of IRQ interrupts and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 18 (IPR01, IPR02, and IPR05 to IPR18). However, if two or more interrupts specified by the same IPR among IPR05 to IPR18 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 6.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 6.4.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 137 of 1692 REJ09B0393-0100 Table 6.4 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority NMI 11 H'0000002C to H'0000002F 16   High UBC 12 H'00000030 to H'00000033 15   H-UDI 14 H'00000038 to H'0000003B 15   IRQ0 64 H'00000100 to H'00000103 0 to 15 (0) IPR01 (15 to 12)  IRQ1 65 H'00000104 to H'00000107 0 to 15 (0) IPR01 (11 to 8)  IRQ2 66 H'00000108 to H'0000010B 0 to 15 (0) IPR01 (7 to 4)  IRQ3 67 H'0000010C to H'0000010F 0 to 15 (0) IPR01 (3 to 0)  IRQ4 68 H'00000110 to H'00000113 0 to 15 (0) IPR02 (15 to 12)  IRQ5 69 H'00000114 to H'00000117 0 to 15 (0) IPR02 (11 to 8)  IRQ6 70 H'00000118 to H'0000011B 0 to 15 (0) IPR02 (7 to 4)  IRQ IRQ7 71 H'0000011C to H'0000011F 0 to 15 (0) IPR02 (3 to 0)  ADI0 92 H'00000170 to H'00000173 0 to 15 (0) IPR05 (7 to 4)  ADI1 96 H'00000180 to H'00000183 0 to 15 (0) IPR05 (3 to 0)  ADC ADI2 100 H'00000190 to H'00000193 0 to 15 (0) IPR17 (7 to 4)  Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 138 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority ERS_0 104 H'000001A0 to H'000001A3 0 to 15 (0) 1 High OVR_0 105 H'000001A4 to H'000001A7 0 to 15 (0) 2 RM0_0, RM1_0 106 H'000001A8 to H'000001AB 0 to 15 (0) 3 RCAN SLE_0 107 H'000001AC to H'000001AF 0 to 15 (0) IPR18 (11 to 8) DEI0 108 H'000001B0 to H'000001B3

1 DMAC0

HEI0 109 H'000001B4 to H'000001B7 0 to 15 (0) IPR06 (15 to 12) DEI1 112 H'000001C0 to H'000001C3

1 DMAC1

HEI1 113 H'000001C4 to H'000001C7 0 to 15 (0) IPR06 (11 to 8) DEI2 116 H'000001D0 to H'000001D3

1 DMAC2

HEI2 117 H'000001D4 to H'000001D7 0 to 15 (0) IPR06 (7 to 4) DEI3 120 H'000001E0 to H'000001E3

1 DMAC3

HEI3 121 H'000001E4 to H'000001E7 0 to 15 (0) IPR06 (3 to 0) DEI4 124 H'000001F0 to H'000001F3

1 DMAC4

HEI4 125 H'000001F4 to H'000001F7 0 to 15 (0) IPR07 (15 to 12) DEI5 128 H'00000200 to H'00000203 DMAC DMAC5 HEI5 129 H'00000204 to H'00000207 0 to 15 (0) IPR07 (11 to 8) Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 139 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority DEI6 132 H'00000210 to H'00000213

1 High DMAC6

HEI6 133 H'00000214 to H'00000217 0 to 15 (0) IPR07 (7 to 4) DEI7 136 H'00000220 to H'00000223 DMAC DMAC7 HEI7 137 H'00000224 to H'00000227 0 to 15 (0) IPR07 (3 to 0) CMI0 140 H'00000230 to H'00000233 0 to 15 (0) IPR08 (15 to 12)  CMT CMI1 144 H'00000240 to H'00000243 0 to 15 (0) IPR08 (11 to 8)  BSC CMI 148 H'00000250 to H'00000253 0 to 15 (0) IPR08 (7 to 4)  WDT ITI 152 H'00000260 to H'00000263 0 to 15 (0) IPR08 (3 to 0)  EP1-FIFO full DTC transfer end

154 H'00000268 to

H'0000026B 0 to 15 (0) IPR18 (7 to 4)  USB EP2-FIFO empty DTC transfer end

155 H'0000026C to

H'0000026F 0 to 15 (0) IPR18 (3 to 0)  TGIA_0 156 H'00000270 to H'00000273 TGIB_0 157 H'00000274 to H'00000277 TGIC_0 158 H'00000278 to H'0000027B TGID_0 159 H'0000027C to H'0000027F 0 to 15 (0) IPR09 (15 to 12) TCIV_0 160 H'00000280 to H'00000283 TGIE_0 161 H'00000284 to H'00000287 MTU2 MTU0 TGIF_0 162 H'00000288 to H'0000028B 0 to 15 (0) IPR09 (11 to 8) Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 140 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority TGIA_1 164 H'00000290 to H'00000293

1 High

TGIB_1 165 H'00000294 to H'00000297 0 to 15 (0) IPR09 (7 to 4) TCIV_1 168 H'000002A0 to H'000002A3 MTU1 TCIU_1 169 H'000002A4 to H'000002A7 0 to 15 (0) IPR09 (3 to 0) TGIA_2 172 H'000002B0 to H'000002B3 TGIB_2 173 H'000002B4 to H'000002B7 0 to 15 (0) IPR10 (15 to 12) TCIV_2 176 H'000002C0 to H'000002C3 MTU2 TCIU_2 177 H'000002C4 to H'000002C7 0 to 15 (0) IPR10 (11 to 8) TGIA_3 180 H'000002D0 to H'000002D3 TGIB_3 181 H'000002D4 to H'000002D7 TGIC_3 182 H'000002D8 to H'000002DB TGID_3 183 H'000002DC to H'000002DF 0 to 15 (0) IPR10 (7 to 4) MTU2 MTU3 TCIV_3 184 H'000002E0 to H'000002E3 0 to 15 (0) IPR10 (3 to 0)  Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 141 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority TGIA_4 188 H'000002F0 to H'000002F3 TGIB_4 189 H'000002F4 to H'000002F7 TGIC_4 190 H'000002F8 to H'000002FB TGID_4 191 H'000002FC to H'000002FF 0 to 15 (0) IPR11 (15 to 12) MTU4 TCIV_4 192 H'00000300 to H'00000303 0 to 15 (0) IPR11 (11 to 8)  TGIU_5 196 H'00000310 to H'00000313 TGIV_5 197 H'00000314 to H'00000317 MTU2 MTU5 TGIW_5 198 H'00000318 to H'0000031B 0 to 15 (0) IPR11 (7 to 4) OEI1 200 H'00000320 to H'00000323

1 POE2

OEI2 201 H'00000324 to H'00000327 0 to 15 (0) IPR11 (3 to 0) TGIA_3 204 H'00000330 to H'00000333 TGIB_3 205 H'00000334 to H'00000337 TGIC_3 206 H'00000338 to H'0000033B TGID_3 207 H'0000033C to H'0000033F 0 to 15 (0) IPR12 (15 to 12) MTU2S MTU3S TCIV_3 208 H'00000340 to H'00000343 0 to 15 (0) IPR12 (11 to 8)  Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 142 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority TGIA_4 212 H'00000350 to H'00000353 TGIB_4 213 H'00000354 to H'00000357 TGIC_4 214 H'00000358 to H'0000035B TGID_4 215 H'0000035C to H'0000035F 0 to 15 (0) IPR12 (7 to 4) MTU4S TCIV_4 216 H'00000360 to H'00000363 0 to 15 (0) IPR12 (3 to 0)  TGIU_5 220 H'00000370 to H'00000373 TGIV_5 221 H'00000374 to H'00000377 MTU2S MTU5S TGIW_5 222 H'00000378 to H'0000037B 0 to 15 (0) IPR13 (15 to 12) High POE2 OEI3 224 H'00000380 to H'00000383 0 to 15 (0) IPR13 (11 to 8)  USI0 226 H'00000388 to H'0000038B

1 USB

USI1 227 H'0000038C to H'0000038F 0 to 15 (0) IPR18 (15 to 12) STPI 228 H'00000390 to H'00000393 NAKI 229 H'00000394 to H'00000397 RXI 230 H'00000398 to H'0000039B TXI 231 H'0000039C to H'0000039F IIC3 TEI 232 H'000003A0 to H'000003A3 0 to 15 (0) IPR13 (7 to 4) Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 143 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority SSERI 233 H'000003A4 to H'000003A7 SSRXI 234 H'000003A8 to H'000003AB SSU SSTXI 235 H'000003AC to H'000003AF 0 to 15 (0) IPR17 (15 to 12) ERI4 236 H'000003B0 to H'000003B3 RXI4 237 H'000003B4 to H'000003B7 TXI4 238 H'000003B8 to H'000003BB SCI4 TEI4 239 H'000003BC to H'000003BF 0 to 15 (0) IPR17 (11 to 8) ERI0 240 H'000003C0 to H'000003C3 RXI0 241 H'000003C4 to H'000003C7 TXI0 242 H'000003C8 to H'000003CB SCI0 TEI0 243 H'000003CC to H'000003CF 0 to 15 (0) IPR16 (15 to 12) ERI1 244 H'000003D0 to H'000003D3 RXI1 245 H'000003D4 to H'000003D7 TXI1 246 H'000003D8 to H'000003DB High SCI SCI1 TEI1 247 H'000003DC to H'000003DF 0 to 15 (0) IPR16 (11 to 8) Low

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 144 of 1692 REJ09B0393-0100 Interrupt Vector Interrupt Source Number Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bit) IPR Setting Unit Internal Priority Default Priority ERI2 248 H'000003E0 to H'000003E3 RXI2 249 H'000003E4 to H'000003E7 TXI2 250 H'000003E8 to H'000003EB High SCI SCI2 TEI2 251 H'000003EC to H'000003EF 0 to 15 (0) IPR16 (7 to 4) BRI3 252 H'000003F0 to H'000003F3 ERI3 253 H'000003F4 to H'000003F7 RXI3 254 H'000003F8 to H'000003FB SCIF SCIF3 TXI3 255 H'000003FC to H'000003FF 0 to 15 (0) IPR14 (3 to 0) Low

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6.6 Operation

6.6.1 Interrupt Op eration Sequence

The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller select s the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 05 to 18 (IPR01, IPR02, and IPR05 to IPR18). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 6.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent fro m the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 6.4). 6. The interrupt exception service routine start address is fetched from the exception handling vector table corresponding to the accepted interrupt. 7. The status register (SR) is saved onto the stac k, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 8. The program counter (PC) is saved onto the stack. 9. The CPU jumps to the fetched interrupt exce ption service routine start address and starts executing the program. The jump that occurs is not a delayed branch. 10. A high level is output from the IRQOUT pin. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just being accepted, the IRQOUT pin holds low level.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 146 of 1692 REJ09B0393-0100 Notes: The interrupt sour ce flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 147 of 1692 REJ09B0393-0100 No No No No Yes Yes Yes Yes Yes Yes No Yes No Yes Yes No No No No Program execution state Interrupt? NMI? User break? I3 to I0 ≤ level 14? Level 14 interrupt? Level 1 interrupt? I3 to I0 ≤ level 13? I3 to I0 = level 0? H-UDI interrupt? Level 15 interrupt? IRQOUT = low Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 IRQOUT = high Read exception handling vector table Branch to interrupt exception service routine Figure 6.2 Interrupt Operation Flow

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6.6.2 Stack after Interrupt Exception Handling

Figure 6.3 shows the stack after interrupt exception handling. Address SP*24n – 8 PC *1 SR4n – 4 32 bits 32 bits Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executed instruction 2. Always make sure that SP is a multiple of 4. Figure 6.3 Stack after Interrupt Exception Handling

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6.7 Interrupt Response Time

Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 6.5 Interrupt Response Time Number of States Item NMI UBC H-UDI IRQ Peripheral Module Remarks

2 Icyc +

1 Bcyc +

2 Pcyc

Time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU

2 Bcyc +

1 Pcyc

3 Icyc 2 Icyc +

3 Bcyc +

1 Bcyc

Interrupts without the DTC activation sources. Min. 3 Icyc + m1 + m2 No register banking Max. 4 Icyc + 2 (m1 + m2) + m3 Min. is when the interrupt wait time is zero. Max. is when a higher- priority interrupt request has occurred during interrupt exception handling. Min. — — 3 Icyc + m1 + m2 Register banking without register bank overflow Max. — — 12 Icyc + m1 + m2 Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. — — 3 Icyc + m1 + m2 Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in exception service routine is fetched Register banking with register bank overflow Max. — — 3 Icyc + m1 + m2 + 19(m4) Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction.

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 150 of 1692 REJ09B0393-0100 Number of States Item NMI UBC H-UDI IRQ Peripheral Module Remarks Min. 5 Icyc +

1 Pcyc +

6 Icyc +

5 Icyc +

100-MHz operation* 0.080 to 0.150 µs No register banking Max. 6 Icyc + 2(m1 + m2) +

7 Icyc +

2(m1 + m2) + 2(m1 + m2) + 2(m1 + m2) + 2(m1 + m2) + 100-MHz operation* 0.120 to 0.190 µs Min. — — 5 Icyc + 100-MHz operation* 0.080 to 0.150 µs Register banking without register bank overflow Max. — — 14 Icyc +

14 Icyc +

100-MHz operation* 0.170 to 0.240 µs Min. — — 5 Icyc + 100-MHz operation* 0.080 to 0.150 µs Interrupt response time Register banking with register bank overflow Max. — — 5 Icyc + 19(m4) 19(m4) 19(m4) 100-MHz operation* 0.270 to 0.340 µs Notes: m1 to m4 are the number of stat es needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case that m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case that (I φ, Bφ, Pφ) = (100 MHz, 50 MHz, 50 MHz).

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2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3

3 Icyc + m1 + m2

Instruction (instruction replacing interrupt exception handling) m1: m2: m3: First instruction in interrupt exception service routine Interrupt acceptance DEEM M M FD E [Legend] Vector address read Saving of SR (stack) Saving of PC (stack) Instruction fetch. Instruction is fetched from memory in which program is stored. Instruction decoding. Fetched instruction is decoded. Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. Memory access. Memory data access is performed. Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking)

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2 Icyc + 3 Bcyc + 1 Pcyc 1 Icyc + m1 + 2(m2) + m3

3 Icyc + m1

[Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance Multiple interrupt acceptance First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine Figure 6.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking) F [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow)

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2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc + m1 + m2

9 Icyc

RESBANK instruction DEEEEEEEE E DEEM M M E F D [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) F [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) ... Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow)

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2 Icyc + 3 Bcyc + 1 Pcyc 1 Icyc + m1 + m2 + 2(m4)

2 Icyc + 17(m4)

RESBANK instruction DEMMM MMM W DEEM M M F D m4 m4 [Legend] m1: m2: m3: m4: Vector address read Saving of SR (stack) Saving of PC (stack) Restoration of banked registers Interrupt acceptance First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) ... ... ... Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow)

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6.8 Register Banks

This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration. General registers Bank control register Bank number register Bank control registers (interrupt controller) Banked register Vector table address offset Note: Interrupt generated (save) RESBANK instruction (restore) Registers Register banks Bank 0 Bank 1 .... Bank 14 R14 R15 SR GBR VBR TBR MACH MACL PR PC Control registers System registers R14 GBR VTO VTO: IBCR IBNR MACH MACL PR Figure 6.10 Overview of Register Bank Configuration

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6.8.1 Banked Register and Input/Output of Banks

(1) Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset are banked. (2) Register Banks This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in last- out (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to.

6.8.2 Bank Save and Restore Operations

(1) Saving to Bank Figure 6.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: a. Assume that the bank number bit value in the bank number register (IBNR), BN, is "i" before the interrupt is generated. b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. c. The BN value is incremented by 1. Bank 0 Register banks Registers Bank 1 Bank i Bank i + 1 Bank 14 (a) (c) (b) BN GBR MACH MACL PR VTO R0 to R14 Figure 6.11 Bank Save Operations

Section 6 Interrupt Controller (INTC) Rev. 1.00 Jun. 26, 2008 Page 157 of 1692 REJ09B0393-0100 Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. F (1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 (4) R4, R5, R6, R7 (5) R0, R1, R2, R3Overrun fetch Saved to bank D E EMMM E F FD E [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) First instruction in interrupt exception service routine Instruction (instruction replacing interrupt exception handling) Figure 6.12 Bank Save Timing (2) Restoration from Bank The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt service routine, execute the RTE instruction to return from the exception handling.

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6.8.3 Save and Restore Operations after Saving to All Banks

If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack 1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, …, R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the ba nk number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the ba nk number register (IBNR) remains set to the maximum value of 15.

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6.8.4 Register Bank Exception

There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0.

6.8.5 Register Bank E rror Exception Handling

When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address.

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6.9 Data Transfer with Interrupt Request Signals

Interrupt request signals can be used to trigger the following data transfer.

• Only the DMAC is activated and no CPU interrupt occurs.
• Only the DTC is activated and a CPU interrupt may occur depending on the DTC setting. Interrupt sources that are designated to activate the DMAC are masked without being input to the INTC. The mask condition is as follows: Mask condition = DME • (DE0 • interrupt source select 0 + DE1 • interrupt source select 1 + DE2 • interrupt source select 2 + DE3 • interrupt source select 3 + DE4 • interrupt source select 4 + DE5 • interrupt source select 5 + DE6
• interrupt source select 6 + DE7 • interrupt source select 7) Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7 of the DMAC. For details, see section 10, Direct Memory Access Controller (DMAC). The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The DTCE clearing condition and interrupt source flag clearing condition are as follows: DTCE clearing condition = DTC transfer end • DTCECLR Interrupt source flag clearing condition = DTC transfer end • DTCECLR + DMAC transfer end However, DTCECLR = DISEL + counter value of 0

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6.9.1 Handling Interrupt Request Signals as DTC Activating Sources and CPU Interrupt

Sources but Not as DMAC Activating Sources 1. Do not select DMAC activat ing sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC. 2. Set both the corresponding DTCE bit and DISEL bit to 1 in the DTC. 3. Activating sources are applied to the DTC when interrupts occur. 4. The DTC clears the DTCE bit to 0 and sends interrupt requests to the CPU when starting data transfer. The DTC does not clear the activating sources. 5. The CPU clears the interrupt sources in the interrupt exception handling routine, and then confirms the transfer counter value. If the transfer counter value is not 0, the DTCE bit is set to 1 and the next data transfer enabled. If the transfer counter value is 0, the CPU performs the necessary termination processing in the interrupt exception handling routine.

6.9.2 Handling Interrupt Request Signals as DMAC Activating Sources but Not as CPU

1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU interrupt sources regardless of the interrupt priority register and DTC register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears the activating so urces when starting data transfer.

6.9.3 Handling Interrupt Request Signals as DTC Activating Sources but Not as CPU

Interrupt Sources or DMAC Activating Sources 1. Do not select DMAC activat ing sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC. 2. Set the corresponding DTCE bit to 1 an d clear the DISEL bit to 0 in the DTC. 3. Activating sources are applied to the DTC when interrupts occur. 4. The DTC clears the activating sources when star ting data transfer. Interrupt requests are not sent to the CPU because the DTCE bit remains set to 1. 5. However, when the transfer counter value is 0, the DTCE bit is cleared to 0 and interrupt requests are sent to the CPU. 6. The CPU performs the necessary termination pr ocessing in the interrupt exception handling routine.

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6.9.4 Handling Interrupt Reque st Signals as CPU Interrupt Sources but Not as DTC

Activating Sources or DMAC Activating Sources 1. Do not select DMAC activat ing sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC. 2. Clear the corresponding DTCE bit to 0 in the DTC. 3. Interrupt requests are sent to the CPU when interrupts occur. 4. The CPU clears the interrupt sources and performs the necessary termination processing in the interrupt exception handling routine.

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6.10 Usage Note

6.10.1 Timing to Clear an Interrupt Source

The interrupt source flags should be cleared in the interrupt exception service routine. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction.

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 165 of 1692 REJ09B0393-0100 Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction fetch or data read/write (bus master (CPU, DMAC, or DTC) selection in the case of data read/write), data size, data contents, address value, and stop timing in the case of instruction fetch are break conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C bus and internal bus (I bus).

7.1 Features

1. The following break comparison conditions can be set. Number of break channels: four channels (channels 0 to 3) User break can be requested as the independent condition on channels 0, 1, 2, and 3.

• Address Comparison of the 32-bit address is maskable in 1-bit units. One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus (IAB)) can be selected.
• Bus master when I bus is selected Selection of CPU cycles, DMAC cycles, or DTC cycles
• Bus cycle Instruction fetch (only when C bus is selected) or data access
• Read/write
• Operand size Byte, word, and longword 2. Exception handling routine for user-specified break conditions can be executed. 3. In an instruction fetch cycle, it can be selected whether PC breaks are set before or after an instruction is executed. 4. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.

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7.2 Input/Output Pin

Table 7.1 shows the pin configuration of the UBC. Table 7.1 Pin Configuration Pin Name Symbol I/O Function UBC trigger UBCTRG Output Indicates that a setting condition is satisfied on either channel 0, 1, 2, or 3 of the UBC.

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7.3 Register Descriptions

The UBC has the following registers. Table 7.2 Register Configuration Channel Register Name Abbrevia- tion R/W Initial Value Address Access Size Break address register_0 BAR_0 R/W H'00000000 H'FFFC0400 32 Break address mask register_0 BAMR_0 R/W H'00000000 H'FFFC0404 32 Break bus cycle register_0 BBR_0 R/W H'0000 H'FFFC04A0 16 Break address register_1 BAR_1 R/W H'00000000 H'FFFC0410 32 Break address mask register_1 BAMR_1 R/W H'00000000 H'FFFC0414 32 Break bus cycle register_1 BBR_1 R/W H'0000 H'FFFC04B0 16 Break address register_2 BAR_2 R/W H'00000000 H'FFFC0420 32 Break address mask register_2 BAMR_2 R/W H'00000000 H'FFFC0424 32 Break bus cycle register_2 BBR_2 R/W H'0000 H'FFFC04A4 16 Break address register_3 BAR_3 R/W H'00000000 H'FFFC0430 32 Break address mask register_3 BAMR_3 R/W H'00000000 H'FFFC0434 32 Break bus cycle register_3 BBR_3 R/W H'0000 H'FFFC04B4 16 Common Break control register BRCR R/W H'00000000 H'FFFC04C0 32

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7.3.1 Break Address Register_0 (BAR_0)

BAR_0 is a 32-bit readable/writable register. BAR_0 specifies the address used as a break condition in channel 0. The control bits CD0_1 and CD0_0 in the break bus cycle register_0 (BBR_0) select one of the three address buses for a break condition of channel 0. BAR_0 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BA0_31BA0_30BA0_29BA0_28BA0_27BA0_26BA0_25BA0_24BA0_23BA0_22BA0_21BA0_20BA0_19BA0_18BA0_17BA0_16 BA0_15BA0_14BA0_13BA0_12BA0_11BA0_10 BA0_9 BA0_8 BA0_7 BA0_6 BA0_5 BA0_4 BA0_3 BA0_2 BA0_1 BA0_0 Bit Bit Name Initial Value R/W Description 31 to 0 BA0_31 to BA0_0 All 0 R/W Break Address 0 Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions of channel 0. When the C bus and instruction fetch cycle are selected by BBR_0, specify an FAB address in bits BA0_31 to BA0_0. When the C bus and data access cycle are selected by BBR_0, specify an MAB address in bits BA0_31 to BA0_0. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_0 to 0.

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7.3.2 Break Address Mask Register_0 (BAMR_0)

BAMR_0 is a 32-bit readable/writable register. BAMR_0 specifies bits masked in the break address bits specified by BAR_0. BAMR_0 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BAM0_31 BAM0_30 BAM0_29 BAM0_28 BAM0_27 BAM0_26 BAM0_25 BAM0_24 BAM0_23 BAM0_22 BAM0_21 BAM0_20 BAM0_19 BAM0_18 BAM0_17 BAM0_16 BAM0_15 BAM0_14 BAM0_13 BAM0_12 BAM0_11 BAM0_10 BAM0_9 BAM0_8 BAM0_7 BAM0_6 BAM0_5 BAM0_4 BAM0_3 BAM0_2 BAM0_1 BAM0_0 Bit Bit Name Initial Value R/W Description 31 to 0 BAM0_31 to BAM0_0 All 0 R/W Break Address Mask 0 Specify bits masked in the channel-0 break address bits specified by BAR_0 (BA0_31 to BA0_0). 0: Break address bit BA0_n is included in the break condition 1: Break address bit BA0_n is masked and not included in the break condition Note: n = 31 to 0

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7.3.3 Break Bus Cycl e Register_0 (BBR_0)

BBR_0 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions of channel 0. BBR_0 is initialized to H'0000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 UBID0 0 R/W User Break Interrupt Disable 0

Disables or enables user break interrupt requests when a channel-0 break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12, 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CP0[2:0] 000 R/W I- Bus Bus Master Select 0 Select the bus master when the bus cycle of the channel-0 break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). xx1: CPU cycle is included in break conditions x1x: DMAC cycle is included in break conditions 1xx: DTC cycle is included in break conditions

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 172 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD0[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select 0 Select the C bus cycle or I bus cycle as the bus cycle of the channel-0 break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID0[1:0] 00 R/W Instructi on Fetch/Data Access Select 0 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel-0 break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW0[1:0] 00 R/W Read/Write Select 0 Select the read cycle or write cycle as the bus cycle of the channel-0 break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle 1, 0 SZ0[1:0] 00 R/W O perand Size Select 0 Select the operand size of the bus cycle for the channel-0 break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access [Legend] x: Don't care

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7.3.4 Break Address Register_1 (BAR_1)

BAR_1 is a 32-bit readable/writable register. BAR_1 specifies the address used as a break condition in channel 1. The control bits CD1_1 and CD1_0 in the break bus cycle register_1 (BBR_1) select one of the three address buses for a break condition of channel 1. BAR_1 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BA1_31BA1_30BA1_29BA1_28BA1_27BA1_26BA1_25BA1_24BA1_23BA1_22BA1_21BA1_20BA1_19BA1_18BA1_17BA1_16 BA1_15BA1_14BA1_13BA1_12BA1_11BA1_10 BA1_9 BA1_8 BA1_7 BA1_6 BA1_5 BA1_4 BA1_3 BA1_2 BA1_1 BA1_0 Bit Bit Name Initial Value R/W Description 31 to 0 BA1_31 to BA1_0 All 0 R/W Break Address 1 Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions of channel 1. When the C bus and instruction fetch cycle are selected by BBR_1, specify an FAB address in bits BA1_31 to BA1_0. When the C bus and data access cycle are selected by BBR_1, specify an MAB address in bits BA1_31 to BA1_0. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_1 to 0.

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7.3.5 Break Address Mask Register_1 (BAMR_1)

BAMR_1 is a 32-bit readable/writable register. BAMR_1 specifies bits masked in the break address bits specified by BAR_1. BAMR_1 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BAM1_31 BAM1_30 BAM1_29 BAM1_28 BAM1_27 BAM1_26 BAM1_25 BAM1_24 BAM1_23 BAM1_22 BAM1_21 BAM1_20 BAM1_19 BAM1_18 BAM1_17 BAM1_16 BAM1_15 BAM1_14 BAM1_13 BAM1_12 BAM1_11 BAM1_10 BAM1_9 BAM1_8 BAM1_7 BAM1_6 BAM1_5 BAM1_4 BAM1_3 BAM1_2 BAM1_1 BAM1_0 Bit Bit Name Initial Value R/W Description 31 to 0 BAM1_31 to BAM1_0 All 0 R/W Break Address Mask 1 Specify bits masked in the channel-1 break address bits specified by BAR_1 (BA1_31 to BA1_0). 0: Break address bit BA1_n is included in the break condition 1: Break address bit BA1_n is masked and not included in the break condition Note: n = 31 to 0

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7.3.6 Break Bus Cycl e Register_1 (BBR_1)

BBR_1 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions of channel 1. BBR_1 is initialized to H'0000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 UBID1 0 R/W User Break Interrupt Disable 1

Disables or enables user break interrupt requests when a channel-1 break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12, 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CP1[2:0] 000 R/W I- Bus Bus Master Select 1 Select the bus master when the bus cycle of the channel-1 break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). xx1: CPU cycle is included in break conditions x1x: DMAC cycle is included in break conditions 1xx: DTC cycle is included in break conditions

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 176 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD1[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select 1 Select the C bus cycle or I bus cycle as the bus cycle of the channel-1 break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID1[1:0] 00 R/W Instructi on Fetch/Data Access Select 1 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel-1 break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW1[1:0] 00 R/W Read/Write Select 1 Select the read cycle or write cycle as the bus cycle of the channel-1 break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle 1, 0 SZ1[1:0] 00 R/W O perand Size Select 1 Select the operand size of the bus cycle for the channel-1 break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access [Legend] x: Don't care

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7.3.7 Break Address Register_2 (BAR_2)

BAR_2 is a 32-bit readable/writable register. BAR_2 specifies the address used as a break condition in channel 2. The control bits CD2_1 and CD2_0 in the break bus cycle register_2 (BBR_2) select one of the three address buses for a break condition of channel 2. BAR_2 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BA2_31BA2_30BA2_29BA2_28BA2_27BA2_26BA2_25BA2_24BA2_23BA2_22BA2_21BA2_20BA2_19BA2_18BA2_17BA2_16 BA2_15BA2_14BA2_13BA2_12BA2_11BA2_10 BA2_9 BA2_8 BA2_7 BA2_6 BA2_5 BA2_4 BA2_3 BA2_2 BA2_1 BA2_0 Bit Bit Name Initial Value R/W Description 31 to 0 BA2_31 to BA2_0 All 0 R/W Break Address 2 Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions of channel 2. When the C bus and instruction fetch cycle are selected by BBR_2, specify an FAB address in bits BA2_31 to BA2_0. When the C bus and data access cycle are selected by BBR_2, specify an MAB address in bits BA2_31 to BA0_2. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_2 to 0.

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7.3.8 Break Address Mask Register_2 (BAMR_2)

BAMR_2 is a 32-bit readable/writable register. BAMR_2 specifies bits masked in the break address bits specified by BAR_2. BAMR_2 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BAM2_31 BAM2_30 BAM2_29 BAM2_28 BAM2_27 BAM2_26 BAM2_25 BAM2_24 BAM2_23 BAM2_22 BAM2_21 BAM2_20 BAM2_19 BAM2_18 BAM2_17 BAM2_16 BAM2_15 BAM2_14 BAM2_13 BAM2_12 BAM2_11 BAM2_10 BAM2_9 BAM2_8 BAM2_7 BAM2_6 BAM2_5 BAM2_4 BAM2_3 BAM2_2 BAM2_1 BAM2_0 Bit Bit Name Initial Value R/W Description 31 to 0 BAM2_31 to BAM2_0 All 0 R/W Break Address Mask 2 Specify bits masked in the channel-2 break address bits specified by BAR_2 (BA2_31 to BA2_0). 0: Break address bit BA2_n is included in the break condition 1: Break address bit BA2_n is masked and not included in the break condition Note: n = 31 to 0

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7.3.9 Break Bus Cycl e Register_2 (BBR_2)

BBR_2 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions of channel 2. BBR_2 is initialized to H'0000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 UBID2 0 R/W User Break Interrupt Disable 2

Disables or enables user break interrupt requests when a channel-2 break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12, 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CP2[2:0] 000 R/W I- Bus Bus Master Select 2 Select the bus master when the bus cycle of the channel-2 break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). xx1: CPU cycle is included in break conditions x1x: DMAC cycle is included in break conditions 1xx: DTC cycle is included in break conditions

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 180 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD2[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select 2 Select the C bus cycle or I bus cycle as the bus cycle of the channel-2 break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID2[1:0] 00 R/W Instructi on Fetch/Data Access Select 2 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel-2 break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW2[1:0] 00 R/W Read/Write Select 2 Select the read cycle or write cycle as the bus cycle of the channel-2 break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle 1, 0 SZ2[1:0] 00 R/W O perand Size Select 2 Select the operand size of the bus cycle for the channel-2 break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access [Legend] x: Don't care

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7.3.10 Break Address Register_3 (BAR_3)

BAR_3 is a 32-bit readable/writable register. BAR_3 specifies the address used as a break condition in channel 3. The control bits CD3_1 and CD3_0 in the break bus cycle register_3 (BBR_3) select one of the three address buses for a break condition of channel 3. BAR_3 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BA3_31BA3_30BA3_29BA3_28BA3_27BA3_26BA3_25BA3_24BA3_23BA3_22BA3_21BA3_20BA3_19BA3_18BA3_17BA3_16 BA3_15BA3_14BA3_13BA3_12BA3_11BA3_10 BA3_9 BA3_8 BA3_7 BA3_6 BA3_5 BA3_4 BA3_3 BA3_2 BA3_1 BA3_0 Bit Bit Name Initial Value R/W Description 31 to 0 BA3_31 to BA3_0 All 0 R/W Break Address 3 Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions of channel 3. When the C bus and instruction fetch cycle are selected by BBR_3, specify an FAB address in bits BA3_31 to BA3_0. When the C bus and data access cycle are selected by BBR_3, specify an MAB address in bits BA3_31 to BA3_0. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_3 to 0.

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7.3.11 Break Address Mask Register_3 (BAMR_3)

BAMR_3 is a 32-bit readable/writable register. BAMR_3 specifies bits masked in the break address bits specified by BAR_3. BAMR_3 is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W: BAM3_31 BAM3_30 BAM3_29 BAM3_28 BAM3_27 BAM3_26 BAM3_25 BAM3_24 BAM3_23 BAM3_22 BAM3_21 BAM3_20 BAM3_19 BAM3_18 BAM3_17 BAM3_16 BAM3_15 BAM3_14 BAM3_13 BAM3_12 BAM3_11 BAM3_10 BAM3_9 BAM3_8 BAM3_7 BAM3_6 BAM3_5 BAM3_4 BAM3_3 BAM3_2 BAM3_1 BAM3_0 Bit Bit Name Initial Value R/W Description 31 to 0 BAM3_31 to BAM3_0 All 0 R/W Break Address Mask 3 Specify bits masked in the channel-3 break address bits specified by BAR_3 (BA3_31 to BA3_0). 0: Break address bit BA3_n is included in the break condition 1: Break address bit BA3_n is masked and not included in the break condition Note: n = 31 to 0

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7.3.12 Break Bus Cycl e Register_3 (BBR_3)

BBR_3 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions of channel 3. BBR_3 is initialized to H'0000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 UBID3 0 R/W User Break Interrupt Disable 3

Disables or enables user break interrupt requests when a channel-3 break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12, 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CP3[2:0] 000 R/W I- Bus Bus Master Select 3 Select the bus master when the bus cycle of the channel-3 break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). xx1: CPU cycle is included in break conditions x1x: DMAC cycle is included in break conditions 1xx: DTC cycle is included in break conditions

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 184 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD3[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select 3 Select the C bus cycle or I bus cycle as the bus cycle of the channel-3 break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID3[1:0] 00 R/W Instructi on Fetch/Data Access Select 3 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel-3 break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW3[1:0] 00 R/W Read/Write Select 3 Select the read cycle or write cycle as the bus cycle of the channel-3 break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle 1, 0 SZ3[1:0] 00 R/W O perand Size Select 3 Select the operand size of the bus cycle for the channel-3 break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access [Legend] x: Don't care

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 185 of 1692 REJ09B0393-0100

7.3.13 Break Control Register (BRCR)

BRCR sets the following conditions: 1. Specifies whether user breaks are set before or after instruction execution. 2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied. BRCR is a 32-bit readable/writable register that has break condition match flags and bits for setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid (previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRR R / W R / W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Bit: Initial value: R/W: Bit: Initial value: R/W: SCMFC SCMFC SCMFC SCMFC SCMFD SCMFD SCMFD SCMFD

3 PCB3 PCB2 PCB1 PCB0 - - - -

31 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 CKS[1:0] 00 R/W Clock Select These bits specify the pulse width output to the UBCTRG pin when a break condition is satisfied. 00: Pulse width of UBCTRG is one bus clock cycle 01: Pulse width of UBCTRG is two bus clock cycles 10: Pulse width of UBCTRG is four bus clock cycles 11: Pulse width of UBCTRG is eight bus clock cycles

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 186 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

15 SCMFC0 0 R/W C Bus Cycle Condition Match Flag 0

When the C bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 0 does not match 1: The C bus cycle condition for channel 0 matches

14 SCMFC1 0 R/W C Bus Cycle Condition Match Flag 1

When the C bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 1 does not match 1: The C bus cycle condition for channel 1 matches

13 SCMFC2 0 R/W C Bus Cycle Condition Match Flag 2

When the C bus cycle condition in the break conditions set for channel 2 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 2 does not match 1: The C bus cycle condition for channel 2 matches

12 SCMFC3 0 R/W C Bus Cycle Condition Match Flag 3

When the C bus cycle condition in the break conditions set for channel 3 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 3 does not match 1: The C bus cycle condition for channel 3 matches

11 SCMFD0 0 R/W I Bus Cycle Condition Match Flag 0

When the I bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 0 does not match 1: The I bus cycle condition for channel 0 matches

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 187 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

10 SCMFD1 0 R/W I Bus Cycle Condition Match Flag 1

When the I bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 1 does not match 1: The I bus cycle condition for channel 1 matches

9 SCMFD2 0 R/W I Bus Cycle Condition Match Flag 2

When the I bus cycle condition in the break conditions set for channel 2 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 2 does not match 1: The I bus cycle condition for channel 2 matches

8 SCMFD3 0 R/W I Bus Cycle Condition Match Flag 3

When the I bus cycle condition in the break conditions set for channel 3 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 3 does not match 1: The I bus cycle condition for channel 3 matches

7 PCB3 0 R/W PC Break Select 3

Selects the break timing of the instruction fetch cycle for channel 3 as before or after instruction execution. 0: PC break of channel 3 is generated before instruction execution 1: PC break of channel 3 is generated after instruction execution

6 PCB2 0 R/W PC Break Select 2

Selects the break timing of the instruction fetch cycle for channel 2 as before or after instruction execution. 0: PC break of channel 2 is generated before instruction execution 1: PC break of channel 2 is generated after instruction execution

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 188 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 PCB1 0 R/W PC Break Select 1

Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution

4 PCB0 0 R/W PC Break Select 0

Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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7.4 Operation

7.4.1 Flow of the User Break Operation

The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break address is set in a break address regi ster (BAR). The masked address bits are set in a break address mask register (BAMR). The bus break conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set to 00. The relevant break control conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBR, and branch after reading from the last written register. The newly written register values become valid from the instruction at the branch destination. 2. In the case where the break conditions are sa tisfied, the UBC sends a user break interrupt request to the CPU, sets the C bus condition match flag (SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the width set by the CKS1 and CKS0 bits. Setting the UBID bit in BBR to 1 enables external monitoring of the trigger output without requesting user break interrupts. 3. On receiving a user break inte rrupt request signal, the INTC determines its priority. Since the user break interrupt has a priority level of 15, it is accepted when the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are checked, and condition match flags are set if the conditions match. For details on ascertaining the priority, see section 6, Interrupt Controller (INTC). 4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been satisfied. They are set when the conditions match, but are not reset. To use these flags again, write 0 to the corresponding bit of the flags. 5. It is possible that the breaks set in channels 0 to 3 occur around the same time. In this case, there will be only one user break request to the CPU, but these four break channel match flags may be set at the same time.

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 190 of 1692 REJ09B0393-0100 6. When selecting the I bus as the break condition, note as follows:  Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC monitors bus cycles generated by the bus master specified by BBR, and determines the condition match.  I bus cycles (including read fill cycles) resulting from instruction fetches on the C bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles.  The DTC and DMAC only issue data access cycles for I bus cycles.  If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the user break is to be accepted cannot be clearly defined.

7.4.2 Break on Inst ruction Fetch Cycle

1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBR), the break condition is the FAB bus instruction fetch cycle. Whether PC breaks are set before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1. 2. A break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed. This means a break does not occur for instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is not generated until the execution of the first instruction at the branch destination. Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When setting a break condition for break after instruction execution, the instruction set with the break condition is executed and then the break is generated prior to execution of the next instruction. As with pre-execution breaks, a break does not occur with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, the break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the br eak data register (BDR) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an inst ruction fetch cycle, the setting is invalidated.

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7.4.3 Break on Data Access Cycle

1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the virtual address accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the physical address of the data access cycles that are issued by the bus master specified by the bits to select the bus master of the I bus, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 6 in section 7.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.3. Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BAR), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. If the data access cycle is selected, the instru ction at which the break will occur cannot be determined.

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7.4.4 Value of Saved Program Counter

When a break occurs, the address of the instruction from where execution is to be resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a break condition, the instruction at which the break should occur cannot be uniquely determined. 1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved to the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 2. When C bus (FAB)/instruction fetch (after in struction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved to the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition: The address after executing several instructions of the instruction that matched the break condition is saved to the stack.

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7.4.5 Usage Examples

(1) Break Condition Specified for C Bus Instruction Fetch Cycle (Example 1-1)

• Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BRCR = H'00000020 <Channel 0> Address: H'00000404, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) <Channel 1> Address: H'00008010, Address mask: H'00000006 Bus cycle: C bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2)
• Register specifications BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415, BAMR_1 = H'00000000, BBR_1 = H'0054, BRCR = H'00000000 <Channel 0> Address: H'00027128, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (b efore instruction execution)/write/word <Channel 1> Address: H'00031415, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) On channel 0, a user break does not occur since instruction fetch is not a write cycle. On channel 1, a user break does not occur since instruction fetch is performed for an even address.

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 194 of 1692 REJ09B0393-0100 (Example 1-3)

• Register specifications BBR_0 = H'0054, BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_1 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BRCR = H'00000020 <Channel 0> Address: H'00008404, Address mask: H'00000FFF Bus cycle: C bus/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) <Channel 1> Address: H'00008010, Address mask: H'00000006 Bus cycle: C bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. (2) Break Condition Specified for C Bus Data Access Cycle (Example 2-1)
• Register specifications BBR_0 = H'0064, BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_1 = H'006A, BAR_1 = H'000ABCDE, BAMR_1 = H'000000FF, BRCR = H'00000000 <Channel 0> Address: H'00123456, Address mask: H'00000000 Bus cycle: C bus/data access/read (operand size is not included in the condition) <Channel 1> Address: H'000ABCDE, Address mask: H'000000FF Bus cycle: C bus/data access/write/word On channel 0, a user break occurs with longword read from address H'00123456, word read from address H'00123456, or byte read from address H'00123456. On channel 1, a user break occurs when word is written in addresses H'000ABC00 to H'000ABCFE.

Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 195 of 1692 REJ09B0393-0100 (3) Break Condition Specified for I Bus Data Access Cycle (Example 3-1)

• Register specifications BBR_0 = H'0094, BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_1 = H'12A9, BAR_1 = H'00055555, BAMR_1 = H'00000000, BRCR = H'00000000 <Channel 0> Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (opera nd size is not included in the condition) <Channel 1> Address: H'00055555, Address mask: H'00000000 Bus cycle: I bus/data access/write/byte On channel 0, the setting of I bus/instruction fetch is ignored. On channel 1, a user break occurs when the DMAC writes byte data in address H'00055555 on the I bus (write by the CPU does not generate a user break).

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7.5 Usage Notes

1. The CPU can read from or wr ite to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. The UBC cannot monitor access to the C bus and I bus cycles in the same channel. 3. When a user break and another exception occu r at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception with a higher priority occurs, the user break does not occur. 4. Note the following when a break occurs in a delay slot. If a pre-execution break is set at a delay slot instruction, the break is not generated until immediately before execution of the branch destination. 5. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 6. Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 (including user break interrupts) as a break address. 7. Do not set break after instruction executio n for the SLEEP instruction or for the delayed branch instruction where the SLEEP instruction is placed at its delay slot. 8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are placed. If the address of the lower 16 bits is set and a break before instruction execution is set as a break condition, the break is handled as a break after instruction execution.

Section 8 Data Transfer Controller (DTC) DTCHX10A_000020030600 Rev. 1.00 Jun. 26, 2008 Page 197 of 1692 REJ09B0393-0100 Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request.

8.1 Features

• Transfer possible over any number of channels
• Chain transfer Multiple rounds of data transfer is executed in response to a single activation source Chain transfer is only possible after data transfer has been done for the specified number of times (i.e. when the transfer counter is 0)
• Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed
• The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte address space directly
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Write-back skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
• Short address mode specifiable
• Bus release timing selectable: Three types
• DTC activation priority selectable: Two types

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8.2 Register Descriptions

DTC has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 30, List of Registers. These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer is complete, it writes a set of updated transfer information back to the data area. On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the CPU. Table 8.1 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size DTC enable register A DTCE RA R/W H'0000 H'FFFE6000 8, 16 DTC enable register B DTCE RB R/W H'0000 H'FFFE6002 8, 16 DTC enable register C DTCE RC R/W H'0000 H'FFFE6004 8, 16 DTC enable register D DTCE RD R/W H'0000 H'FFFE6006 8, 16 DTC enable register E DTCE RE R/W H'0000 H'FFFE6008 8, 16 DTC control register DTCCR R/W H'00 H'FFFE6010 8 DTC vector base register DTC VBR R/W H'00000000 H'FFFE6014 8, 16, 32 Bus function extending register BSC EHR R/W H'0000 H'FFFE3C1A 8, 16

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8.2.1 DTC Mode Register A (MRA)

MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit: Initial value: R/W: 7654321 0 : Undefined* Bit Bit Name Initial Value R/W Description 7, 6 MD[1:0] Undefined  DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 5, 4 Sz[1:0] Undefined  DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited 3, 2 SM[1:0] Undefined  Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR write-back is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 201 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0  Undefined  Reserved The write value should always be 0. [Legend] x: Don't care

8.2.2 DTC Mode Register B (MRB)

MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit: Initial value: R/W: 7654321 0 CHNE CHNS DISEL DTS DM[1:0] - - : Undefined* Bit Bit Name Initial Value R/W Description

7 CHNE Undefined  DTC Chain Transfer Enable

Specifies the chain transfer. For details, see section 8.5.6, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer

6 CHNS Undefined  DTC Chain Transfer Select

Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0

5 DISEL Undefined  DTC Interrupt Select

When this bit is set to 1, an interrupt request is generated to the CPU every time a data transfer or a block data transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfers ends.

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4 DTS Undefined  DTC Transfer Mode Select

Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area 3, 2 DM[1:0] Undefined  Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0x: DAR is fixed (DAR write-back is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0  Undefined  Reserved The write value should always be 0. [Legend] x: Don't care

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8.2.3 DTC Source Address Register (SAR)

SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. SAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined*

8.2.4 DTC Destination Address Register (DAR)

DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. DAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined*

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8.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 : Undefined*

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8.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time a block of data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 : Undefined*

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8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE)

DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.2. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Bit Bit Name Initial Value R/W Description DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable 15 to 0 Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions]

• When writing 0 to the bit to be cleared after reading 1
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended [Setting condition]
• Writing 1 to the bit after reading 0

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8.2.8 DTC Control Register (DTCCR)

DTCCR specifies transfer information read skip. Bit: Initial value: R/W: 7654321 0 00000000 R R R R/W R/W R R R/(W) * Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* - - - RRS RCHNE - - ERR Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

4 RRS 0 R/W DTC Transfer Information Read Skip Enable

Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match.

3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer

Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer 2, 1  All 0 R Reserved These are read-only bits and cannot be modified.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 208 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 ERR 0 R/(W) * Transfer Stop Flag

Indicates that a DTC address error or NMI interrupt has occurred. If a DTC address error or NMI interrupt occurs while the DTC is active, a DTC address error handling or NMI interrupt handling processing is executed after the DTC has released the bus mastership. The DTC halts after a data transfer or a transfer information writing state depending on the NMI input timing. Note that a writing state is not exact, when the DTC halts after a data transfer. When the data is transferred, set a transfer information once again (except that a read skip is performed). 0: No interrupt has occurred 1: An interrupt has occurred [Clearing condition]

• When writing 0 after reading 1 Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 209 of 1692 REJ09B0393-0100

8.2.9 DTC Vector Base Register (DTCVBR)

DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R / W R / W R / W R / W RRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 31 to 12 All 0 R/W 11 to 0  All 0 R Bits 11 to 0 are always read as 0. The write value should always be 0.

8.2.10 Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other functions. This register should be used to give priority to the DTC transfer or reduce the number of cycles in which the DTC is active. For more details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

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8.3 Activation Sources

The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared.

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8.4 Location of Transfer Information and DTC Vector Table

Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2. Short address mode can be selected by setting the DTSA bit in the bus function extending register (BSCEHR) to 1 only when all DTC transfer sources and destinations are located in the on-chip RAM and on-chip peripheral module areas (see section 9.4.8, Bus Function Extending Register (BSCEHR)). In normal transfer, four longwords should be read as the transfer information; in short address mode, the transfer information is reduced to three longwords and the DTC active period becomes shorter. The DTC reads the start address of transfer information from the vector table according to the activation source, and then reads the transfer information from the start address. Figure 8.3 shows correspondences between the DTC vector address and transfer information. MRA MRB MRA MRB SAR DAR CRA CRB CRA CRB SAR DAR 103 2 MRA MRB MRA MRB SAR DAR CRA CRB CRA CRB SAR DAR Lower addresses Transfer information in short address mode 103 2 The short address mode can be used only for transfer between an on-chip peripheral module and the on-chip RAM because the upper eight bits of SAR and DAR are assumed as all 1s. Reserved (0 write) Reserved (0 write) Lower addresses Transfer information in normal operation Transfer information for one transfer (4 longwords) Transfer information for the 2nd transfer in chain transfer (4 longwords) Transfer information for one transfer (3 longwords) Transfer information for the 2nd transfer in chain transfer (3 longwords) Start address 4 bytes 4 bytes Chain transfer Start address Chain transfer Note: Figure 8.2 Transfer Information on Data Area

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 212 of 1692 REJ09B0393-0100 Transfer information (1) start address Transfer information (2) start address Transfer information (n) start address Vector table Upper: DTCVBR Lower: H'400 + vector number × 4 DTC vector address +4n Transfer information (1) 4 bytes Transfer information (2) Transfer information (n) Figure 8.3 Correspondence between DTC Vector Address and Transfer Information

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 213 of 1692 REJ09B0393-0100 Table 8.2 shows correspondence between the DTC activation source and vector address. Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Transfer Source Transfer Destination Priority IRQ0 64 H'00000500 DTCERA15 Any location * Any location * High IRQ1 65 H'00000504 DTCERA14 Any location * Any location * IRQ2 66 H'00000508 DTCERA13 Any location * Any location * IRQ3 67 H'0000050C DTCERA12 Any location * Any location * IRQ4 68 H'00000510 DTCERA11 Any location * Any location * IRQ5 69 H'00000514 DTCERA10 Any location * Any location * IRQ6 70 H'00000518 DTCERA9 Any location * Any location * External pin IRQ7 71 H'0000051C DTCERA8 Any location * Any location * ADI0 92 H'00000570 DTCERA7 ADDR0 to ADDR3 Any location* ADI1 96 H'00000580 DTCERA6 ADDR4 to ADDR7 Any location* A/D ADI2 100 H'00000590 DTCERA5 ADDR8 to ADDR11 Any location* RCAN RM0_0 106 H'000005A8 DTCERA4 CONTROL0H to CONTROL1L* Any location* CMI0 140 H'00000630 DTCERA3 Any location * Any location * CMT CMI1 144 H'00000640 DTCERA2 Any location * Any location * USRDTCEND 154 H'00000668 DTCERA1 USBEPDR1 Any location * USB USTDTCEND 155 H'0000066C DTCERA0 Any location * USBEPDR2 TGIA_0 156 H'00000670 DTCERB15 Any location * Any location * TGIB_0 157 H'00000674 DTCERB14 Any location * Any location * TGIC_0 158 H'00000678 DTCERB13 Any location * Any location * MTU2_CH0 TGID_0 159 H'0000067C DTCERB12 Any location * Any location * TGIA_1 164 H'00000690 DTCERB11 Any location * Any location * MTU2_CH 1 TGIB_1 165 H'00000694 DTCERB10 Any location * Any location * Low

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 214 of 1692 REJ09B0393-0100 Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Transfer Source Transfer Destination Priority TGIA_2 172 H'000006B0 DTCERB9 Any location * Any location * High MTU2_CH2 TGIB_2 173 H'000006B4 DTCERB8 Any location * Any location * TGIA_3 180 H'000006D0 DTCERB7 Any location * Any location * TGIB_3 181 H'000006D4 DTCERB6 Any location * Any location * TGIC_3 182 H'000006D8 DTCERB5 Any location * Any location * MTU2_CH3 TGID_3 183 H'000006DC DTCERB4 Any location * Any location * TGIA_4 188 H'000006F0 DTCERB3 Any location * Any location * TGIB_4 189 H'000006F4 DTCERB2 Any location * Any location * TGIC_4 190 H'000006F8 DTCERB1 Any location * Any location * TGID_4 191 H'000006FC DTCERB0 Any location * Any location * MTU2_CH4 TCIV_4 192 H'00000700 DTCERC15 Any location * Any location * TGIU_5 196 H'00000710 DTCERC14 Any location * Any location * TGIV_5 197 H'00000714 DTCERC13 Any location * Any location * MTU2_CH5 TGIW_5 198 H'00000718 DTCERC12 Any location * Any location * TGISA_3 204 H'00000730 DTCERC3 Any location * Any location * TGISB_3 205 H'00000734 DTCERC2 Any location * Any location * TGISC_3 206 H'00000738 DTCERC1 Any location * Any location * MTU2S_CH3 TGISD_3 207 H'0000073C DTCERC0 Any location * Any location * TGISA_4 212 H'00000750 DTCERD15 Any location * Any location * TGISB_4 213 H'00000754 DTCERD14 Any location * Any location * TGISC_4 214 H'00000758 DTCERD13 Any location * Any location * TGISD_4 215 H'0000075C DTCERD12 Any location * Any location * MTU2S_CH4 TCISV_4 216 H'00000760 DTCERD11 Any location * Any location * TGISU_5 220 H'00000770 DTCERD10 Any location * Any location * TGISV_5 221 H'00000774 DTCERD9 Any location * Any location * MTU2S_CH5 TGISW_5 222 H'00000778 DTCERD8 Any location * Any location * RXI 230 H'00000798 DTCERD7 ICDRR Any location * IIC3 TXI 231 H'0000079C DTCERD6 Any location * ICDRT Low

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 215 of 1692 REJ09B0393-0100 Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Transfer Source Transfer Destination Priority SSRXI 234 H'000007A8 DTCERD5 SSRDR0 to SSRDR3 Any location* High SSU SSTXI 235 H'000007AC DTCERD4 Any location * SSTDR0 to SSTDR3 RXI4 237 H'000007B4 DTCERD3 SCRDR_4 Any location * SCI4 TXI4 238 H'000007B8 DTCERD2 Any location * SCTDR_4 RXI0 241 H'000007C4 DTCERE15 SCRDR_0 Any location * SCI0 TXI0 242 H'000007C8 DTCERE14 Any location * SCTDR_0 RXI1 245 H'000007D4 DTCERE13 SCRDR_1 Any location * SCI1 TXI1 246 H'000007D8 DTCERE12 Any location * SCTDR_1 RXI2 249 H'000007E4 DTCERE11 SCRDR_2 Any location * SCI2 TXI2 250 H'000007E8 DTCERE10 Any location * SCTDR_2 RXI3 254 H'000007F8 DTCERE9 SCFRDR_3 Any location * SCIF3 TXI3 255 H'000007FC DTCERE8 Any location * SCFTDR_3 Low Notes: 1. The DTCE bits with no corresponding in terrupt are reserved, and the write value should always be 0. 2. An external memory, a memory-mapped ex ternal device, an on-chip memory, or an on- chip peripheral module (except for DTC, BSC, UBC, AUD, FLASH, and DMAC) can be selected as the source or destination. Note that at least either the source or destination must be an on-chip peripheral module; transfer cannot be done among an external memory, a memory-mapped external device, and an on-chip memory. 3. Read to a message control field in mailbox 0 by using a block transfer mode or etc.

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8.5 Operation

There are three transfer modes: normal, repeat, and block. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. When activated, the DTC reads the transfer information stored in the data area and transfers data according to the transfer information. After the data transfer is complete, it writes updated transfer information back to the data area. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 8.3 shows the DTC transfer modes. Table 8.3 DTC Transfer Modes Transfer Mode Size of Data Transferred at One Transfer Request Memory Address Increment or Decrement Transfer Count Normal 1 byte/word/longword Increm ented/decremented by 1, 2, or 4, or fixed 1 to 65536 Repeat* 1 byte/word/longword Incremented/decremented by 1, 2, or 4, or fixed 1 to 256* Block* Block size specified by CRAH (1 to 256 bytes/words/longwords) Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536* Notes: 1. Either source or destinat ion is specified to repeat area. 2. Either source or destinati on is specified to block area. 3. After transfer of the specified transfer co unt, initial state is recovered to continue the operation. 4. Number of transfers of t he specified block size of data Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 8.4 shows a flowchart of DTC operation, and table 8.4 summarizes the conditions for DTC transfers including chain transfer (combinations for performing the second and third transfers are omitted).

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 217 of 1692 REJ09B0393-0100 Start Match & RRS = 1 Not match | RRS = 0 Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Transfer counter = 0 or DISEL = 1 Clear activation source flag End CHNS = 0 Transfer counter = 0 DISEL = 1 Clear DTCER/request an interrupt to the CPU No No No No No Yes Yes Yes Yes Yes Vector number comparison Read DTC vector Figure 8.4 Flowchart of DTC Operation

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 218 of 1692 REJ09B0393-0100 Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included) 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer 0   0 Not 0      Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU 1 0    0   0 Not 0 Ends at 2nd transfer 0   0 0 0   1  Ends at 2nd transfer Interrupt request to CPU 1 1  0 Not 0      Ends at 1st transfer 1 1  1 Not 0      Ends at 1st transfer Interrupt request to CPU 1 1   0 0   0 Not 0 Ends at 2nd transfer 0   0 0 Normal 0   1  Ends at 2nd transfer Interrupt request to CPU

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 219 of 1692 REJ09B0393-0100 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer transfer transfer Interrupt request to CPU 1 0    0   0  Ends at 2nd transfer 0   1  Ends at 2nd transfer Interrupt request to CPU 1 1  0 Not 0      Ends at 1st transfer 1 1  1 Not 0      Ends at 1st transfer Interrupt request to CPU 1 1 0 0 0 * transfer 1 1 0 1 0 * transfer Interrupt request to CPU 1 1 1  0 * 0   0  Ends at 2nd transfer Repeat 0   1  Ends at 2nd transfer Interrupt request to CPU

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 220 of 1692 REJ09B0393-0100 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer Block 0   0 Not 0      Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU 1 0    0   0 Not 0 Ends at 2nd transfer 0   0 0 0   1  Ends at 2nd transfer Interrupt request to CPU transfer 1 1  1 Not 0      Ends at 1st transfer Interrupt request to CPU 1 1  1 0 0   0 Not 0 Ends at 2nd transfer 0   0 0 0   1  Ends at 2nd transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CR AH is written to the CRAL

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8.5.1 Transfer Information Read Skip Function

By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 8.5 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. R RWW Vector read Transfer information read Data transfer Transfer information write Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Internal address DTC activation request DTC request Skip transfer information read Clock (Bφ) Figure 8.5 Transfer Information Read Skip Timing (Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information is Written in 3 Cycles)

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8.5.2 Transfer Information Write-Back Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. Table 8.5 shows the transfer information write-back skip condition and write-back skipped registers. Note that the CRA and CRB are always written back. The write-back of the MRA and MRB are always skipped. Table 8.5 Transfer Information Write-Back Skip Condition and Write-Back Skipped Registers SM1 DM1 SAR DAR 0 0 Skipped Skipped 0 1 Skipped Written back 1 0 Written back Skipped 1 1 Written back Written back

8.5.3 Normal Transfer Mode

In normal transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in normal transfer mode. Table 8.6 Register Function in Normal Transfer Mode Register Function Written Back Value SAR Source address Incremented/decremented/fixed * DAR Destination address Incremented/decremented/fixed * CRA Transfer count A CRA − 1 CRB Transfer count B Not updated Note: * Transfer information write-back is skipped.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 223 of 1692 REJ09B0393-0100 SAR Transfer source data area DAR Transfer Transfer destination data area Figure 8.6 Memory Map in Normal Transfer Mode

8.5.4 Repeat Transfer Mode

In repeat transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in repeat transfer mode.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 224 of 1692 REJ09B0393-0100 Table 8.7 Register Function in Repeat Transfer Mode Written Back Value Register Function CRAL is not 1 CRAL is 1 SAR Source address Incremented/decremented/fixed * DTS = 0: Incremented/ decremented/fixed* DTS = 1: SAR initial value DAR Destination address Incremented/decremented/fixed * DTS = 0: DAR initial value DTS = 1: Incremented/ decremented/fixed* CRAH Transfer count storage CRAH CRAH CRAL Transfer count A CRAL − 1 CRAH CRB Transfer count B Not updated Not updated Note: * Transfer information write-back is skipped. SAR Transfer source data area (specified as repeat area) DAR Transfer Transfer destination data area Figure 8.7 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area)

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8.5.5 Block Transfer Mode

In block transfer mode, data are transferred in block units in response to a single activation request. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When transfer of one block of data ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) for the area specified as the block area are initialized. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in block transfer mode. Table 8.8 Register Function in Block Transfer Mode Register Function Written Back Value SAR Source address DTS = 0: Incremented/decremented/fixed* DTS = 1: SAR initial value DAR Destination address DTS = 0: DAR initial value DTS = 1: Incremented/decremented/fixed* CRAH Block size storage CRAH CRAL Block size counter CRAH CRB Block transfer counter CRB − 1 Note: * Transfer information write-back is skipped.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 226 of 1692 REJ09B0393-0100 Transfer source data area Transfer destination data area (specified as block area) Block area DAR SAR Transfer1st block Nth block Figure 8.8 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area)

8.5.6 Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 227 of 1692 REJ09B0393-0100 Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer information stored in user area Data area Transfer source data (1) Transfer destination data (1) Transfer source data (2) Transfer destination data (2) Transfer information start address Vector table DTC vector address Figure 8.9 Operation of Chain Transfer

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 228 of 1692 REJ09B0393-0100

8.5.7 Operation Timing

Figures 8.10 to 8.15 show the DTC operation timings. RWInternal address Vector read Transfer information read Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. DTC activation request DTC request Clock (Bφ) Figure 8.10 Example of DTC Operation Timing: Normal Transfer Mode or Repeat Transfer Mode (Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information is Written in 3 Cycles) RR WWInternal address Vector read Transfer information read Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. DTC activation request DTC request Clock (Bφ) Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2 (Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information is Written in 3 Cycles)

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8.5.8 Number of DTC Execution Cycles

Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the number of cycles required for each execution. Table 8.9 DTC Execution Status Mode Vector Read I Transfer Information Read J Transfer Information Write K Data Read L Data Write M Internal Operation N Normal 1 0 * 4 0 * 3 2 * 1 * 1 1 1 0 * Repeat 1 0 * 4 0 * 3 2 * 1 * 1 1 1 0 * Block transfer 1 0 * 4 0 * 3 2 * 1 * 1•P 1P 1 0 * [Legend] P: Block size (CRAH and CRAL value) Notes: 1. When transfer information read is skipped 2. When the SAR or DAR is in fixed mode 3. When the SAR and DAR are in fixed mode

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 232 of 1692 REJ09B0393-0100 Table 8.10 Number of Cycles Required for Each Execution State Object to be Accessed On-Chip RAM * On-Chip ROM * On-Chip I/O Registers External Device * Bus width 32 bits 32 bits 8 bits * 16 bits 8 bits 16 bits 32 bits Access cycles 1B φ to 3Bφ* 3B φ to 4Iφ + 3Bφ* 2Pφ 2P φ 2B φ 2B φ 2B φ Vector read SI 1B φ to 3Bφ* 3B φ to 4Iφ + 3Bφ*   9B φ 5B φ 3B φ Transfer information read S J 1Bφ to 3Bφ*    9B φ 5B φ 3B φ Exe- cution status Transfer information write S k 1Bφ to 3Bφ*    2B φ* 2B φ* 2B φ* Byte data read S L 1B φ to 3Bφ*  1B φ + 2Pφ* 1B φ + 2Pφ* 3B φ 3B φ 3B φ Word data read S L 1B φ to 3Bφ*   1B φ + 2Pφ* 5B φ 3B φ 3B φ Longword data read S L 1B φ to 3Bφ*   1B φ + 2Pφ* 9B φ 5B φ 3B φ Byte data write S M 1B φ to 3Bφ*  1B φ + 2Pφ* 1B φ + 2Pφ* 2B φ* 2B φ* 2B φ* Word data write S M 1B φ to 3Bφ*   1B φ + 2Pφ* 2B φ* 2B φ* 2B φ* Longword data write S M 1B φ to 3Bφ*   1B φ + 2Pφ* 2B φ* 2B φ* 2B φ* Internal operation S N 1 Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of Iφ:Bφ. Read Write I φ:Bφ = 1:1 3B φ 2B φ I φ:Bφ = 1:1/2 2B φ 2B φ I φ:Bφ = 1:1/4 2B φ 2B φ I φ:Bφ = 1:1/8 1B φ 1B φ 2. Values for on-chip ROM. Number of cycles varies depending on the ratio of Iφ:Bφ. Read Write I φ:Bφ = 1:1 4I φ + 3Bφ 4I φ + 3Bφ I φ:Bφ = 1:1/2 4I φ + 3Bφ 4I φ + 3Bφ I φ:Bφ = 1:1/4 4I φ + 3Bφ 4I φ + 3Bφ I φ:Bφ = 1:1/8 3B φ 3B φ

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 233 of 1692 REJ09B0393-0100 3. The values in the table are those for t he fastest case. Depending on the state of the internal bus, replace 1Bφ by 1Pφ in a slow case. 4. Value for I C2. 5. Values are different depending on the BSC register setting. The values in the table are the sample for the case with no wait cycles and the WM bit in CSnWCR = 1. 6. Values are different depending on the bus state. The number of cycles increases when many external wait cycles are inserted in the case where writing is frequently executed, such as block transfer, and when the external bus is in use because the write buffer cannot be used efficiently in such cases. For details on the write buffer, see section 9.5.12 (2), Access from the Side of the LSI Internal Bus Master. The number of execution cycles is calculated from the formula below. Note that Σ means the sum of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in transfer information plus 1). Number of execution cycles = I • SI + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN

8.5.9 DTC Bus Release Timing

The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, NOP execution after vector read, transfer information read, a single data transfer, or transfer information write-back. The DTC does not release the bus mastership during transfer information read, a single data transfer, or write-back of transfer information. The bus release timing can be specified through the bus function extending register (BSCEHR). For details see section 9.4.8, Bus Function Extending Register (BSCEHR). The difference in bus release timing according to the register setting is summarized in table 8.11. Settings other than shown in the table are prohibited. The value of BSCEHR must not be modified while the DTC is active. Figure 8.16 is a timing chart showing an example of bus release timing.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 234 of 1692 REJ09B0393-0100 Table 8.11 DTC Bus Release Timing Bus Function Extending Register (BSCEHR) Setting Bus Release Timing (O: Bus must be released; x: Bus is not released) After Write-Back of Transfer Information DTLOCK DTBST After Vector Read After Transfer Information Read After a Single data Transfer Normal Transfer Continuous Transfer Setting 1 0 0 × × × O O Setting 3 1 0 O O O O O Note: * The following restrictions apply to setting 2.

• The clock setting through the frequency control register (FROCR) must be Iφ : Bφ : Pφ =
• The vector information must be st ored in the on-chip ROM or RAM.
• The transfer information must be stored in the on-chip RAM.
• Transfer must be between the on-chip RAM and an on-chip peripheral module or between the external memory and an on-chip peripheral module.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 235 of 1692 REJ09B0393-0100 Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined. Clock (Bφ) Vector read DTC request DTC activation request 1 DTC activation request 2 Vector read Transfer information read Data transfer Transfer information write Bus release timing (setting 3) Bus release timing (setting 1) Bus release timing (setting 2) : Indicates bus mastership release timing. Internal address : Bus mastership is only released for the external access request from the CPU. RW Transfer information read Data transfer Transfer information write RW Figure 8.16 Example of DTC Operation Timing: Conflict of Two Activation Requests in Normal Transfer Mode (Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information is Written in 3 Cycles)

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 236 of 1692 REJ09B0393-0100

8.5.10 DTC Activation Priority Order

If multiple DTC activation requests are generated while the DTC is inactive, whether to start the DTC transfer from the first activation request or according to the DTC activation priority can be selected through the DTPR bit setting in the bus function extending register (BSCEHR). If multiple activation requests are generated while the DTC is active, transfer is performed according to the DTC activation priority. Figure 8.17 shows an example of DTC activation according to the priority. Transfer is started for the first activation request Transfer is performed according to the priority Transfer is performed according to the priority Other than DTC DTC (request 3) DTC (request 1) DTC (request 2)Internal bus DTC activation request 1 (High priority) DTC activation request 2 (Medium priority) DTC activation request 3 (Low priority) DTC activation request 1 (High priority) DTC activation request 2 (Medium priority) DTC activation request 3 (Low priority) Priority determination Transfer is started according to the priority Other than DTC DTC (request 1) DTC (request 2) DTC (request 3)Internal bus Priority determination Priority determination (1) DTPR = 0 (2) DTPR = 1 DTC is inactive DTC is inactive DTC is active DTC is active Figure 8.17 Example of DTC Activation According to Priority

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8.6 DTC Activation by Interrupt

The procedure for using the DTC with interrupt activation is shown in figure 8.18. Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 8.2, Register Descriptions. For details on location of transfer information, see section 8.4, Location of Transfer Information and DTC Vector Table. Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 8.4, Location of Transfer Information and DTC Vector Table. Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecu- tively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 8.2. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 8.2, Register Descriptions and figure 8.4. DTC activation by interrupt Clear RRS bit in DTCCR to 0 Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB) Set starts address of transfer information in DTC vector table Set RRS bit in DTCCR to 1 Set corresponding bit in DTCER to 1 Set enable bit of interrupt request for activation source to 1 Interrupt request generated DTC activated Corresponding bit in DTCER cleared or CPU interrupt requested Transfer end [1] [2] [3] [4] [5] [6] [7] [1] [2] [3] [4] [5] [6] [7] Determine clearing method of activation source Clear activation source Clear corresponding bit in DTCER Figure 8.18 DTC Activation by Interrupt

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8.7 Examples of Use of the DTC

8.7.1 Normal Transfer Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer informatio n for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Se t the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.

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8.7.2 Chain Transfer when Transfer Counter = 0

By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.19 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set rep eat transfer mode (with the source side as the repeat area) for re- setting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU.

Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 240 of 1692 REJ09B0393-0100 1st data transfer information 2nd data transfer information Transfer information located on the on-chip memory Chain transfer (counter = 0) Input circuit Input buffer Upper 8 bits of DAR Figure 8.19 Chain Transfer when Transfer Counter = 0

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8.8 Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or on completion of a single data transfer or a single block data transfer with the DISEL bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller. For details, refer to section 6.9, Data Transfer with Interrupt Request Signals.

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8.9 Usage Notes

8.9.1 Module Standby Mode Setting

Operation of the DTC can be disabled or enabled using the standby control register. The initial setting is for operation of the DTC to be disabled. DTC operation is disabled in module standby mode but register access is available. However, do not place the DTC in module standby mode while it is active. Before entering software standby mode or module standby mode, all DTCER registers must be cleared. For details, refer to section 28, Power-Down Modes.

8.9.2 On-Chip RAM

Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must not be cleared to 0.

8.9.3 DTCE Bit Setting

To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it. While DTC transfer is in progress, do not modify the DTCE bits.

8.9.4 Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI, SSU, RCAN-ET, SCIF, IIC3, and A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the relevant register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained.

8.9.5 Transfer Information Start Address, Source Address, and Destination Address

The transfer information start address to be specified in the vector table should be address 4n. Transfer information should be placed in on-chip RAM or external memory space.

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8.9.6 Access to DTC Registers through DTC

Do not access the DMAC or DTC registers by using DTC operation. Do not access the DTC registers by using DMAC operation.

8.9.7 Notes on IRQ Interrupt as DTC Activation Source

• When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request an interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be held low until the CPU accepts the interrupt.

8.9.8 Note on SCI or SCIF as DTC Activation Sources

When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag in the SCI must not be used as the transfer end flag. When the TXIF interrupt from the SCIF is specified as a DTC activation source, the TEND flag in the SCIF must not be used as the transfer end flag.

8.9.9 Clearing Interrupt Source Flag

The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt handler in the same way as for general interrupt source flags. For details, refer to section 6.10, Usage Note.

8.9.10 Conflict between NMI Interrupt and DTC Activation

When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated. It takes 3Bφ + 2Pφ for checking DTC stop by the NMI, 3Bφ + 2Pφ for checking DTC activation by the IRQ, and 1Bφ + 1Pφ to 4Bφ + 1Pφ for checking DTC activation by the peripheral module.

8.9.11 Note on USB as DTC Activation Sources

To generate a CPV interrupt when a DTC transfer activated by the USB is completed, refer to the procedure described in section 25, USB Function Module.

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8.9.12 Operation when a DTC Activation Request has been Cancelled

Once DTC has accepted an activation request, the next activation request will not be accepted until the sequence of the DTC transaction has finished up to the end of write-back.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 245 of 1692 REJ09B0393-0100 Section 9 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.

9.1 Features

The BSC has the following features. 1. External address space  A maximum of 64 Mbytes for each of areas CS0 to CS7.  Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clock synchronous or asynchronous), MPX-I/O, and SDRAM for each address space.  Can select the data bus width (8, 16, or 32 bits) for each address space.  Controls insertion of wait cycles for each address space.  Controls insertion of wait cycles for each read access and write access.  Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different spaces), read-read (in same space/different spaces), the first cycle is a write access. 2. Normal space interface  Supports the interface that can directly connect to the SRAM. 3. Burst ROM interface (clock asynchronous)  High-speed access to the ROM that has the page mode function. 4. MPX-I/O interface  Can directly connect to a peripheral LSI that needs an address/data multiplexing. 5. SDRAM interface  Can set the SDRAM in up to two areas.  Multiplex output for row address/column address.  Efficient access by single read/single write.  High-speed access in bank-active mode.  Supports an auto-refresh and self-refresh.  Supports low-frequency and power-down modes.  Issues MRS and EMRS commands.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 246 of 1692 REJ09B0393-0100 6. SRAM interface with byte selection  Can connect directly to a SRAM with byte selection. 7. Burst ROM interface (clock synchronous)  Can connect directly to a ROM of the clock-synchronous type. 8. Bus arbitration  Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 9. Refresh function  Supports the auto-refresh and self-refresh functions.  Specifies the refresh interval using the refresh counter and clock selection.  Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 10. Usage as interval timer for refresh counter  Generates an interrupt request at compare match. Figure 9.1 shows a block diagram of the BSC.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 247 of 1692 REJ09B0393-0100 CMNCR CS0WCR CS7WCR CS0BCR CS7BCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller Wait controller Area controller Internal bus Memory controller Refresh controller [Legend] Module bus BSC CS0 to CS7 REFOUT WAIT MD1, MD0 A25 to A0*, D31 to D0* BACK BREQ BS, RD/WR, RD, WRx, RASL, RASU*, CASL, CASU*, CKE, DQMxx, AH, CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0 to 7) CSn space bus control register (n = 0 to 7) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register . . . . . . . . . . . . . . . Note * A20 to A0, D15 to D0, RASL, and CASL are available only in the SH7285 and the SH7243. Figure 9.1 Block Diagram of BSC

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 248 of 1692 REJ09B0393-0100

9.2 Input/Output Pins

Table 9.1 shows the pin configuration of the BSC. Table 9.1 Pin Configuration Name I/O Function A25 to A0 Output Address bus (A20 to A0 in SH7285 and SH7243) D31 to D0 I/O Data bus (D15 to D0 in SH7285 and SH7243) BS Output Bus cycle start CS0 to CS7 Output Chip select RD/WR Output Read/write Connects to WE pins when SDRAM or SRAM with byte selection is connected. RD Output Read pulse signal (read data output enable signal) Functions as a strobe signal for indicating memory read cycles when PCMCIA is used. AH Output A signal used to hold an address when MPX-I/O is in use WRHH/DQMUU Output Indicates t hat D31 to D24 are being written to (only in SH7286). Connected to the byte select signal when SRAM with byte selection is connected. Functions as the select signals for D31 to D24 when SDRAM is connected. WRHL/DQMUL Output Indicates that D23 to D26 are being written to (only in SH7286). Connected to the byte select signal when SRAM with byte selection is connected. Functions as the select signals for D23 to D26 when SDRAM is connected. WRH/DQMLU Output Indicates that D 15 to D8 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D15 to D8 when SDRAM is connected.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 249 of 1692 REJ09B0393-0100 Name I/O Function WRL/DQMLL Output Indica tes that D7 to D0 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D7 to D0 when SDRAM is connected. RASL, RASU Output Connected to RAS pin when SDRAM is connected (RASU is available only in the SH7286). CASL, CASU Output Connected to CAS pin when SDRAM is connected (CASU is available only in the SH7286). CKE Output Connected to CKE pin when SDRAM is connected. WAIT Input External wait input BREQ Input Bus request input BACK Output Bus enable output REFOUT Output Refresh request output in bus-released state MD0 Input Selects bus width of area 0. 8 or 16 bits: SH7285 and SH7243 16 or 32 bits: SH7286 It also selects the on-chip ROM enabled or disabled mode and external bus access enabled or disabled mode.

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9.3 Area Overview

9.3.1 Address Map

In the architecture, this LSI has a 32-bit address space, which is divided into external address space and on-chip spaces (on-chip ROM, on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 251 of 1692 REJ09B0393-0100 Table 9.2 Address Map in On-Chip ROM-Enabled Mode Address Space Memory to be Connected Size H'0000 0000 to H'000F FFFF On-chip ROM On-chip ROM 256 Kbytes (SH7243)

768 Kbytes

(SH7285)

1 Mbytes

(SH7286) H'0070 0000 to H'01FF FFFF Other Reserved area  H'0200 0000 to H'03FF FFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous)

32 Mbytes

H'0400 0000 to H'07FF FFFF CS1 Normal space, SRAM with byte selection 64 Mbytes H'0800 0000 to H'0BFF FFFF CS2 Normal space, SRAM with byte selection, SDRAM

64 Mbytes

H'0C00 0000 to H'0FFF FFFF CS3 Normal sp ace, SRAM with byte selection, SDRAM H'1000 0000 to H'13FF FFFF CS4 Normal space, SRAM with byte selection, burst ROM (asynchronous) H'1400 0000 to H'17FF FFFF CS5 Normal space, SRAM with byte selection, MPX-I/O H'1800 0000 to H'1BFF FFFF CS6 Normal space, SRAM with byte selection 64 Mbytes H'1C00 0000 to H'1FFF FFFF CS7 Normal space, SRAM with byte selection 64 Mbytes H'2000 0000 to H'FFF7 FFFF Other Reserved area  H'FFF8 0000 to H'FFFB FFFF Other On-chip RAM, reserved area *  H'FFFC 0000 to H'FFFF FFFF Other On-chip peripheral modules, reserved area *  Note: * For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 30, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 252 of 1692 REJ09B0393-0100 Table 9.3 Address Map in On -Chip ROM-Disabled Mode Address Space Memory to be Connected Size H'0000 0000 to H'03FF FFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) H'0400 0000 to H'07FF FFFF CS1 Normal space, SRAM with byte selection 64 Mbytes H'0800 0000 to H'0BFF FFFF CS2 Normal space, SRAM with byte selection, SDRAM H'0C00 0000 to H'0FFF FFFF CS3 Normal sp ace, SRAM with byte selection, SDRAM H'1000 0000 to H'13FF FFFF CS4 Normal space, SRAM with byte selection, burst ROM (asynchronous) H'1400 0000 to H'17FF FFFF CS5 Normal space, SRAM with byte selection, MPX-I/O H'1800 0000 to H'1BFF FFFF CS6 Normal space, SRAM with byte selection 64 Mbytes H'1C00 0000 to H'1FFF FFFF CS7 Normal space, SRAM with byte selection 64 Mbytes H'2000 0000 to H'FFF7 FFFF Other Reserved area  H'FFF8 0000 to H'FFFB FFFF Other On-chip RAM, reserved area *  H'FFFC 0000 to H'FFFF FFFF Other On-chip peripheral modules, reserved area *  Note: * For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM. For the on-chip I/O register space, access the addresses shown in section 30, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 253 of 1692 REJ09B0393-0100

9.3.2 Setting Operating Modes

This LSI can set the following modes of operation at the time of power-on reset using the external pins.

• Single-Chip Mode/External Bus Accessible Mode In single-chip mode, no access is made to the external bus, and the LSI is activated by the on- chip ROM program upon a power-on reset. The BSC module enters the module standby state to reduce power consumption. The address, data, bus control pins used in external bus accessible mode can be used as the port function pins in single-chip mode.
• On-Chip ROM-Enabled Mode/On-Chip ROM-Disabled Mode In on-chip ROM-enabled mode, since the first half of area 0 is allocated to the on-chip ROM, the LSI can be activated by the on-chip ROM program upon a power-on reset. The second half of area 0 is the external memory space. In on-chip ROM-disabled mode, the LSI is activated by the program stored in the external memory allocated to area 0. The second half of area 0 is the external memory space. In this case, a ROM is assumed for the external memory of area 0. Therefore, minimum functions are provided for the pins including address bus, data bus, CS0, and RD. Although BS, RDWR, WEn, and other pins are shown in the examples of access waveforms in this section, these are examples when pin settings are performed by the pin function controller. For details, see section 23, Pin Function Controller (PFC). Do not perform any operation except for area 0 read access until the pin settings by the program is completed.
• Initial Settings of Data Bus Widths for Areas 0 to 7 The initial settings of data bus widths of areas 0 to 7 can be selected at a time as 16 bits or 32 bits in the SH7286 or 8 bits or 16 bits in the SH7285 and SH7243. In on-chip ROM-disabled mode, the data bus width of area 0 cannot be changed from its initial setting after a power-on reset, but the data bus widths of areas 1 to 7 can be changed by register settings in the program. In on-chip ROM-enabled mode, all the data bus widths of areas 0 to 7 can be changed by register settings in the program. Note that data bus widths will be restricted depending on memory types.

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• Initial Settings of Big Endian / Little Endian The initial settings of byte-data alignment of areas 1 to 7 can be selected as big endian or little endian. In on-chip ROM-disabled mode, the endianness of area 0 cannot be changed from its initial setting after a power-on reset, but the endianness of areas 1 to 7 can be changed by register settings in the program. In on-chip ROM-enabled mode, all the endianness of areas 1 to 7 can be changed by register settings in the program. Area 0 cannot be selected as little endian. Since the instruction fetch is mixed with the 32- and 16-bit access and the allocation to the little endian area is difficult, the instruction must be executed within the big endian area. For details of mode settings, see section 3, MCU Operating Modes.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 255 of 1692 REJ09B0393-0100

9.4 Register Descriptions

The BSC has the following registers. Do not access spaces other than area 0 until settings of the connected memory interface are completed. Table 9.4 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Common control register CMNCR R/W H'00001010 H'FFFC0000 32 CSn space bus control register CSnBCR R/W H'36DB0400 * H'FFFC 0004 to H'FFFC 0020 CSn space wait control register CSnWCR R/W H'00000500 H'FFFC0028 to H'FFFC 0044 SDRAM control register SDCR R/W H'00000000 H'FFFC004C 32 Refresh timer control/status register RTCSR R/W H'00000000 H'FFFC0050 32 Refresh timer counter RTCNT R/W H'00000000 H'FFFC0054 32 Refresh time constant register RTCOR R/W H'00000000 H'FFFC0058 32 Bus function extending register BSCEHR R/W H'0000 H'FFFE3C1A 16 Note: * Value when selecting the16-bit bus width with the external pin (MD0). When selecting the 32-bit bus width, the initial value will be H'36DB 0600 and when selecting the 8-bit bus width, the initial value will be H'36DB 0200.

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9.4.1 Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. This register is initialized to H'00001010 by a power-on reset and retains the value by a manual reset and in software standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0001000000010000 R R R R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W ---- B LOCK DPRTY[1:0] DMAIW[2:0] DMA IWA -- HIZ CKIO HIZ MEM HIZ CNT Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12  1 R Reserved This bit is always read as 1. The write value should always be 1.

11 BLOCK 0 R/W Bus Lock

Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. 10, 9 DPRTY[1:0] 00 R/W DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer. 01: Accepts a refresh request but does not accept a bus mastership request during DMA burst transfer. 10: Accepts neither a refresh request nor a bus mastership request during DMA burst transfer. 11: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 257 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 8 to 6 DMAIW[2:0] 000 R/W Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted

5 DMAIWA 0 R/W Method of inserting wait states between access cycles

when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous access cycles to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK 4  1 R Reserved This bit is always read as 1. The write value should always be 1.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 258 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 3  0 R Reserved These bits are always read as 0. The write value should always be 0.

2 HIZCKIO 0 R/W High-Z CK Control

Specifies the state in CK standby mode and when bus mastership is released. 0: CK is in high impedance state in standby mode and bus-released state. 1: CK is driven in standby mode and bus-released state.

1 HIZMEM 0 R/W High-Z Memory Control

Specifies the pin state in standby mode for A25 to A0, BS, CSn, RD/WR, WEn/DQMxx, AH, and RD. At bus- released state, these pins are in high-impedance state regardless of the setting value of the HIZMEM bit. 0: High impedance in standby mode. 1: Driven in standby mode

0 HIZCNT 0 R/W High-Z Control

Specifies the state in standby mode and bus-released state for CKE, RASL, CASL, RASU, and CASU. 0: CKE, RASL, CASL, RASU, and CASU are in high- impedance state in standby mode and bus-released state. 1: CKE, RASL, CASL, RASU, and CASU are driven in standby mode and bus-released state.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 259 of 1692 REJ09B0393-0100

9.4.2 CSn Space Bus Control Regi ster (CSnBCR) (n = 0 to 7)

CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a space, data bus width of an area, endian, and the number of waits between access cycles. This register is initialized to H'36DB0x00 by a power-on reset and retains the value by a manual reset and in software standby mode. Do not access external memory other than area 0 until CSnBCR initial setting is completed. Idle cycles may be inserted even when they are not specified. For details, see section 9.5.10, Wait between Access Cycles. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0011011011011011 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 000000 * 1* 000000000 R R/W R/W R/W R/W R/W R/W R R R R R R R R R - IWW[2:0] IWRWD[2:0] IWRWS[2:0] IWRRD[2:0] IWRRS[2:0] - TYPE[2:0] ENDIAN BSZ[1:0] - - - - - - - - - Bit Bit Name Initial Value R/W Description 31  0 R Reserved This bit is always read as 0. The write value should always be 0. 30 to 28 IWW[2:0] 011 R/W Idle Cycles between Write-Read Cycles and Write- Write Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 260 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 27 to 25 IWRWD[2:0] 011 R/W Idle C ycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 24 to 22 IWRWS[2:0] 011 R/W Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 261 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 21 to 19 IWRRD[2:0] 011 R/W Idle Cycl es for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 to 16 IWRRS[2:0] 011 R/W Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 262 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 14 to 12 TYPE[2:0] 000 R/W S pecify the type of memory connected to a space. 000: Normal space 001: Burst ROM (clock asynchronous) 010: MPX-I/O 011: SRAM with byte selection 100: SDRAM 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Burst ROM (clock synchronous) For details of memory type in each area, see tables 9.2 and 9.3.

11 ENDIAN 0 R/W Endian Select

Specifies data alignment in a space. 0: Big endian 1: Little endian

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 263 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10, 9 BSZ[1:0] 01 * R/W Data Bus Width Specification Specify the data bus widths of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size (only in SH7286, Setting prohibited both in the SH7285 and SH7243) For MPX-I/O, selects bus width by address. Notes: 1. If area 5 is specified as MPX-I/O, the bus width can be specified as 8 bits or 16 bits by the address according to the SZSEL bit in CS5WCR by specifying the BSZ[1:0] bits to 11. The fixed bus width can be specified as 8 bits or 16 bits. 2. The initial data bus width for areas 0 to 7 is specified by external pins. In on-chip ROM-disabled mode, writing to the BSZ1 and BSZ0 bits in CS0BCR is ignored, but the bus width settings in CS1BCR to CS7BCR can be modified. In on-chip ROM-enabled mode, the bus width settings in CS0BCR to CS7BCR can be modified. 3. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as 16 bits only. 4. If area 0 or 4 is specified as clock- synchronous burst ROM space, the bus width can be specified as 16 bits only. 8 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 264 of 1692 REJ09B0393-0100 Note: * Details of Initial value of this bit are shown below according to the product and MCU operating mode. Mode SH7243 SH7285 SH7286 Mode 0 10 10 11 Mode 1 01 01 10 Mode 2 01 01 01 Mode 3 01 01 01

9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7)

CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. CSnWCR is initialized to H'00000500 by a power-on reset and retains the value by a manual reset and in software standby mode. (1) Normal Space, SRAM with Byte Selection, MPX-I/O

• CS0WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000010100000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21  * All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 265 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

20 BAS * 0 R/W Byte Access Selection when SRAM with Byte

Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 13  * All 0 R/W Reserved Set these bits to 0 when the interface for normal space or SRAM with byte selection is used. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS0 Assertion to RD, Wen Assertion Specify the number of delay cycles from address and CS0 assertion to RD and Wen assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 266 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 267 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS0 Negation Specify the number of delay cycles from RD and WEn negation to address and CS0 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Note * To connect the burst ROM to the CS0 spac e and switch to the burst ROM interface after activation in ROM-disabled mode, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits 20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the reserved bits other than above bits.

• CS1WCR, CS7WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRR R / W R R / W R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

20 BAS 0 R/W SRAM with Byte Se lection Byte Access Select

Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 268 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 269 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 270 of 1692 REJ09B0393-0100

• CS2WCR, CS3WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRR R / W RRRR 0000010100000000 R R R R R R/W R/W R/W R/W R/W R R R R R R Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 271 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 272 of 1692 REJ09B0393-0100

• CS4WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRR R / W R R / W R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 273 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 274 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

• CS5WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 R R R R R R R R R R R/W R/W R R/W R/W R/W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W BAS - WW[2:0] Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 275 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description MPX-I/O Interface Bus Width Specification Specifies an address to select the bus width when the BSZ[1:0] of CS5BCR are specified as 11. This bit is valid only when area 5 is specified as MPX-I/O. Always set this bit to 0 in the SH7285 and SH7243. 0: Selects the bus width by address A14 1: Selects the bus width by address A21 The relationship between the SZSEL bit and bus width selected by A14 or A21 are summarized below. SZSEL A14 A21 Bus Width 0 0 Not affected 8 bits 0 1 Not affected 16 bits

1 Not affected 0 8 bits

1 Not affected 1 16 bits

21 SZSEL 0 R/W

MPXW 0 R/W MPX-I/O Interface Address Wait This bit setting is valid only when area 5 is specified as MPX-I/O. Specifies the address cycle insertion wait for MPX-I/O interface. 0: Inserts no wait cycle 1: Inserts 1 wait cycle BAS 0 R/W SRAM with Byte Selection Byte Access Select This bit setting is valid only when area 5 is specified as SRAM with byte selection. Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 276 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS5 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS5 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 277 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 278 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS5 Negation Specify the number of delay cycles from RD and WEn negation to address and CS5 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

• CS6WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRR R / W RRRR 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 279 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS6 Assertion to RD, WEn Assertion Specify the number of delay cycles from address, CS6 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

6 WN 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid. The specification of this bit is valid even when the number of access wait cycles is 0. 0: The external wait input is valid 1: The external wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 280 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Number of Delay Cycles from RD, WEn Negation to Address, CS6 Negation Specify the number of delay cycles from RD, WEn negation to address, and CS6 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles (2) Burst ROM (Clo ck Asynchronous)

• CS0WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRR R / W R / W RR R / W R / W 0000010100000000 R R R R R R/W R/W R/W R/W R/W R R R R R R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 281 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width BST[1:0] Burst count 00 16 burst × one time 8 bits 01 4 burst × four times 00 8 burst × one time 01 2 burst × four times 16 bits 10 4-4 or 2-4-2 burst 21, 20 BST[1:0] 00 R/W 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 282 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 283 of 1692 REJ09B0393-0100

• CS4WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRR R / W R / W RR R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width BST[1:0] Burst count 00 16 burst × one time 8 bits 01 4 burst × four times 00 8 burst × one time 01 2 burst × four times 16 bits 10 4-4 or 2-4-2 burst 21, 20 BST[1:0] 00 R/W 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 284 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 285 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 286 of 1692 REJ09B0393-0100 (3) SDRAM *

• CS2WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0000010100000000 RRRRRRR R / W R / W RRRRRRR Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10  1 R Reserved This bit is always read as 1. The write value should always be 1. 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A2CL[1:0] 10 R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * If only one area is connected to the SDRAM, s pecify area 3. In this case, specify area 2 as normal space or SRAM with byte selection.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 287 of 1692 REJ09B0393-0100

• CS3WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0000010100000000 R R/W R/W R R/W R/W R R/W R/W R R R/W R/W R R/W R/W Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. - WTRP[1:0] * WTRCD[1:0]* TRWL[1:0]* WTRC[1:0]*- - A3CL[1:0] - - - Bit Bit Name Initial Value R/W Description 31 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14, 13 WTRP[1:0] * 00 R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below.
• From the start of auto-precharge and issuing of ACTV command for the same bank
• From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank
• Till entering power-down mode or deep power- down mode
• From the issuing of PALL command to issuing REF command in auto-refresh mode
• From the issuing of PALL command to issuing SELF command in self-refresh mode The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 288 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0] 01 R/W Nu mber of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 289 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 4, 3 TRWL[1:0] * 00 R/W Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below.

• Cycle number from the issuance of the WRITA command by this LSI until the completion of auto- precharge in the SDRAM. Equivalent to the cycle number from the issuance of the WRITA command until the issuance of the ACTV command. Confirm that how many cycles are required between the WRITE command receive in the SDRAM and the auto-precharge activation, referring to each SDRAM data sheet. And set the cycle number so as not to exceed the cycle number specified by this bit.
• Cycle number from the issuance of the WRITA command until the issuance of the PRE command. This is the case when accessing another low address in the same bank in bank active mode. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 290 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 WTRC[1:0] * 00 R/W Number of Idle Cycles from REF Command/Self- Refresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below.

• From the issuance of the REF command until the issuance of the ACTV/REF/MRS command
• From releasing self-refresh until the issuance of the ACTV/REF/MRS command. The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 291 of 1692 REJ09B0393-0100 (4) Burst ROM (Clock Synchronous)

• CS0WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRR R / W R / W 0000010100000000 R R R R R R/W R/W R/W R/W R/W R R R R R R Bit Bit Name Initial Value R/W Description 31 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 292 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 293 of 1692 REJ09B0393-0100

9.4.4 SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. SDCR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit: Initial value: R/W: 0000000000000000 R R R R R R R R R R R R/W R/W R R/W R/W 0000000000000000 R R R/W R/W R/W R/W R/W R/W R R R R/W R/W R R/W R/W A3ROW[1:0] A2COL[1:0] A3COL[1:0] - - DEEP SLOW RFSH RMODEPDOWN BACTV - - - - Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20, 19 A2ROW[1:0] 00 R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 294 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 17, 16 A2COL[1:0] 00 R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 DEEP 0 R/W Deep Power-Down Mode

This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low- power SDRAM enters deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode

12 SLOW 0 R/W Low-Frequency Mode

Specifies the output timing of command, address, and write data for SDRAM and the latch timing of read data from SDRAM. Setting this bit makes the hold time for command, address, write and read data extended for half cycle (output or read at the falling edge of CK). This mode is suitable for SDRAM with low-frequency clock. 0: Command, address, and write data for SDRAM is output at the rising edge of CK. Read data from SDRAM is latched at the rising edge of CK. 1: Command, address, and write data for SDRAM is output at the falling edge of CK. Read data from SDRAM is latched at the falling edge of CK.

11 RFSH 0 R/W Refresh Control

Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 295 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

10 RMODE 0 R/W Refresh Control

Specifies whether to perform auto-refresh or self- refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed

9 PDOWN 0 R/W Power-Down Mode

Specifies whether the SDRAM will enter power-down mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters power- down mode. 0: The SDRAM does not enter power-down mode after being accessed. 1: The SDRAM enters power-down mode after being accessed.

8 BACTV 0 R/W Bank Active Mode

Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be set only in area 3, and only the 16-bit bus width can be set. When both the CS2 and CS3 spaces are set to SDRAM, specify auto-precharge mode. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 296 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 4, 3 A3ROW[1:0] 00 R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 A3COL[1:0] 00 R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 297 of 1692 REJ09B0393-0100

9.4.5 Refresh Timer Contro l/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM. RTCSR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value other than B'000. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W - - - - - - - - CMF CMIE CKS[2:0] RRC[2:0] Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved These bits are always read as 0.

7 CMF 0 R/W Compare Match Flag

Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 298 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

6 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: Bφ/4 010: Bφ/16 011: Bφ/64 100: Bφ/256 101: Bφ/1024 110: Bφ/2048 111: Bφ/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: 1 time 001: 2 times 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited)

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9.4.6 Refresh Time r Counter (RTCNT)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0000000000000000 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This counter is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved These bits are always read as 0. 7 to 0 All 0 R/W 8-Bit Counter

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 300 of 1692 REJ09B0393-0100

9.4.7 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. The REFOUT signal can be asserted when a refresh request is generated while the bus is released. For details, see the description of Relationship between Refresh Requests and Bus Cycles in section 9.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 9.5.11, Bus Arbitration. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This register is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved These bits are always read as 0. 7 to 0 All 0 R/W 8-Bit Register

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 301 of 1692 REJ09B0393-0100

9.4.8 Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit register that specifies the timing of DTC or DMAC bus release. It is used to give priority to DTC or DMAC transfer or reduce the number of cycles in which the DTC is active. For the differences in DTC operation according to the combinations of the DTLOCK and DTBST bit settings, refer to section 8.5.9, DTC Bus Release Timing. Setting the DTSA bit enables DTC short address mode. For details of the short address mode, see section 8.4, Location of Transfer Information and DTC Vector Table. The DTPR bit selects the DTC activation priority used when multiple DTC activation requests are generated before DTC activation. Do not modify this register while the DMAC or DTC is active. RRRRRRRRR/WRR/WR/WRRRR/W Initial value: R/W: LOCK 0000000000000000 Bit: 15 14 13 12 11 8 1 0 9 76543 0 2 1 Bit Bit Name Initial Value R/W Description

15 DTLOCK 0 R/W DTC Lock Enable

Specifies the timing of DTC bus release. 0: The DTC releases the bus when the NOP instruction is issued after vector read, or after write-back of transfer information is completed. 1: The DTC releases the bus after vector read, when the NOP instruction is issued after vector read, after transfer information read, after a single data transfer, or after write-back of transfer information. 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 302 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

11 DTBST 0 R/W DTC Burst Enable

Selects whether the DTC continues operation without releasing the bus when multiple DTC activation requests are generated. 0: The DTC releases the bus every time a DTC activation request has been processed. 1: The DTC continues operation without releasing the bus until all DTC activation requests have been processed. Notes: When this bit is set to 1, the following restrictions apply. 1. Clock setting through the frequency control register (FRQCR) must be Iφ : Bφ : Pφ: Mφ: Aφ = 8 : 4 : 4 : 4 : 4, 4 : 2 : 2 : 2 : 2, or 2 : 1 : 1 : 1 : 1. 2. The vector information must be stored in the on-chip ROM or on-chip RAM. 3. The transfer information must be stored in the on-chip RAM. 4. Transfer must be between the on-chip RAM and an on-chip peripheral module or between the external memory and an on- chip peripheral module. 5. Do not set the DTBST bit to 1, when the activation source is low-level setting for IRQ7 to IRQ0 and the RRS bit is set to 1.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 303 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

10 DTSA 0 R/W DTC Short Address Mode

Selects the short address mode in which only three longwords are required for DTC transfer information read. 0: Four longwords are read as the transfer information. The transfer information is arranged as shown in the figure for normal mode in figure 8.2. 1: Three longwords are read as the transfer information. The transfer information is arranged as shown in the figure for short address mode in figure 8.2. Note: The short address mode can be used only for transfer between an on-chip peripheral module and the on-chip RAM because the upper eight bits of SAR and DAR are assumed as all 1s. 9  0 R Reserved This bit is always read as 0. The write value should always be 0.

8 DTPR 0 R/W DTC Activation Priority

Selects whether to start transfer from the first DTC activation request or according to the DTC activation priority when multiple DTC activation requests are generated before the DTC is activated. Note that DTC transfer is always started according to the DTC activation priority when multiple DTC activation requests are generated while the DTC is active. 0: Starts transfer from the DTC activation request generated first. 1: Starts transfer according to the DTC activation priority. Notes: When this bit is set to 1, the following restrictions apply. 1. The vector information must be stored in the on-chip ROM or on-chip RAM. 2. The transfer information must be stored in the on-chip RAM. 3. The function for skipping the transfer information read step is always disabled.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 304 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 305 of 1692 REJ09B0393-0100

9.5 Operation

9.5.1 Endian/Access Size and Data Alignment

This LSI supports big endian in which the 0 address is the most significant byte (MSB), and little endian in which the 0 address is the least significant byte (LSB) in the byte data. In a space of areas 1 to 7, endian can be set by the CSnBCR setting while the target space is not accessed. In a space of area 0, the CSnBCR setting is invalid in on-chip ROM-disabled mode. In on-chip ROM- enabled mode, endian can be set by the CSnBCR setting in a space of areas 0 to 7. For normal memory and SRAM with byte selection, the data bus width can be selected from three widths (8, 16, and 32 bits) in the SH7286 or two widths (8 and 16 bits) in the SH7285 and SH7243. For SDRAM, the data bus width can be selected from two widths (16 and 32 bits) in the SH7286 but only the 16-bit data bus width is available in the SH7285 and SH7243. For MPX-I/O, the data bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. Data alignment is performed in accordance with the data bus width of the device. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 9.5 to 9.10 show the relationship between device data width and access unit. Note that addresses corresponding to the strobe signals for the 16-bit bus width differ between big endian and little endian. WRH indicates the 0 address in big-endian mode, but WRL indicates the 0 address in little-endian mode. Area 0 cannot be selected as little endian. Since the instruction fetch is mixed with the 32- and 16- bit access and the allocation to the little endian area is difficult, the instruction must be executed within the big endian aera.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 306 of 1692 REJ09B0393-0100 Table 9.5 32-Bit External Device Access and Data Alignment in Big-Endian Mode (Only in SH7286) Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WRHH, DQMUU WRHL, DQMUL WRH, DQMLU WRL, DQMLL Byte access at 0 Data 7 to 0    Assert    Byte access at 1  Data 7 to 0    Assert   Byte access at 2   Data 7 to 0    Assert  Byte access at 3    Data 7 to 0    Assert Word access at 0 Data 15 to 8 Data 7 to 0   Assert Assert   Word access at 2  Data 15 to 8 Data 7 to 0   Assert Assert Longword access at 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 9.6 16-Bit External Device Access and Data Alignment in Big-Endian Mode Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH, DQMLU WRL, DQMLL Byte access at 0 Data 7 to 0  Assert  Byte access at 1  Data 7 to 0  Assert Byte access at 2 Data 7 to 0  Assert  Byte access at 3  Data 7 to 0  Assert Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert 1st time at 0 Data 23 to 16 Data 31 to 24 Assert Assert Longword access at 0 2nd time at 2 Data 7 to 0 Data 15 to 8 Assert Assert

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 307 of 1692 REJ09B0393-0100 Table 9.7 8-Bit External Device Access and Data Alignment in Big-Endian Mode Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH, DQMLU WRL, DQMLL Byte access at 0  Data 7 to 0  Assert Byte access at 1  Data 7 to 0  Assert Byte access at 2  Data 7 to 0  Assert Byte access at 3  Data 7 to 0  Assert 1st time at 0  Data 15 to 8  Assert Word access at 0 2nd time at 1  Data 7 to 0  Assert 1st time at 2  Data 15 to 8  Assert Word access at 2 2nd time at 3  Data 7 to 0  Assert 1st time at 0  Data 31 to 24  Assert 2nd time at 2  Data 23 to 16  Assert 3rd time at 2  Data 15 to 8  Assert Longword access at 0 4th time at 3  Data 7 to 0  Assert

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 308 of 1692 REJ09B0393-0100 Table 9.8 32-Bit External Device Access and Data Alignment in Little-Endian Mode (Only in SH7286) Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WRHH, DQMUU WRHL, DQMUL WRH, DQMLU WRL, DQMLL Byte access at 0    Data 7 to 0    Assert Byte access at 1   Data 7 to 0    Assert  Byte access at 2  Data 7 to 0    Assert   Byte access at 3 Data 7 to 0    Assert    Word access at 0   Data 15 to 8 Data 7 to 0   Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0   Assert Assert   Longword access at Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 9.9 16-Bit External Device Access and Data Alignment in Little-Endian Mode Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH, DQMLU WRL, DQMLL Byte access at 0  Data 7 to 0  Assert Byte access at 1 Data 7 to 0  Assert  Byte access at 2  Data 7 to 0  Assert Byte access at 3 Data 7 to 0  Assert  Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert 1st time at 0 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at 0 2nd time at 2 Data 31 to 24 Data 23 to 16 Assert Assert

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 309 of 1692 REJ09B0393-0100 Table 9.10 8-Bit External Device Access and Data Alignment in Little-Endian Mode Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WRH, DQMLU WRL, DQMLL Byte access at 0  Data 7 to 0  Assert Byte access at 1  Data 7 to 0  Assert Byte access at 2  Data 7 to 0  Assert Byte access at 3  Data 7 to 0  Assert 1st time at 0  Data 7 to 0  Assert Word access at 0 2nd time at 1  Data 15 to 8  Assert 1st time at 2  Data 7 to 0  Assert Word access at 2 2nd time at 3  Data 15 to 8  Assert 1st time at 0  Data 7 to 0  Assert 2nd time at 2  Data 15 to 8  Assert 3rd time at 2  Data 23 to 16  Assert Longword access at 0 4th time at 3  Data 31 to 24  Assert

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 310 of 1692 REJ09B0393-0100

9.5.2 Normal Space Interface

(1) Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. CK Note: * The waveform for DACKn is when active low is specified. A25 to A0 RD/WR RD/WR D15 to D0 DACKn CSn T1 T2 RD WEn BS D15 to D0 Read Write Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 311 of 1692 REJ09B0393-0100 There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 16 bits are always read in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 9.3 and 9.4 show the basic timings of normal space access. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 9.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 9.4). CK A25 to A0 RD RD/WR D15 to D0 WEn D15 to D0 DACKn BS WAIT CSn T1 T2 Tnop T1 T2 Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 312 of 1692 REJ09B0393-0100 CK A25 to A0 RD/WR D15 to D0 DACKn CSn T1 T2 T1 T2 RD WEn BS WAIT D15 to D0 Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 313 of 1692 REJ09B0393-0100 A16 CS OE I/O7 I/O0 A18 CSn RD D31 D24 WE3 D23 D16 WE2 D15 WE1 WE0 This LSI 128K × 8-bit SRAM . . . A16 CS OE I/O7 I/O0 A16 CS OE I/O7 I/O0 A16 CS OE I/O7 I/O0 Figure 9.5 Example of 32-Bit Data-Width SRAM Connection (Only SH7286)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 315 of 1692 REJ09B0393-0100

9.5.3 Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 1, 4, 5, and 7 to insert wait cycles independently in read access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 9.8. CK A25 to A0 CSn RD/WR RD D15 to D0 WEn D15 to D0 BS Tw Read Write DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 316 of 1692 REJ09B0393-0100 When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CK at the transition from the T1 or Tw cycle to the T2 cycle. CK A25 to A0 CSn RD/WR RD D15 to D0 WEn D15 to D0 WAIT Tw Tw Twx T2 Read Write BS Wait states inserted by WAIT signal DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 9.9 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 317 of 1692 REJ09B0393-0100

9.5.4 CSn Assert Period Expansion

The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. CK A25 to A0 CSn RD/WR RD D15 to D0 WEn D15 to D0 BS Th Read Write DACKn* Tf Note: * The waveform for DACKn is when active low is specified. Figure 9.10 CSn Assert Period Expansion

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 318 of 1692 REJ09B0393-0100

9.5.5 MPX-I/O Interface

Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous access cycles. Address output is increased to 3 cycles by setting the MPXW bit in CS5WCR to 1. The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. Timing charts are shown in figures 9.11 to 9.13.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 319 of 1692 REJ09B0393-0100 CK A25 to A0 CS5 RD/WR RD D15/D7 to D0 D15/D7 to D0 WEn BS Read Write DACKn* Note * The waveform for DACKn is when active low is specified. Ta1 Ta2 Ta3 AH Address Address Data Data Figure 9.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 320 of 1692 REJ09B0393-0100 CK A25 to A0 CS5 RD/WR RD D15/D7 to D0 WEn D15/D7 to D0 BS Read Write DACKn* Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note: * The waveform for DACKn is when active low is specified. Figure 9.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 321 of 1692 REJ09B0393-0100 CK A25 to A0 CS5 RD/WR RD D15/D7 to D0 WEn D15/D7 to D0 BS Read Write DACKn* Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note: * The waveform for DACKn is when active low is specified. Figure 9.13 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 322 of 1692 REJ09B0393-0100

9.5.6 SDRAM Interface

(1) SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RASU, RASL, CASL, CASU, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 bits or 16 bits in the SH7286 or 16 bits only in the SH7285 and SH7243. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as SDRAM operating mode. Commands for SDRAM can be specified by RASL, CASL, RD/WR, and specific address signals. These commands supports:

• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks pre-charge (PALL)
• Specified bank pre-charge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with pre-charge (READA)
• Write (WRIT)
• Write with pre-charge (WRITA)
• Write mode register (MRS, EMRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, see section 9.5.1, Endian/Access Size and Data Alignment. Figures 9.14 to 9.16 show examples of the connection of the SDRAM with the LSI.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 323 of 1692 REJ09B0393-0100 As shown in figure 9.16, two sets of SDRAMs of 32Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted. When accessing the address with A25 = 1, RASU and CASU are asserted. A15 CKE CKIO CSn RASU CASU RASL CASL RD/WR D31 D16 DQMUU DQMUL D15 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) . . . A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Unused Unused Figure 9.14 Example of 32-Bit Data Width SRAM Connection (RASU and CASU are Not Used)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 324 of 1692 REJ09B0393-0100 A14 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Figure 9.15 Example of 16-bit Data Width SRAM Connection (RASU and CASU are Used)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 325 of 1692 REJ09B0393-0100 A14 CKE CK CSn RASL CASL RD/WR D15 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) . . . A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU . . . This LSI Figure 9.16 Example of 16-Bit Data Width SDRAM Connection (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0], and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.11 to 9.13 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A29 to A18 are not multiplexed and the original values of address are always output at these pins. The A0 pin of SDRAM specifies a word address. Therefore, connect the A0 pin of SDRAM to the A1 pin of the LSI; then connect the A1 pin of SDRAM to the A2 pin of the LSI, and so on.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 326 of 1692 REJ09B0393-0100 Table 9.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 Bits) 00 (11 Bits) 00 (8 Bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 Unused A13 A21 * A21 * A12 (BA1) A12 A20 * A20 * A11 (BA0) Specifies bank A11 A19 L/H * A10/AP Specifies address/precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 16-Mbit product (512 Kwords × 16 bits × 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 327 of 1692 REJ09B0393-0100 Table 9.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 Bits) 01 (12 Bits) 00 (8 Bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22 * A22 * A13 (BA1) A13 A21 * A21 * A12 (BA0) Specifies bank A12 A20 A12 A11 Address A11 A19 L/H * A10/AP Specifies address/precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specific ation; it is fixed at L or H according to access the mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 328 of 1692 REJ09B0393-0100 Table 9.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 Bits) 01 (12 Bits) 01 (9 Bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 A16 A25 A16 A15 A24 A15 Unused A14 A23 * A23 * A13 (BA1) A13 A22 * A22 * A12 (BA0) Specifies bank A12 A21 A12 A11 Address A11 A20 L/H * A10/AP Specifies address/precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 329 of 1692 REJ09B0393-0100 Table 9.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A27 A17 A16 A26 A16 A15 A25 A15 Unused A14 A24 * A24 * A13 (BA1) A13 A23 * A23 * A12 (BA0) Specifies bank A12 A22 A12 A11 Address A11 A21 L/H * A10/AP Specifies address/precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 330 of 1692 REJ09B0393-0100 Table 9.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 A16 A25 A16 Unused A15 A24 * A24 * A14 (BA1) A14 A23 * A23 * A13 (BA0) Specifies bank A13 A22 A13 A12 A12 A21 A12 A11 Address A11 A20 L/H * A10/AP Specifies address/precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 331 of 1692 REJ09B0393-0100 Table 9.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A27 A17 A16 A26 A16 Unused A15 A25 * A25 * A14 (BA1) A14 A24 * A24 * A13 (BA0) Specifies bank A13 A23 A13 A12 A12 A22 A12 A11 Address A11 A21 L/H * A10/AP Specifies address/precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 512-Mbit product (8 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 332 of 1692 REJ09B0393-0100 (3) Burst Read A burst read occurs in the following cases with this LSI.

• Access size in reading is larger than data bus width.
• 16-byte transfer in DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that is connected to a 16-bit data bus. This access is called the burst read with the burst number 8. Table 9.14 shows the relationship between the access size and the number of bursts. Table 9.14 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 Figures 9.17 and 9.18 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CK) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto- precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM in variable frequencies. Figure 9.18 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 333 of 1692 REJ09B0393-0100 be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. Tc4 CK A25 to A0 CSn RD/WR RASL, RASU DQMxx D15 to D0 BS (Tap) DACKn*2 Tr Tc2 Tc3Tc1 Td4 Tde Td2 Td3Td1 A12/A11*1 CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.17 Burst Read Basic Timing (CAS Latency 1, Auto-Precharge)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 334 of 1692 REJ09B0393-0100 Tc4 (Tap)Tr Tc2 Tc3Tc1 Td4 Tde Td2 Td3Td1 Trw Tw CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.18 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD[1:0] = 1 Cycle, Auto-Precharge)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 336 of 1692 REJ09B0393-0100 (5) Burst Write A burst write occurs in the following cases in this LSI.

• Access size in writing is larger than data bus width.
• 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is connected to a 16-bit data bus. This access is called burst write with the burst number 8. The relationship between the access size and the number of bursts is shown in table 9.14. Figure 9.20 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto- precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 337 of 1692 REJ09B0393-0100 Tc4 TapTr Tc2 Tc3Tc1 Trwl CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.20 Basic Timing for Burst Write (Auto-Precharge)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 338 of 1692 REJ09B0393-0100 (6) Single Write A write access ends in one cycle when the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write. Figure 9.21 shows the single write basic timing. TapTr Tc1 Trwl CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.21 Single Write Basic Timing (Auto-Precharge)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 339 of 1692 REJ09B0393-0100 (7) Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM or both the upper and lower bits of area 3 are connected to SDRAM, auto-precharge mode must be set. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As SDRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 9.22, a burst read cycle for the same row address in figure 9.23, and a burst read cycle for different row addresses in figure 9.24. Similarly, a burst write cycle without auto-precharge is shown in figure 9.25, a burst write cycle for the same row address in figure 9.26, and a burst write cycle for different row addresses in figure 9.27. In figure 9.23, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 340 of 1692 REJ09B0393-0100 latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. When bank active mode is set, if only access cycles to the respective banks in the area 3 space are considered, as long as access cycles to the same row address continue, the operation starts with the a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 9.23 or 9.26 is executed instead of that in figure 9.24 or 9.27. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Tc4Tr Tc2 Tc3Tc1 Td4Td2 Td3Td1 Tde CK A25 to A0 CS3 RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.22 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 341 of 1692 REJ09B0393-0100 Tc4Tc2 Tc3Tc1Tnop Td4 Tde Td2 Td3Td1 CK A25 to A0 CS3 RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.23 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 342 of 1692 REJ09B0393-0100 Tc4TpwTp Tc2 Tc3Tc1 Td4Td2 Td3Td1 TdeTr CK A25 to A0 CS3 RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 343 of 1692 REJ09B0393-0100 Tr Tc1 CK A25 to A0 CS3 RD/WR RASL DQMxx D31 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.25 Single Write Timing (Bank Active, Different Bank)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 344 of 1692 REJ09B0393-0100 Tnop Tc1 CK A25 to A0 CS3 RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.26 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 345 of 1692 REJ09B0393-0100 TpwTp Tc1Tr CK A25 to A0 CS3 RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.27 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 346 of 1692 REJ09B0393-0100 (8) Refreshing This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. (a) Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto- refresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 9.28 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 347 of 1692 REJ09B0393-0100 TpwTp Trr Trc Trc Trc Hi-z CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.28 Auto-Refresh Timing

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 348 of 1692 REJ09B0393-0100 (b) Self-refreshing Self-refresh mode is a standby mode in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR. Self-refresh timing is shown in figure 9.29. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 349 of 1692 REJ09B0393-0100 TpwTp Trr Trc Trc Hi-z Trc CK CKE A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.29 Self-Refresh Timing

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 350 of 1692 REJ09B0393-0100 (9) Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. This LSI has the REFOUT pin to request the bus while waiting for refresh execution. For REFOUT pin function selection, see section 23, Pin Function Controller (PFC). This LSI continues to assert REFOUT (low level) until the bus is acquired. On receiving the asserted REFOUT signal, the external device must negate the BREQ signal and return the bus. If the external bus does not return the bus for a period longer than the specified refresh interval, refresh cannot be executed and the SDRAM contents may be lost. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is completed.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 353 of 1692 REJ09B0393-0100 (12) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after waiting for 100 µs or a longer period after powering on. This 100-µs or longer period should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2 SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 9.15. In this time 0 is output at the external address pins of A12 or later. Table 9.15 Access Address in SDRAM Mode Register Write

• Setting for Area 2 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4440 H'0000440

3 H'FFFC4460 H'0000460

Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4040 H'0000040

3 H'FFFC4060 H'0000060

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 354 of 1692 REJ09B0393-0100

• Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5440 H'0000440

3 H'FFFC5460 H'0000460

Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5040 H'0000040

3 H'FFFC5060 H'0000060

Mode register setting timing is shown in figure 9.32. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 355 of 1692 REJ09B0393-0100 TpwTp Trr Trc Trc Tmw Hi-Z TnopTrc Trr Trc REF REF MRSPALL CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.32 SDRAM Mode Write Timing (Based on JEDEC)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 356 of 1692 REJ09B0393-0100 (13) Low-Power SDRAM The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which there is data in a work area other than the specific area can be lost without severe repercussions. The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the EMRS command. The EMRS command is issued according to the conditions specified in table below. For example, if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Table 9.16 Output Addresses when EMRS Command Is Issued Command to be Issued Access Address Access Data Write Access Size MRS Command Issue Address EMRS Command Issue Address CS2 MRS H'FFFC4XX0 H' ****** 16 bits H'0000XX0  CS3 MRS H'FFFC5XX0 H' ****** 16 bits H'0000XX0  CS2 MRS + EMRS (with refresh) H'FFFC4XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY CS3 MRS + EMRS (with refresh) H'FFFC5XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY CS2 MRS + EMRS (without refresh) H'FFFC4XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY CS3 MRS + EMRS (without refresh) H'FFFC5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 357 of 1692 REJ09B0393-0100 CK A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS Tpw DACKn*4 Tp Trr A12/A11*3 BA1*1 BA0*2 CASL Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified. Trc Trc Tmw Hi-Z TnopTrc Trr Trc REF REF MRS Temw Tnop EMRSPALL Figure 9.33 EMRS Command Issue Timing

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 358 of 1692 REJ09B0393-0100

• Deep power-down mode The low-power SDRAM supports deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In deep power- down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel deep power-down mode. Before executing an access after returning from deep power-down mode, the power-up sequence must be re-executed. TpwTp Tdpd Trc Hi-Z Trc Trc Trc Trc CK CKE A25 to A0 CSn RD/WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.34 Deep Power-Down Mode Transition Timing

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 359 of 1692 REJ09B0393-0100

9.5.7 Burst ROM (Clock Asynchronous) Interface

The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called burst mode or page mode. In a burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles, addresses are changed at the falling edge of the CK. For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1 to W0 bits in CSnWCR is inserted. In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that does not perform the burst operation in the burst ROM (clock asynchronous) interface, access timing is same as a normal space. Table 9.17 lists a relationship between bus width, access size, and the number of bursts. Figure 9.35 shows a timing chart.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 360 of 1692 REJ09B0393-0100 Table 9.17 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 8 bits 8 bits Not affected 1 1 16 bits Not affected 2 1 32 bits Not affected 4 1 x0 16 1 16 bytes 10 4 4 16 bits 8 bits Not affected 1 1 16 bits Not affected 1 1 32 bits Not affected 2 1 00 8 1 01 2 4 4 2 16 bytes 10* 2, 4, 2 3 Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in CSnWCR are 10, the number of bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4 or H'xxxC, 2-4-2 burst access is performed.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 361 of 1692 REJ09B0393-0100 CK A25 to A0 RD D15 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. WAIT CSn T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 RD/WR BS Figure 9.35 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 362 of 1692 REJ09B0393-0100

9.5.8 SRAM Interface with Byte Selection

The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin (WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 9.36. In write access, data is written to the memory according to the timing of the byte- selection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 9.37 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 9.38 shows the access timing when a software wait is specified.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 363 of 1692 REJ09B0393-0100 CK A25 to A0 CSn WEn RD/WR RD RD D15 to D0 D15 to D0 RD/WR BS DACKn* Read Write Note: * The waveform for DACKn is when active low is specified. T1 T2 High Figure 9.36 Basic Access Timing for SRAM with Byte Selection (BAS = 0)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 364 of 1692 REJ09B0393-0100 T1 T2 High CK A25 to A0 CSn WEn RD/WR RD RD D15 to D0 D15 to D0 RD/WR BS DACKn* Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.37 Basic Access Timing for SRAM with Byte Selection (BAS = 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 365 of 1692 REJ09B0393-0100 T2 TfTh T1 Tw High CK A25 to A0 CSn WEn RD/WR RD RD D15 to D0 D15 to D0 RD/WR BS DACKn* Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.38 Wait Timing for SRAM with Byte Selection (BAS = 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 366 of 1692 REJ09B0393-0100 This LSI A16 . . CSn RD RD/WR D15 . WRH WRL A15 . . CS OE WE I/O 15 . I/O 0 UB LB 64K × 16-bit SRAM Figure 9.39 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 367 of 1692 REJ09B0393-0100

9.5.9 Burst ROM (Clock Synchronous) Interface

The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR. While the burst ROM (clock synchronous) is accessed, the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. If the bus width is 16 bits, the burst length must be specified as 8. The burst ROM interface does not support the 8-bit bus width for the burst ROM. The burst ROM interface performs burst operations for all read access. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, using 16-byte read by cache fill in the cache-enabled space or 16-byte read by the DMA is recommended. The burst ROM interface performs write access in the same way as normal space access. TwbT1 T2Tw T2BTw T2B Twb Twb T2B T2B Twb Twb T2B T2B Twb T2B Twb Note: * The waveform for DACKn is when active low is specified. CK CS0 RD/WR A25 to A0 RD D15 to D0 WAIT BS DACKn* Figure 9.40 Burst ROM Access Timing (Clock Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 368 of 1692 REJ09B0393-0100

9.5.10 Wait betw een Access Cycles

As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS 0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the idle cycles between access cycles are shown below. 1. Continuous acce ss cycles are write-read or write-write 2. Continuous access cycles are read-write for different spaces 3. Continuous access cycles are read-write for the same space 4. Continuous access cycles are read-read for different spaces 5. Continuous access cycles are read-read for the same space 6. Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) For the specification of the number of idle cycles between access cycles described above, refer to the description of each register. Besides the idle cycles between access cycles specified by the registers, idle cycles must be inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed pin (WEn). The following gives detailed information about the idle cycles and describes how to estimate the number of idle cycles. The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is described below. There are eight conditions that determine the number of idle cycles on the external bus as shown in table 9.18. The effects of these conditions are shown in figure 9.41.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 369 of 1692 REJ09B0393-0100 Table 9.18 Conditions for Determining Number of Idle Cycles No. Condition Description Range Note (1) DMAIW[2:0] in CMNCR These bits specify the number of idle cycles for DMA single address transfer. This condition is effective only for single address transfer and generates idle cycles after the access is completed. 0 to 12 When 0 is specified for the number of idle cycles, the DACK signal may be asserted continuously. This causes a discrepancy between the number of cycles detected by the device with DACK and the DMAC transfer count, resulting in a malfunction. (2) IW ***[2:0] in CSnBCR These bits specify the number of idle cycles for access other than single address transfer. The number of idle cycles can be specified independently for each combination of the previous and next cycles. For example, in the case where reading CS1 space followed by reading other CS space, the bits IWRRD[2:0] in CS1BCR should be set to B'100 to specify six or more idle cycles. This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed. 0 to 12 Do not set 0 for the number of idle cycles between memory types which are not allowed to be accessed successively. (3) SDRAM-related bits in CSnWCR These bits specify precharge completion and startup wait cycles and idle cycles between commands for SDRAM access. This condition is effective only for SDRAM access and generates idle cycles after the access is completed 0 to 3 Specify these bits in accordance with the specification of the target SDRAM. (4) WM in CSnWCR This bit enables or disables external WAIT pin input for the memory types other than SDRAM. When this bit is cleared to 0 (external WAIT enabled), one idle cycle is inserted to check the external WAIT pin input after the access is completed. When this bit is set to 1 (disabled), no idle cycle is generated. 0 or 1

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 370 of 1692 REJ09B0393-0100 No. Condition Description Range Note (5) Read data transfer cycle One idle cycle is inserted after a read access is completed. This idle cycle is not generated for the first or middle cycles in divided access cycles. This is neither generated when the HM[1:0] bits in CSnWCR are not B'00. 0 or 1 One idle cycle is always generated after a read cycle with SDRAM interface. (6) Internal bus idle cycles, etc. External bus access requests from the CPU or DMAC and their results are passed through the internal bus. The external bus enters idle state during internal bus idle cycles or while a bus other than the external bus is being accessed. This condition is not effective for divided access cycles, which are generated by the BSC when the access size is larger than the external data bus width. 0 or larger The number of internal bus idle cycles may not become 0 depending on the Iφ:Bφ clock ratio. Tables 9.19 and 9.20 show the relationship between the clock ratio and the minimum number of internal bus idle cycles. (7) Write data wait cycles During write access, a write cycle is executed on the external bus only after the write data becomes ready. This write data wait period generates idle cycles before the write cycle. Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous write cycle, write data can be prepared in parallel with the previous write cycle and therefore, no idle cycle is generated (write buffer effect). 0 or 1 For write → write or write → read access cycles, successive access cycles without idle cycles are frequently available due to the write buffer effect described in the left column. If successive access cycles without idle cycles are not allowed, specify the minimum number of idle cycles between access cycles through CSnBCR. (8) Idle cycles between different memory types To ensure the minimum pulse width on the signal-multiplexed pins, idle cycles may be inserted before access after memory types are switched. For some memory types, idle cycles are inserted even when memory types are not switched. 0 to 2.5 The number of idle cycles depends on the target memory types. See table 9.21.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 371 of 1692 REJ09B0393-0100 In the above conditions, a total of four conditions, that is, condition (1) or (2) (either one is effective), condition (3) or (4) (either one is effective), a set of conditions (5) to (7) (these are generated successively, and therefore the sum of them should be taken as one set of idle cycles), and condition (8) are generated at the same time. The maximum number of idle cycles among these four conditions becomes the number of idle cycles on the external bus. To ensure the minimum idle cycles, be sure to make register settings for condition (1) or (2). CK CSn Previous access External bus idle cycles Idle cycle after access Either one of them is effective [1]DMAIW[2:0] setting in CMNCR [2]IWW[2:0] setting in CSnBCR IWRWD[2:0] setting in CSnBCR IWRWS[2:0] setting in CSnBCR IWRRD[2:0] setting in CSnBCR IWRRS[2:0] setting in CSnBCR [3]WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR WTRC[1:0] setting in CSnWCR [4]WM setting in CSnWCR [6] Internal bus idle cycles, etc. [8] Idle cycles between different memory types [5]Read data transfer [7] Write data wait Idle cycle before access Next access Condition [1] or [2] A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7], and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of cycles among these four conditions become the number of idle cycles. Note: Condition [8] Condition [3] or [4] Set of conditions [5] to [7] Either one of them is effective Figure 9.41 Idle Cycle Conditions

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 372 of 1692 REJ09B0393-0100 Table 9.19 Minimum Number of Idle Cycles on Internal Bus (CPU Operation) Clock Ratio (Iφ:Bφ) CPU Operation 4:1 2:1 1:1 Write → write 2 2 3 Write → read 0 0 1 Read → write 2 2 3 Read → read 0 0 1 Table 9.20 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation) Transfer Mode DMAC Operation Dual Address Single Address Write → write 0 2 Write → read 0 or 2 0 Read → write 0 0 Read → read 0 2 Notes: 1. The write → write and read → read columns in dual address transfer indicate the cycles in the divided access cycles. 2. For the write → read cycles in dual address transfer, 0 means different channels are activated successively and 2 means when the same channel is activated successively. 3. The write → read and read → write columns in single address transfer indicate the case when different channels are activated successively. The "write" means transfer from a device with DACK to external memory and the "read" means transfer from external memory to a device with DACK.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 373 of 1692 REJ09B0393-0100 Table 9.21 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types Next Cycle Previous Cycle SRAM Burst ROM (Asynchronous) MPX- I/O Byte SRAM (BAS = 0) Byte SRAM (BAS = 1) SDRAM SDRAM (Low-Frequency Mode) Burst ROM (Synchronous) SRAM 0 0 1 0 1 1 1.5 0 Burst ROM (asynchronous) 0 0 1 0 1 1 1.5 0 MPX-I/O 1 1 0 1 1 1 1.5 1 Byte SRAM (BAS = 0) 0 0 1 0 1 1 1.5 0 Byte SRAM (BAS = 1) 1 1 2 1 0 0 1.5 1 SDRAM 1 1 2 1 0 0  1 SDRAM (low-frequency mode) Burst ROM (synchronous) 0 0 1 0 1 1 1.5 0 Figure 9.42 shows sample estimation of idle cycles between access cycles. In the actual operation, the idle cycles may become shorter than the estimated value due to the write buffer effect or may become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU instruction execution or CPU register conflicts. Please consider these errors when estimating the idle cycles.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 374 of 1692 REJ09B0393-0100 Sample Estimation of Idle Cycles between Access Cycles

• Conditions Condition Note R → RR → WW → WW → R 0000 0000 1100 0220 0100 0420 0000 1420 [1] or [2] [3] or [4] [5] [6] [7] [5] + [6] + [7] [8] Estimated idle cycles Actual idle cycles CSnBCR is set to 0. The WM bit is set to 1. Generated after a read cycle. See the Iφ:Bφ = 4:1 column in table 9.19. No idle cycle is generated for the second time due to the write buffer effect. Value for SRAM → SRAM access Maximum value among conditions [1] or [2], [3] or [4], The estimated value does not match the actual value in the W → R cycles because the internal idle cycles due to condition [6] is estimated as 0 but actually an internal idle cycle is generated due to execution of a loop condition check instruction. 421 The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0. In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00 (CS negation is not extended). Iφ:Bφ is set to 4:1, and no other processing is done during transfer. For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is also 32 bits. This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is repeated in the following order: CS1 read → CS1 read → CS2 write → CS2 write → CS1 read → ... The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table, R indicates a read cycle and W indicates a write cycle. Figure 9.42 Comparison between Estimated Idle Cycles and Actual Value

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 375 of 1692 REJ09B0393-0100

9.5.11 Bus Arbitration

The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. Between the read and write cycles of a TAS inst ruction, or 64-bit transfer cycle of an FMOV instruction 2. Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 3. 16-byte transfer by the DMAC 4. Setting the BLOCK bit in CMNCR to 1 Moreover, by using DPRTY bit in CMNCR, whether the bus mastership request is received or not can be selected during DMAC burst transfer. The LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the external device has released the bus, it negates the BACK signal and resumes the bus usage. With the SDRAM interface, all bank pre-charge commands (PALLs) are issued when active banks exist and the bus is released after completion of a PALL command. The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CK. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CK. The bus control signals (BS, CSn, RASL, CASL, CKE, DQMxx, WEn, RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CK. Bus request signals are sampled at the falling edge of CKIO. Note that CKE, RASL, and CASL can continue to be driven at the previous value even in the bus-released state by setting the HIZCNT bit in CMNCR.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 376 of 1692 REJ09B0393-0100 The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CK, the bus control signals are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CK where address and data signals are driven. Figure 9.43 shows the bus arbitration timing. When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership should be returned using the REFOUT signal. For details on the selection of REFOUT, see section 23, Pin Function Controller (PFC). The REFOUT signal is kept asserting at low level until the bus mastership is acquired. The BREQ signal is negated by asserting the REFOUT signal and the bus mastership is returned from the external device. If the bus mastership is not returned for a refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed. While releasing the bus mastership, the SLEEP instruction (to enter sleep mode or standby mode), as well as a manual reset, cannot be executed until the LSI obtains the bus mastership. The BREQ input signal is ignored in standby mode and the BACK output signal is placed in the high impedance state. If the bus mastership request is required in this state, the bus mastership must be released by pulling down the BACK pin to enter standby mode. The bus mastership release (BREQ signal for high level negation) after the bus mastership request (BREQ signal for low level assertion) must be performed after the bus usage permission (BACK signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted, only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be negated and this may cause a bus contention between the external device and the LSI. CK Other bus contorol sigals BREQ BACK A25 to A0 D15 to D0 CSn Figure 9.43 Bus Arbitration Timing

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 377 of 1692 REJ09B0393-0100

9.5.12 Others

(1) Reset The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. (2) Access from the Side of the LSI Internal Bus Master Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. Changing the registers in the BSC while the write buffer is operating may disrupt correct write access. Therefore, do not change the registers in the BSC immediately after a write access. If this change becomes necessary, do it after executing a dummy read of the write data.

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 378 of 1692 REJ09B0393-0100 (3) On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. Table 9.22 shows the number of cycles required for access to the on-chip peripheral I/O registers by the CPU. Table 9.22 Number of Cycles for Access to On-Chip Peripheral module registers Number of Access Cycles Write (2 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ Read (2 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + (2 + I) × Iφ Notes: The above indicates the number of access c ycles of which executed when the instructions are by on-chip ROM or by on-chip RAM. When I φ:Bφ = 1:1, n = 0 and I = 0. When I φ:Bφ = 2:1, n = 1 to 0 and I = 1. When I φ:Bφ = 4:1, n = 3 to 0 and I = 2. When I φ:Bφ = 8:1, n = 7 to 0 and I = 2. When B φ:Pφ = 1:1, m = 0. When B φ:Pφ = 2:1, m = 1 to 0. When B φ:Pφ = 4:1, m = 3 to 0. n and m depend on the internal execution state. Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus are input and output in synchronization with rising edges of the corresponding clock signal. The C

Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 380 of 1692 REJ09B0393-0100 (1 + m) × Bφ 2 × Pφ(2 + n) × Iφ (2 + I) × Iφ Iφ C bus Bφ I bus Pφ Peripheral bus Figure 9.45 Timing of Read Access to On-Chip Peripheral I/O Registers When I φ:Bφ:Pφ = 4:2:1

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 381 of 1692 REJ09B0393-0100 Section 10 Direct Memory Access Controller (DMAC) The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.

10.1 Features

• Number of channels selectable: Eight channels (channels 0 to 7) max. CH0 to CH2 channels (SH7285, SH7243) and CH0 to CH3 channels (SH7286) can only receive external requests.
• 4-Gbyte physical address space
• Transfer data length is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword × 4)
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests  External request  On-chip peripheral module request  Auto request The following modules can issue on-chip peripheral module requests.  Two SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, two CMT sources, two USB sources, two SSU sources, and one RCAN source
• Selectable bus modes  Cycle steal mode (normal mode and intermittent mode)  Burst mode
• Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full- data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to the CPU when half of the initially specified DMA transfer is completed.
• External request detection: There are following four types of DREQ input detection.  Low level detection  High level detection  Rising edge detection  Falling edge detection

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 383 of 1692 REJ09B0393-0100

10.2 Input/Output Pins

The external pins for DMAC are described below. Table 10.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for four channels (CH0 to CH3) for SH7286 and two channels (CH0 and CH1) for SH7243 and SH7285, as the external bus use. Table 10.1 Pin Configuration Channel Name Abbreviation I/O Function DMA transfer request DREQ0 I DMA transfer request input from an external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to an external device DMA transfer request DREQ1 I DMA transfer request input from an external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to an external device DMA transfer request DREQ2 I DMA transfer request input from an external device to channel 2 (only in SH7286) DMA transfer request acknowledge DACK2 O DMA transfer request acknowledge output from channel 2 to an external device (only in SH7286) DMA transfer request DREQ3 I DMA transfer request input from an external device to channel 3 (only in SH7286) DMA transfer request acknowledge DACK3 O DMA transfer request acknowledge output from channel 3 to an external device (only in SH7286)

0 DMA transfer end TEND0 O DMA transfer end output for channel 0

1 DMA transfer end TEND1 O DMA transfer end output for channel 1

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 384 of 1692 REJ09B0393-0100

10.3 Register Descriptions

The DMAC has the registers listed in table 10.2. There are four control registers and three reload registers for each channel, and one common control register is used by all channels. In addition, there is one extension resource selector per two channels. Each channel number is expressed in the register names, as in SAR_0 for SAR in channel 0. Table 10.2 Register Configuration Channel Register Name Abbrevi ation R/W Initial Value Address Access Size DMA source address register_0 SAR_0 R/W H'00000000 H'FFFE1000 16, 32 DMA destination address register_0 DAR_0 R/W H'00000000 H'FFFE1004 16, 32 DMA transfer count register_0 DMATCR_0 R/W H'000 00000 H'FFFE1008 16, 32 DMA channel control register_0 CHCR_0 R/W * H'00000000 H'FFFE100C 8, 16, 32 DMA reload source address register_0 RSAR_0 R/W H'00000000 H'FFFE1100 16, 32 DMA reload destination address register_0 RDAR_0 R/W H'000000 00 H'FFFE1104 16, 32 DMA reload transfer count register_0 RDMATCR_0 R/W H'000 00000 H'FFFE1108 16, 32 DMA source address register_1 SAR_1 R/W H'00000000 H'FFFE1010 16, 32 DMA destination address register_1 DAR_1 R/W H'00000000 H'FFFE1014 16, 32 DMA transfer count register_1 DMATCR_1 R/W H'000 00000 H'FFFE1018 16, 32 DMA channel control register_1 CHCR_1 R/W * H'00000000 H'FFFE101C 8, 16, 32 DMA reload source address register_1 RSAR_1 R/W H'00000000 H'FFFE1110 16, 32 DMA reload destination address register_1 RDAR_1 R/W H'000000 00 H'FFFE1114 16, 32 DMA reload transfer count register_1 RDMATCR_1 R/W H'000 00000 H'FFFE1118 16, 32

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 385 of 1692 REJ09B0393-0100 Channel Register Name Abbrevi ation R/W Initial Value Address Access Size DMA source address register_2 SAR_2 R/W H'00000000 H'FFFE1020 16, 32 DMA destination address register_2 DAR_2 R/W H'00000000 H'FFFE1024 16, 32 DMA transfer count register_2 DMATCR_2 R/W H'000 00000 H'FFFE1028 16, 32 DMA channel control register_2 CHCR_2 R/W * H'00000000 H'FFFE102C 8, 16, 32 DMA reload source address register_2 RSAR_2 R/W H'00000000 H'FFFE1120 16, 32 DMA reload destination address register_2 RDAR_2 R/W H'000000 00 H'FFFE1124 16, 32 DMA reload transfer count register_2 RDMATCR_2 R/W H'000 00000 H'FFFE1128 16, 32 DMA source address register_3 SAR_3 R/W H'00000000 H'FFFE1030 16, 32 DMA destination address register_3 DAR_3 R/W H'00000000 H'FFFE1034 16, 32 DMA transfer count register_3 DMATCR_3 R/W H'000 00000 H'FFFE1038 16, 32 DMA channel control register_3 CHCR_3 R/W * H'00000000 H'FFFE103C 8, 16, 32 DMA reload source address register_3 RSAR_3 R/W H'00000000 H'FFFE1130 16, 32 DMA reload destination address register_3 RDAR_3 R/W H'000000 00 H'FFFE1134 16, 32 DMA reload transfer count register_3 RDMATCR_3 R/W H'000 00000 H'FFFE1138 16, 32

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 386 of 1692 REJ09B0393-0100 Channel Register Name Abbrevi ation R/W Initial Value Address Access Size DMA source address register_4 SAR_4 R/W H'00000000 H'FFFE1040 16, 32 DMA destination address register_4 DAR_4 R/W H'00000000 H'FFFE1044 16, 32 DMA transfer count register_4 DMATCR_4 R/W H'000 00000 H'FFFE1048 16, 32 DMA channel control register_4 CHCR_4 R/W * H'00000000 H'FFFE104C 8, 16, 32 DMA reload source address register_4 RSAR_4 R/W H'00000000 H'FFFE1140 16, 32 DMA reload destination address register_4 RDAR_4 R/W H'000000 00 H'FFFE1144 16, 32 DMA reload transfer count register_4 RDMATCR_4 R/W H'000 00000 H'FFFE1148 16, 32 DMA source address register_5 SAR_5 R/W H'00000000 H'FFFE1050 16, 32 DMA destination address register_5 DAR_5 R/W H'00000000 H'FFFE1054 16, 32 DMA transfer count register_5 DMATCR_5 R/W H'000 00000 H'FFFE1058 16, 32 DMA channel control register_5 CHCR_5 R/W * H'00000000 H'FFFE105C 8, 16, 32 DMA reload source address register_5 RSAR_5 R/W H'00000000 H'FFFE1150 16, 32 DMA reload destination address register_5 RDAR_5 R/W H'000000 00 H'FFFE1154 16, 32 DMA reload transfer count register_5 RDMATCR_5 R/W H'000 00000 H'FFFE1158 16, 32

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 387 of 1692 REJ09B0393-0100 Channel Register Name Abbrevi ation R/W Initial Value Address Access Size DMA source address register_6 SAR_6 R/W H'00000000 H'FFFE1060 16, 32 DMA destination address register_6 DAR_6 R/W H'00000000 H'FFFE1064 16, 32 DMA transfer count register_6 DMATCR_6 R/W H'000 00000 H'FFFE1068 16, 32 DMA channel control register_6 CHCR_6 R/W * H'00000000 H'FFFE106C 8, 16, 32 DMA reload source address register_6 RSAR_6 R/W H'00000000 H'FFFE1160 16, 32 DMA reload destination address register_6 RDAR_6 R/W H'000000 00 H'FFFE1164 16, 32 DMA reload transfer count register_6 RDMATCR_6 R/W H'000 00000 H'FFFE1168 16, 32 DMA source address register_7 SAR_7 R/W H'00000000 H'FFFE1070 16, 32 DMA destination address register_7 DAR_7 R/W H'00000000 H'FFFE1074 16, 32 DMA transfer count register_7 DMATCR_7 R/W H'000 00000 H'FFFE1078 16, 32 DMA channel control register_7 CHCR_7 R/W * H'00000000 H'FFFE107C 8, 16, 32 DMA reload source address register_7 RSAR_7 R/W H'00000000 H'FFFE1170 16, 32 DMA reload destination address register_7 RDAR_7 R/W H'000000 00 H'FFFE1174 16, 32 DMA reload transfer count register_7 RDMATCR_7 R/W H'000 00000 H'FFFE1178 16, 32

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 388 of 1692 REJ09B0393-0100 Channel Register Name Abbrevi ation R/W Initial Value Address Access Size Common DMA operation r egister DMAOR R/W * H'0000 H'FFFE1200 8, 16 0 and 1 DMA extension resource selector 0 DMARS0 R/W H'0000 H'FFFE1300 16 2 and 3 DMA extension resource selector 1 DMARS1 R/W H'0000 H'FFFE1304 16 4 and 5 DMA extension resource selector 2 DMARS2 R/W H'0000 H'FFFE1308 16 6 and 7 DMA extension resource selector 3 DMARS3 R/W H'0000 H'FFFE130C 16 Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is read. 2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is read.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 389 of 1692 REJ09B0393-0100

10.3.1 DMA Source Addr ess Registers (SAR)

The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in single address mode, SAR is ignored. To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary. SAR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 390 of 1692 REJ09B0393-0100

10.3.2 DMA Destination Address Registers (DAR)

The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in single address mode, DAR is ignored. To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary. DAR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 391 of 1692 REJ09B0393-0100

10.3.3 DMA Transfer Count Registers (DMATCR)

The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. DMATCR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 392 of 1692 REJ09B0393-0100

10.3.4 DMA Channel Control Registers (CHCR)

The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control DMA transfer mode. The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit which specifies the TEND external pin function can be read and written to in channels 0 and 1, but it is reserved in channels 2 to 7. CHCR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R R R/W R R R R R/W R/W R R R/(W) * R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) * R/W Bit: Initial value: R/W: Bit: Initial value: R/W: Note: Only 0 can be written to clear the flag after 1 is read.* TC - - RLD - - - - DO TL - - HE HIE AM AL DM[1:0] SM[1:0] RS[3:0] DL DS TB TS[1:0] IE TE DE Bit Bit Name Initial Value R/W Descriptions

31 TC 0 R/W Transfer Count Mode

Specifies whether to transmit data once or for the count specified in DMATCR by one transfer request. Note that when this bit is set to 0, the TB bit must not be set to 1 (burst mode). When the USB, RCAN, SSU, SCIF_3, or IIC3 is selected for the transfer request source, this bit (TC) must not be set to 1. 0: Transmits data once by one transfer request 1: Transmits data for the count specified in DMATCR by one transfer request 30, 29  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 393 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions

28 RLD 0 R/W Reload Function Enable or Disable

Enables or disables the reload function. 0: Disables the reload function 1: Enables the reload function 27 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

23 DO 0 R/W DMA Overrun

Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 and CHCR_7; it is always read as 0 and the write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1

22 TL 0 R/W Transfer End Level

Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0: Low-active output from TEND 1: High-active output from TEND 21, 20  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 394 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions

19 HE 0 R/(W) * Half-End Flag

This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts. If DMA transfer ends because of an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches half of the initial DMATCR value, the HE bit is not set to 1. If DMA transfer ends due to an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR after the HE bit is set to 1, the bit remains set to 1. To clear the HE bit, write 0 to it after HE = 1 is read. 0: DMATCR > (DMATCR set before transfer starts)/2 during DMA transfer or after DMA transfer is terminated [Clearing condition]

• Writing 0 after reading HE = 1. 1: DMATCR ≤ (DMATCR set before transfer starts)/2

18 HIE 0 R/W Half-End Interrupt Enable

Specifies whether to issue an interrupt request to the CPU when the transfer count reaches half of the DMATCR value that was specified before transfer starts. When the HIE bit is set to 1, the DMAC requests an interrupt to the CPU when the HE bit becomes 1. 0: Disables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 1: Enables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 395 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions

17 AM 0 R/W Acknowledge Mode

Specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: DACK output in read cycle (dual address mode) 1: DACK output in write cycle (dual address mode)

16 AL 0 R/W Acknowledge Level

Specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Low-active output from DACK 1: High-active output from DACK Note: To use the DACK pins as high-active output, pull them down and perform the following settings. 1. After the reset start, specify the high-active output by this bit in CHCR for the DACK pins. 2. Then specify the DACK pins for the pin function controller setting. 3. The DACK pin setting in CHCR should be retained hereafter.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 396 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions 15,14 DM[1:0] 00 R/W Destination Address Mode These bits select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (Setting prohibited in 16- byte transfer) 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (–1 in 8-bit transfer, –2 in 16-bit transfer, –4 in 32-bit transfer, setting prohibited in 16-byte transfer) 11: Setting prohibited 13, 12 SM[1:0] 00 R/W Source Address Mode These bits select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (Setting prohibited in 16- byte-unit transfer) 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword- unit transfer, +16 in 16-byte-unit transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longword- unit transfer, setting prohibited in 16-byte-unit transfer) 11: Setting prohibited

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 397 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions 11 to 8 RS[3:0] 0000 R/W Resource Select These bits specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state when DMA enable bit (DE) is set to 0. 0000: External request, dual address mode 0001: Setting prohibited 0010: External request/single address mode External address space → External device with DACK 0011: External request/single address mode External device with DACK → External address space 0100: Auto request 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: DMA extension resource selector 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: External request specification is valid only in CHCR_0 to CHCR_3. If a request source is selected in channels CHCR_4 to CHCR_7, no operation will be performed.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 398 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions DL DS R/W R/W DREQ Level DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 to CHCR_3. These bits are reserved in CHCR_4 to CHCR_7; they are always read as 0 and the write value should always be 0. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by these bits is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge

5 TB 0 R/W Transfer Bus Mode

Specifies bus mode when DMA transfers data. Note that burst mode must not be selected when TC = 0. 0: Cycle steal mode 1: Burst mode 4, 3 TS[1:0] 00 R/W Transfer Size These bits specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte unit 01: Word unit (two bytes) 10: Longword unit (four bytes) 11: 16-byte unit (four longwords)

2 IE 0 R/W Interrupt Enable

Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Disables an interrupt request 1: Enables an interrupt request

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 399 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Descriptions

1 TE 0 R/(W) * Transfer End Flag

This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends. The TE bit is not set to 1 in the following cases.

• DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0.
• DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). To clear the TE bit, write 0 after reading TE = 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been terminated [Clearing condition]
• Writing 0 after reading TE = 1 1: DMA transfer ends by the specified count (DMATCR = 0)

0 DE 0 R/W DMA Enable

Enables or disables the DMA transfer. In auto-request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this case, all of the bits TE, NMIF in DMAOR, and AE must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0 as in the case of auto-request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag after 1 is read.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 400 of 1692 REJ09B0393-0100

10.3.5 DMA Reload Source Address Registers (RSAR)

The DMA reload source address registers (RSAR) are 32-bit readable/writable registers. When the reload function is enabled, the RSAR value is written to the source address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RSAR during the current DMA transfer. When the reload function is disabled, RSAR is ignored. To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary. RSAR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 401 of 1692 REJ09B0393-0100

10.3.6 DMA Reload Destination Address Registers (RDAR)

The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers. When the reload function is enabled, the RDAR value is written to the destination address register (DAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDAR during the current DMA transfer. When the reload function is disabled, RDAR is ignored. To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary. RDAR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 402 of 1692 REJ09B0393-0100

10.3.7 DMA Reload Transfer Count Registers (RDMATCR)

The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers. When the reload function is enabled, the RDMATCR value is written to the transfer count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the reload function is disabled, RDMATCR is ignored. The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0. As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. RDMATCR is initialized to H'00000000 by a reset and retains the value in software standby mode and module standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bit: Initial value: R/W:

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 403 of 1692 REJ09B0393-0100

10.3.8 DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register also shows the DMA transfer status. DMAOR is initialized to H'0000 by a reset and retains the value in software standby mode and module standby mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R/W R/W R R R/W R/W R R R R R R/(W) * R/(W)* R/W Note: Only 0 can be written to clear the flag after 1 is read.* Bit: Initial value: R/W: - - CMS[1:0] - - PR[1:0] - - - - - AE NMIF DME Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W C ycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make intermittent mode valid. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer for every 16 cycles of Bφ clock. 11: Intermittent mode 64 Executes one DMA transfer for every 64 cycles of Bφ clock. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 404 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 9, 8 PR[1:0] 00 R/W Priority Mode These bits select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 10: Setting prohibited 11: Round-robin mode (only supported in CH0 to CH3) 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 AE 0 R/(W) * Address Error Flag

Indicates whether an address error has occurred by the DMAC. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error 1: DMAC address error occurred [Clearing condition]

• Writing 0 after reading AE = 1

1 NMIF 0 R/(W) * NMI Flag

Indicates that an NMI interrupt occurred. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the NMI interrupt is input while the DMAC is not in operation, the NMIF bit is set to 1. 0: No NMI interrupt 1: NMI interrupt occurred [Clearing condition]

• Writing 0 after reading NMIF = 1

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 405 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 DME 0 R/W DMA Master Enable

Enables or disables DMA transfer on all channels. If the DME bit and DE bit in CHCR are set to 1, DMA transfer is enabled. However, transfer is enabled only when the TE bit in CHCR of the transfer corresponding channel, the NMIF bit in DMAOR, and the AE bit are all cleared to 0. Clearing the DME bit to 0 can terminate the DMA transfer on all channels. 0: DMA transfer is disabled on all channels 1: DMA transfer is enabled on all channels Note: * Only 0 can be written to clear the flag after 1 is read. If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If round-robin mode is specified, the transfer end channel is reset. Table 10.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode bits. In each priority mode, the channel priority to accept the next transfer request may change in up to three ways according to the transfer end channel. For example, when the transfer end channel is channel 1, the priority of the channel to accept the next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the priority level is not changed at the end of transfer in the channels 4 to 7. The DMAC internal operation for an address error is as follows:

• No address error: Read (source to DMAC) → Write (DMAC to destination)
• Address error in source address: Nop → Nop
• Address error in destination address: Read → Nop

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 406 of 1692 REJ09B0393-0100 Table 10.3 Combinations of Priority Mode Bits Priority Level at the End of Transfer Transfer End Priority Mode B i t s H i g h L o w Mode CH No. PR[1] PR[0] 0 1 2 3 4 5 6 7 Mode 0 (fixed mode 1) Any channel 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Mode 1 (fixed mode 2) Any channel 0 1 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 CH0 1 1 CH1 CH2 CH3 CH0 CH4 CH5 CH6 CH7 CH1 1 1 CH2 CH3 CH0 CH1 CH4 CH5 CH6 CH7 CH2 1 1 CH3 CH0 CH1 CH2 CH4 CH5 CH6 CH7 CH3 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH4 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH5 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH6 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Mode 2 (round-robin mode) CH7 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 407 of 1692 REJ09B0393-0100

10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)

The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and DMARS3 is for channels 6 and 7. Table 10.4 shows the specifiable combinations. DMARS can specify transfer requests from two USB sources, one RCAN source, two SSU sources, two SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, and two CMT sources. DMARS is initialized to H'0000 by a reset and retains the value in software standby mode and module standby mode.

• DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH1 MID[5:0] CH1 RID[1:0] CH0 RID[1:0] CH0 MID[5:0]
• DMARS1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH3 MID[5:0] CH3 RID[1:0] CH2 RID[1:0] CH2 MID[5:0]
• DMARS2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH5 MID[5:0] CH5 RID[1:0] CH4 RID[1:0] CH4 MID[5:0]
• DMARS3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH7 MID[5:0] CH7 RID[1:0] CH6 RID[1:0] CH6 MID[5:0]

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 408 of 1692 REJ09B0393-0100 Transfer requests from the various modules specify MID and RID as shown in table 10.4. Table 10.4 DMARS Settings Peripheral Module Setting Value for One Channel ({MID, RID}) MID RID Function H'81 B'01 Receive USB H'82 B'100000 B'10 Transmit RCAN H'86 B'100001 B'10 Receive H'89 B'01 Transmit SSU H'8A B'100010 B'10 Receive H'8D B'01 Transmit SCIF_3 H'8E B'100011 B'10 Receive H'A1 B'01 Transmit IIC3 H'A2 B'101000 B'10 Receive A/D converter_0 H'B3 B'101100 B'11  MTU2_0 H'E3 B'111000 B'11  MTU2_1 H'E7 B'111001 B'11  MTU2_2 H'EB B'111010 B'11  MTU2_3 H'EF B'111011 B'11  MTU2_4 H'F3 B'111100 B'11  CMT_0 H'FB B'111110 B'11  CMT_1 H'FF B'111111 B'11  When MID or RID other than the values listed in table 10.4 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set, the transfer request source is not accepted.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 409 of 1692 REJ09B0393-0100

10.4 Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.

10.4.1 Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extension resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1. 4. When transfer has been completed for the specified count (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. Figure 10.2 is a flowchart of this procedure.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 410 of 1692 REJ09B0393-0100 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? No No Yes Yes Transfer request occurs?*1 Transfer (one transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated DMATCR = 0? No NoYes Yes No No DEI interrupt request (when IE = 1) For a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. When reload function is enabled, RSAR → SAR, RDAR → DAR, and RDMATCR → DMATCR TE = 1 NMIF = 1 or AE = 1 or DE = 0 or DME = 0? NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Transfer end Transfer terminatedNormal end Bus mode, transfer request mode, DREQ detection system*3 Yes Yes DMATCR=1/2 ? HEI interrupt request (when HE = 1) HE=1 When the TC bit in CHCR is 0, or for a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the DE and DME bits are set to 1. 2. DREQ level detection in burst mode (external request) or cycle steal mode. 3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode. Figure 10.2 DMA Transfer Flowchart

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 411 of 1692 REJ09B0393-0100

10.4.2 DMA Transfer Requests

DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and DMARS0 to DMARS3. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits in DMAOR are 0. (2) External Request Mode In this mode a transfer is performed at the request signals (DREQ0 to DREQ3) of an external device. Choose one of the modes shown in table 10.5 according to the application system. When the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), DMA transfer is performed upon a request at the DREQ input. Table 10.5 Selecting External Request Modes with the RS Bits RS[3] RS[2] RS[1] RS[0] Address Mode Transfer Source Transfer Destination 0 0 0 0 Dual address mode Any Any

0 External memory,

External memory, memory-mapped external device Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in CHCR_0 to CHCR_3 as shown in table 10.6. The source of the transfer request does not have to be the data transfer source or destination.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 412 of 1692 REJ09B0393-0100 Table 10.6 Selecting External Request Detection with DL and DS Bits CHCR DL bit DS bit Detection of External Request

0 Low level detection 0

1 Falling edge detection

0 High level detection 1

1 Rising edge detection

When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests. Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 10.7 Selecting External Request Detection with DO Bit CHCR DO bit External Request

0 Overrun 0

1 Overrun 1

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 413 of 1692 REJ09B0393-0100 (3) On-Chip Peripheral Module Request In this mode, the transfer is performed in response to the DMA transfer request signal from an on- chip peripheral module. DMA transfer request signals from on-chip peripheral modules to the DMAC include transmit data empty and receive data full requests from the SCIF, A/D conversion end request from the A/D converter, compare match request from the CMT, and data transfer requests from the IIC3 and MTU2. When a transfer request signal is sent in on-chip peripheral module request mode while DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, and NMIF = 0), DMA transfer is performed. When the transmit data empty from the SCIF is selected, specify the transfer destination as the corresponding SCIF transmit data register. Likewise, when the receive data full from the SCIF is selected, specify the transfer source as the corresponding SCIF receive data register. When a transfer request is made by the A/D converter, the transfer source must be the A/D data register (ADDR). When the IIC3 transmit is selected as the transfer request, the transfer destination must be ICDRT; when the IIC3 reception is selected as the transfer request, the transfer source must be ICDRR. Any address can be specified for data transfer source and destination when a transfer request is sent from the CMT or MTU2.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 414 of 1692 REJ09B0393-0100 Table 10.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR DMARS RS[3:0] MID RID DMA Transfer Request Source DMA Transfer Request Signal Transfer Source Transfer Destination Bus Mode

01 USB receive EP1 FIFO full transfer request USBEPDR1 Any 100000

10 USB transmit EP2 FIFO empty transfer request Any USBEPDR2

100001 10 RCAN RM0 (RCAN receive interrupt) MB0 to MB31 Any Cycle steal

01 SSU transmit SSTXI (transmit data empty) Any SSTDR0 to

10 SSU receive SSRXI (receive data full) SSRDR0 to

01 SCIF_3 transmit TXI3 (transmit FIFO data empty) Any SCFTDR3 100011

10 SCIF_3 receive RXI3 (receive FIFO data full) SCFRDR3 Any

01 IIC3 transmit TXI (transmit data empty) Any ICDRT 101000

10 IIC3 receive RXI (receive data full) ICDRR Any

101100 11 A/D converter_0 ADI0 (A/D conversion end) ADDR0 to ADDR3 Any Cycle steal 111000 11 MTU2_0 TGI0A Any Any 111001 11 MTU2_1 TGI1A Any Any 111010 11 MTU2_2 TGI2A Any Any 111011 11 MTU2_3 TGI3A Any Any 111100 11 MTU2_4 TGI4A Any Any Cycle steal or burst 111110 11 CMT_0 Compare match 0 Any Any 1000 111111 11 CMT_1 Compare match 1 Any Any Cycle steal or burst

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 415 of 1692 REJ09B0393-0100

10.4.3 Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Three modes (fixed mode 1, fixed mode 2, and round-robin mode) are selected using the PR1 and PR0 bits in DMAOR. (1) Fixed Mode In fixed modes, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). (2) Round-Robin Mode Each time one unit of word, byte, longword, or 16 bytes is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished is rotated to the lowest of the priority order among the four round-robin channels (channels 0 to 4). The priority of the channels other than the round-robin channels (channels 0 to 4) does not change even in round-robin mode. The round-robin mode operation is shown in figure 10.3. The priority in round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 immediately after a reset. When round-robin mode has been specified, do not concurrently specify cycle steal mode and burst mode as the bus modes of any two or more channels.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 416 of 1692 REJ09B0393-0100 Channel 2 is given the lowest priority among the round-robin channels. The priority of channels 0 and 1, which were higher than channel 2, is also shifted. If there is a transfer request only to channel 5 immediately after that, the priority does not change because channel 5 is not a round-robin channel. Channel 1 is given the lowest priority among the round-robin channels. The priority of channel 0, which was higher than channel 1, is also shifted. Channel 0 is given the lowest priority among the round-robin channels. CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH1 > CH2 > CH3 > CH0 > CH4 > CH5 > CH6 > CH7 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH2 > CH3 > CH0 > CH1 > CH4 > CH5 > CH6 > CH7 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 (1) When channel 0 transfers Initial priority order Initial priority order Initial priority order Initial priority order Priority order after transfer Priority order after transfer Priority order after transfer Priority order after transfer Post-transfer priority order when there is an immediate transfer request to channel 5 only (2) When channel 1 transfers (3) When channel 2 transfers (4) When channel 7 transfers Priority order does not change. Figure 10.3 Round-Robin Mode

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 418 of 1692 REJ09B0393-0100

10.4.4 DMA Transfer Types

DMA transfer has two types: single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to the transfer source and destination. A data transfer timing depends on the bus mode, which is cycle steal mode or burst mode. The DMAC supports the transfers shown in table 10.9. Table 10.9 Supported DMA Transfers Transfer Destination Transfer Source External Device with DACK External Memory Memory-Mapped External Device On-Chip Peripheral Module On-Chip Memory External device with DACK Not available Dual, single Dual, si ngle Not available Not available External memory Dual, singl e Dual Dual Dual Dual Memory-mapped external device Dual, single Dual Dual Dual Dual On-chip peripheral module Not available Dual Dual Dual Dual On-chip memory Not availabl e Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is available only for on- chip peripheral modules that support longword access.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 420 of 1692 REJ09B0393-0100 CK A25 to A0 D31 to D0 DACKn (Active-low) CSn WEn RD Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer source address Transfer destination address Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 10.6 Example of DMA Transfer Timing in Dual Mode (Transfer Source: Normal Memory, Transfer Destination: Normal Memory)

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 425 of 1692 REJ09B0393-0100 Table 10.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Size (Bits) Usable Channels External device with DACK and external memory External B/C 8/16/32/128 0 to 3 External device with DACK and memory-mapped external device External B/C 8/16/32/128 0 to 3 External memory and external memory All * B/C 8/16/32/128 0 to 7 * External memory and memory-mapped external device All* B/C 8/16/32/128 0 to 7 * Memory-mapped external device and memory- mapped external device All* B/C 8/16/32/128 0 to 7 * External memory and on-chip peripheral module All * B/C * 8/16/32/128 * 0 to 7 * Memory-mapped external device and on-chip peripheral module All* B/C * 8/16/32/128 * 0 to 7 * On-chip peripheral module and on-chip peripheral module All* B/C * 8/16/32/128 * 0 to 7 * On-chip memory and on-chip memory All * B/C 8/16/32/128 0 to 7 * On-chip memory and memory-mapped external device All* B/C 8/16/32/128 0 to 7 * On-chip memory and on-chip peripheral module All * B/C * 8/16/32/128 * 0 to 7 * Dual On-chip memory and external memory All * B/C 8/16/32/128 0 to 7 * External device with DACK and external memory External B/C 8/16/32/128 0 to 3 Single External device with DACK and memory-mapped external device External B/C 8/16/32/128 0 to 3 [Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, along with the exception of CMT and MTU2 as the transfer request source, the requesting module must be designated as the transfer source or the transfer destination. 2. Access size permitted for the on-chip perip heral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, channels 0 to 3 are only available. 4. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, the CMT and MTU2 are only available. 5. Only cycle steal except for the MTU2 and CMT as the transfer request source.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 426 of 1692 REJ09B0393-0100 (4) Bus Mode and Channel Priority In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1, channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of this is shown in figure 10.12. When multiple channels are in burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, the bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed. CPU DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 CPU CH0 CH1 CH0 DMAC CH0 and CH1 Cycle steal mode DMAC CH1 Burst mode CPUCPU Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode DMAC CH1 Burst mode Figure 10.12 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes as shown in figure 10.3. Note that channels in cycle steal and burst modes must not be mixed.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 427 of 1692 REJ09B0393-0100

10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing

(1) Number of Bus Cycles When the DMAC is the bus master, the number of bus cycles is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9, Bus State Controller (BSC). (2) DREQ Pin Sampling Timing Figures 10.13 to 10.16 show the DREQ input sampling timings in each bus mode. CK DREQ DACK Bus cycle (Rising) (Active-high) 1st acceptance 2nd acceptance CPU CPU CPU Acceptance start DMAC Non sensitive period Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CK DREQ (Overrun 0 at high level) DACK (Active-high) Bus cycle 1st acceptance CPU CPUCPU DMAC CK DREQ (Overrun 1 at high level) DACK (Active-high) Bus cycle 2nd acceptance CPU CPU CPU DMAC Acceptance start Acceptance start 2nd acceptance 1st acceptance Non sensitive period Non sensitive period Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 430 of 1692 REJ09B0393-0100 CK Address RD Data WEn WAIT CS T1 T2 Taw T1 T2 DACKn (Active low) TEND (Active low) Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 10.18 BSC Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 431 of 1692 REJ09B0393-0100

10.5 Usage Notes

10.5.1 Setting of the Half-End Flag and the Half-End Interrupt

Since the following points for caution apply in cases where reference to the state of the half-end flag in the CHCR register or the half-end interrupt is used in conjunction with the reload function, please take care on these points. Ensure that the reloaded number of transfers (the value set in RDMATCR) is always the same as the number of transfers that was initially set (the value set in DMATCR). If the initial setting in DMATCR and the value for the second and later transfers in RDMATCR are different, the timing with which the half-end flag is set may be faster than half the number of transfers, or the half-end flag might not be set at all. The same considerations apply to the half-end interrupt.

10.5.2 Timing of DACK and TEND Outputs

When the external memory is MPX-I/O or burst MPX-I/O, assertion of the DACK output has the same timing as the data cycle. For details, see the respective figures under section 9.5.5, MPX-I/O Interface, in section 9, Bus State Controller. When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted with the same timing as the corresponding CS signal. The TEND output does not depend on the type of memory and is always asserted with the same timing as the corresponding CS signal.

Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 432 of 1692 REJ09B0393-0100

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 433 of 1692 REJ09B0393-0100 Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels.

11.1 Features

• Maximum 16 pulse input/output lines and three pulse input lines
• Selection of eight counter input clocks for each channel (four clocks for channel 5)
• The following operations can be set for channels 0 to 4:  Waveform output at compare match  Input capture function  Counter clear operation  Multiple timer counters (TCNT) can be written to simultaneously  Simultaneous clearing by compare match and input capture is possible  Register simultaneous input/output is possible by synchronous counter operation  A maximum 12-phase PWM output is possible in combination with synchronous operation.
• Buffer operation settable for channels 0, 3, and 4
• Phase counting mode settable independently for each of channels 1 and 2
• Cascade connection operation
• Fast access via internal 16-bit bus
• 28 interrupt sources
• Automatic transfer of register data
• A/D converter start trigger can be generated
• Module standby mode can be settable
• A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible.
• AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible.
• Dead time compensation counter available in channel 5
• In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 434 of 1692 REJ09B0393-0100 Table 11.1 MTU2 Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock P φ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRU_5 TGRV_5 TGRW_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0 — — TGRC_3 TGRD_3 TGRC_4 TGRD_4 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input pins TIC5U TIC5V TIC5W Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare match output Toggle output Input capture function Synchronous operation Complementary PWM mode AC synchronous motor drive mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 435 of 1692 REJ09B0393-0100 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Phase counting mode Dead time compensation counter function DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture and TCNT overflow or underflow DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture or TCNT overflow or underflow TGR compare match or input capture A/D converter start trigger TGRA_0 compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complement ary PWM mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 436 of 1692 REJ09B0393-0100 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Interrupt sources 7 sources

• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match 0E
• Compare match 0F
• Overflow 4 sources
• Compare match or input capture
• Compare match or input capture
• Overflow
• Underflow 4 sources
• Compare match or input capture
• Compare match or input capture
• Overflow
• Underflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Overflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Overflow or underflow 3 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 437 of 1692 REJ09B0393-0100 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 A/D converter start request delaying function converter start request at a match between TADCOR A_4 and TCNT_4

• A/D converter start request at a match between TADCOR B_4 and TCNT_4 Interrupt skipping function — — — • Skips TGRA_3 compare match interrupts
• Skips TCIV_4 interrupts [Legend] √: Possible —: Not possible

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 439 of 1692 REJ09B0393-0100

11.2 Input/Output Pins

Table 11.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input)

0 TIOC0A I/O TGRA_0 input capture inpu t/output compare output/PWM output pin

TIOC0B I/O TGRB_0 input capture inpu t/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture inpu t/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture inpu t/output compare output/PWM output pin

1 TIOC1A I/O TGRA_1 input capture inpu t/output compare output/PWM output pin

TIOC1B I/O TGRB_1 input capture inpu t/output compare output/PWM output pin

2 TIOC2A I/O TGRA_2 input capture inpu t/output compare output/PWM output pin

TIOC2B I/O TGRB_2 input capture inpu t/output compare output/PWM output pin

3 TIOC3A I/O TGRA_3 input capture inpu t/output compare output/PWM output pin

TIOC3B I/O TGRB_3 input capture inpu t/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture inpu t/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture inpu t/output compare output/PWM output pin

4 TIOC4A I/O TGRA_4 input capture inpu t/output compare output/PWM output pin

TIOC4B I/O TGRB_4 input capture inpu t/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture inpu t/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture inpu t/output compare output/PWM output pin

5 TIC5U Input TGRU_5 input captur e input/external pulse input pin

TIC5V Input TGRV_5 input captur e input/external pulse input pin TIC5W Input TGRW_5 input captur e input/external pulse input pin

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 440 of 1692 REJ09B0393-0100

11.3 Register Descriptions

The MTU2 has the following registers. For details on register addresses and register states during each process, refer to section 30, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 11.3 Register Descriptions Register Name Abbrevia- tion R/W Initial value Address Access Size Timer control register_3 TCR _3 R/W H'00 H'FFFE4200 8, 16, 32 Timer control register_4 TCR_4 R/W H'00 H'FFFE4201 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFE4202 8, 16 Timer mode register_4 TMDR_4 R/W H'00 H'FFFE4203 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFE4204 8, 16, 32 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFE4205 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFE4206 8, 16 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFE4207 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFE4208 8, 16 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFE4209 8 Timer output master enable register TOER R/W H'C0 H'FFFE420A 8 Timer gate control register TGCR R/W H'80 H'FFFE420D 8 Timer output control register 1 TOCR1 R/W H'00 H'FFFE420E 8, 16 Timer output control register 2 TOCR2 R/W H'00 H'FFFE420F 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFE4210 16, 32 Timer counter_4 TCNT _4 R/W H'0000 H'FFFE4212 16 Timer cycle control register TCDR R/W H'FFFF H'FFFE4214 16, 32 Timer dead time data register TDDR R/W H'FFFF H'FFFE4216 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFE4218 16, 32 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFE421A 16 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFE421C 16, 32

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 441 of 1692 REJ09B0393-0100 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFE421E 16 Timer subcounter TCNT S R H'0000 H'FFFE4220 16, 32 Timer cycle buffer register TCBR R/W H'FFFF H'FFFE4222 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFE4224 16, 32 Timer general register D_3 TGRD_3 R/W H'FFFF H'FFFE4226 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFE4228 16, 32 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFE422A 16 Timer status register_3 TSR_3 R/W H'C0 H'FFFE422C 8, 16 Timer status register_4 TSR_4 R/W H'C0 H'FFFE422D 8 Timer interrupt skipping set register TITCR R/W H'00 H'FFFE4230 8, 16 Timer interrupt skipping counter TITCNT R H'00 H'FFFE4231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFE4232 8 Timer dead time enable register TDER R/W H'01 H'FFFE4234 8 Timer output level buffer register TOLBR R/W H'00 H'FFFE4236 8 Timer buffer operation transfer mode register_3 TBTM_3 R/W H'00 H'FFFE4238 8, 16 Timer buffer operation transfer mode register_4 TBTM_4 R/W H'00 H'FFFE4239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFE4240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFE4244 16, 32 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFE4246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFE4248 16, 32 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFE424A 16 Timer waveform control register TWCR R/W H'00 H'FFFE4260 8 Timer start register TSTR R/W H'00 H'FFFE4280 8, 16 Timer synchronous register TSYR R/W H'00 H'FFFE4281 8 Timer counter synchronous start register TCSYSTR R/W H'00 H'FFFE4282 8

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 442 of 1692 REJ09B0393-0100 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer read/write enable register TRWER R/W H'01 H'FFFE4284 8 Timer control register_0 TCR _0 R/W H'00 H'FFFE4300 8, 16, 32 Timer mode register_0 TMDR_0 R/W H'00 H'FFFE4301 8 Timer I/O control registerH_0 TIORH_0 R/W H'00 H'FFFE4302 8, 16 Timer I/O control registerL_0 TIORL_0 R/W H'00 H'FFFE4303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFE4304 8, 16, 32 Timer status register_0 TSR_0 R/W H'C0 H'FFFE4305 8 Timer counter_0 TCNT _0 R/W H'0000 H'FFFE4306 16 Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFE4308 16, 32 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFE430A 16 Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFE430C 16, 32 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFE430E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFE4320 16, 32 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFE4322 16 Timer interrupt enable register2_0 TIER2_0 R/W H'00 H'FFFE4324 8, 16 Timer status register2_0 TSR2_0 R/W H'C0 H'FFFE4325 8 Timer buffer operation transfer mode register_0 TBTM_0 R/W H'00 H'FFFE4326 8 Timer control register_1 T CR_1 R/W H'00 H'FFFE4380 8, 16 Timer mode register_1 TMDR_1 R/W H'00 H'FFFE4381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFE4382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFE4384 8, 16, 32 Timer status register_1 TSR_1 R/W H'C0 H'FFFE4385 8 Timer counter_1 TCNT _1 R/W H'0000 H'FFFE4386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFE4388 16, 32

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 443 of 1692 REJ09B0393-0100 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFE438A 16 Timer input capture control register TICCR R/W H'00 H'FFFE4390 8 Timer control register_2 T CR_2 R/W H'00 H'FFFE4000 8, 16 Timer mode register_2 TMDR_2 R/W H'00 H'FFFE4001 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFE4002 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFE4004 8, 16, 32 Timer status register_2 TSR_2 R/W H'C0 H'FFFE4005 8 Timer counter_2 TCNT _2 R/W H'0000 H'FFFE4006 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFE4008 16, 32 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFE400A 16 Timer counter U_5 TCNTU _5 R/W H'0000 H'FFFE4080 16, 32 Timer general register U_5 TGRU_5 R/W H'FFFF H'FFFE4082 16 Timer control register U_5 TCRU_5 R/W H'00 H'FFFE4084 8 Timer I/O control register U_5 TIORU_5 R/W H'00 H'FFFE4086 8 Timer counter V_5 TCNTV _5 R/W H'0000 H'FFFE4090 16, 32 Timer general register V_5 TGRV_5 R/W H'FFFF H'FFFE4092 16 Timer control register V_5 TCRV_5 R/W H'00 H'FFFE4094 8 Timer I/O control register V_5 TIORV_5 R/W H'00 H'FFFE4096 8 Timer counter W_5 TCNTW_5 R/W H'0000 H'FFFE40A0 16, 32 Timer general register W_5 TGRW_5 R/W H'FFFF H'FFFE40A2 16 Timer control register W_5 TCRW_5 R/W H'00 H'FFFE40A4 8 Timer I/O control register W_5 TIORW_5 R/W H'00 H'FFFE40A6 8 Timer status register_5 TSR_5 R/W H'00 H'FFFE40B0 8 Timer interrupt enable register_5 TIER_5 R/W H'00 H'FFFE40B2 8 Timer start register_5 TSTR_5 R/W H'00 H'FFFE40B4 8 Timer compare match clear register TCNTCMPCLR R/W H'00 H'FFFE40B6 8

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 444 of 1692 REJ09B0393-0100

11.3.1 Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W CCLR[2:0] CKEG[1:0] TPSC[2:0] Bit Bit Name Initial Value R/W Description 7 to 5 CCLR[2:0] 000 R/W Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 11.4 and 11.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. MPφ/4 both edges = MPφ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is MPφ/4 or slower. When MPφ/1 or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.6 to 11.10 for details. [Legend] x: Don't care

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 445 of 1692 REJ09B0393-0100 Table 11.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0

Description

0, 3, 4 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture* 1 0 TCNT cleared by TGRD compare match/input capture* channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer re gister, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 1, 2 0 0 0 TCNT clearing disabled 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is select ed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 446 of 1692 REJ09B0393-0100 Table 11.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 0 0 0 0 Internal clock: counts on P φ/1

1 Internal clock: counts on P φ/4

1 0 Internal clock: counts on P φ/16

1 Internal clock: counts on P φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Table 11.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 1 0 0 0 Internal clock: counts on P φ/1 1 0 Internal clock: counts on P φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on P φ/256

1 Counts on TCNT_2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 447 of 1692 REJ09B0393-0100 Table 11.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 2 0 0 0 Internal clock: counts on P φ/1 1 0 Internal clock: counts on P φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on P φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 3, 4 0 0 0 Internal clock: counts on P φ/1 1 0 Internal clock: counts on P φ/16 1 0 0 Internal clock: counts on P φ/256 1 0 External clock: counts on TCLKA pin input

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 448 of 1692 REJ09B0393-0100 Table 11.10 TPSC1 and TPSC0 (Channel 5) Channel Bit 1 TPSC1 Bit 0 TPSC0 5 0 0 Internal clock: counts on P φ/1 1 0 Internal clock: counts on P φ/16 Note: Bits 7 to 2 are reserved in channel 5. T hese bits are always read as 0. The write value should always be 0.

11.3.2 Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 R R/W R/W R/W R/W R/W R/W R/W - BFE BFB BFA MD[3:0] Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 BFE 0 R/W Buffer Operation E

Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. TGRF compare match is generated when TGRF is used as the buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 449 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated in a mode other than complementary PWM. TGRD compare match is generated in complementary PWM mode. When compare match occurs during the Tb period in complementary PWM mode, TGFD is set. Therefore, set the TGIED bit in the timer interrupt enable register 3/4 (TIER_3/4) to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated in a mode other than complementary PWM. TGRC compare match is generated when in complementary PWM mode. When compare match for channel 4 occurs during the Tb period in complementary PWM mode, TGFC is set. Therefore, set the TGIEC bit in the timer interrupt enable register 4 (TIER_4) to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 11.11 for details.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 450 of 1692 REJ09B0393-0100 Table 11.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0

1 Setting prohibited

1 PWM mode 2 *

1 0 0 Phase counting mode 1 *

1 Phase counting mode 2 *

1 0 Phase counting mode 3 *

1 Phase counting mode 4 *

1 0 0 0 Reset synchronous PWM mode *

1 X Setting prohibited

1 Complementary PWM mode 1 (transmit at crest) *

1 0 Complementary PWM mode 2 (transmit at trough) *

1 Complementary PWM mode 2 (transmit at crest and

trough)* [Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 451 of 1692 REJ09B0393-0100

11.3.3 Timer I/O Cont rol Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOB[3:0] IOA[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: Table 11.12 TIOR_1: Table 11.14 TIOR_2: Table 11.15 TIORH_3: Table 11.16 TIORH_4: Table 11.18 3 to 0 IOA[3:0] 0000 R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: Table 11.20 TIOR_1: Table 11.22 TIOR_2: Table 11.23 TIORH_3: Table 11.24 TIORH_4: Table 11.26

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 452 of 1692 REJ09B0393-0100

• TIORL_0, TIORL_3, TIORL_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOD[3:0] IOC[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 11.13 TIORL_3: Table 11.17 TIORL_4: Table 11.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 11.21 TIORL_3: Table 11.25 TIORL_4: Table 11.27
• TIORU_5, TIORV_5, TIORW_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R/W R/W R/W R/W R/W - - - IOC[4:0] Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 11.28.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 453 of 1692 REJ09B0393-0100 Table 11.12 TIORH_0 (Channel 0) TGRB_0 Function TIOC0B Pin Function

0 Output retained * 0

1 Initial output is 0

0 Initial output is 0

Toggle output at compare match 0 0 Output retained

1 Initial output is 1

0 Initial output is 1

Toggle output at compare match

0 Input capture at rising edge 0

1 Input capture at falling edge

1 X Input capture at both edges

1 X X

Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 454 of 1692 REJ09B0393-0100 Table 11.13 TIORL_0 (Channel 0) TGRD_0 Function TIOC0D Pin Function 0 0 0 0 Output retained * register* Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 455 of 1692 REJ09B0393-0100 Table 11.14 TIOR_1 (Channel 1) TGRB_1 Function TIOC1B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 456 of 1692 REJ09B0393-0100 Table 11.15 TIOR_2 (Channel 2) TGRB_2 Function TIOC2B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match

1 X 0 0 Input capture at rising edge

Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 457 of 1692 REJ09B0393-0100 Table 11.16 TIORH_3 (Channel 3) TGRB_3 Function TIOC3B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 458 of 1692 REJ09B0393-0100 Table 11.17 TIORL_3 (Channel 3) TGRD_3 Function TIOC3D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match register* Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on rese t, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 459 of 1692 REJ09B0393-0100 Table 11.18 TIORH_4 (Channel 4) TGRB_4 Function TIOC4B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 460 of 1692 REJ09B0393-0100 Table 11.19 TIORL_4 (Channel 4) TGRD_4 Function TIOC4D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match register* Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 461 of 1692 REJ09B0393-0100 Table 11.20 TIORH_0 (Channel 0) TGRA_0 Function TIOC0A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 462 of 1692 REJ09B0393-0100 Table 11.21 TIORL_0 (Channel 0) TGRC_0 Function TIOC0C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 463 of 1692 REJ09B0393-0100 Table 11.22 TIOR_1 (Channel 1) TGRA_1 Function TIOC1A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 464 of 1692 REJ09B0393-0100 Table 11.23 TIOR_2 (Channel 2) TGRA_2 Function TIOC2A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 465 of 1692 REJ09B0393-0100 Table 11.24 TIORH_3 (Channel 3) TGRA_3 Function TIOC3A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 466 of 1692 REJ09B0393-0100 Table 11.25 TIORL_3 (Channel 3) TGRC_3 Function TIOC3C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match register* Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 467 of 1692 REJ09B0393-0100 Table 11.26 TIORH_4 (Channel 4) TGRA_4 Function TIOC4A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 468 of 1692 REJ09B0393-0100 Table 11.27 TIORL_4 (Channel 4) TGRC_4 Function TIOC4C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match register* Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 469 of 1692 REJ09B0393-0100 Table 11.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function 0 0 0 0 0 Compare match

1 X X Setting prohibited

1 X X X

1 0 0 0 0 Setting prohibited

1 Input capture at rising edge

1 0 Input capture at falling edge

1 Input capture at both edges

1 0 0 0 Setting prohibited

1 Measurement of low pulse width of external input signal

Capture at trough in complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest in complementary PWM mode Capture at crest and trough in complementary PWM mode 1 0 0 Setting prohibited

1 Measurement of high pulse width of external input

Capture at trough in complementary PWM mode 1 0 Measurement of high pulse width of external input signal Capture at crest in complementary PWM mode Input capture register Measurement of high pulse width of external input signal Capture at crest and trough in complementary PWM mode [Legend] X: Don't care

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 470 of 1692 REJ09B0393-0100

11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR)

TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- CMP CLR5U CMP CLR5V CMP CLR5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMPCLR5U 0 R/W TCNT Compare Clear 5U

Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture

1 CMPCLR5V 0 R/W TCNT Compare Clear 5V

Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 471 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 CMPCLR5W 0 R/W TCNT Compare Clear 5W

Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture

11.3.5 Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5.

• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 76543210Bit: Initial value: R/W: 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Bit Bit Name Initial Value R/W Description

7 TTGE 0 R/W A/D Converter Start Request Enable

Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 472 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

6 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 473 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 474 of 1692 REJ09B0393-0100

• TIER2_0 Bit: Initial value: R/W: 7654321 0 00000000 R/W R R R R R R/W R/W TTGE2 - - - - - TGIEF TGIEE Bit Bit Name Initial Value R/W Description

7 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGIEF 0 R/W TGR Interrupt Enable F

Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled

0 TGIEE 0 R/W TGR Interrupt Enable E

Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 475 of 1692 REJ09B0393-0100

• TIER_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- TGIE5U TGIE5V TGIE5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TGIE5U 0 R/W TGR Interrupt Enable 5U

Enables or disables interrupt requests (TGIU_5) by the CMFU5 bit when this bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled

1 TGIE5V 0 R/W TGR Interrupt Enable 5V

Enables or disables interrupt requests (TGIV_5) by the CMFV5 bit when this bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled

0 TGIE5W 0 R/W TGR Interrupt Enable 5W

Enables or disables interrupt requests (TGIW_5) by the CMFW5 bit when this bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 476 of 1692 REJ09B0393-0100

11.3.6 Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.

• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 7654321 0 R R R/(W) *1R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1 11000000 Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1. TCFD - TCFU TCFV TGFD TGFC TGFB TGFA Bit Bit Name Initial Value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

5 TCFU 0 R/(W) *

Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]

• When 0 is written to TCFU after reading TCFU = 1* [Setting condition]
• When the TCNT value underflows (changes from H'0000 to H'FFFF)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 477 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

4 TCFV 0 R/(W) *

Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Clearing condition]

• When 0 is written to TCFV after reading TCFV = 1* [Setting condition]
• When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set.

3 TGFD 0 R/(W) *

Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]

• When 0 is written to TGFD after reading TGFD = 1*
• When DTC is activated by TGID interrupt, and the DISEL bit of MRB in DTC is cleared to 0. [Setting conditions]
• When TCNT = TGRD and TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 478 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 TGFC 0 R/(W) *

Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]

• When DTC is activated by TGIC interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFC after reading TGFC = 1* [Setting conditions]
• When TCNT = TGRC and TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register

1 TGFB 0 R/(W) *

Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition]

• When DTC is activated by TGIB interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFB after reading TGFB = 1* [Setting conditions]
• When TCNT = TGRB and TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 479 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 TGFA 0 R/(W) *

Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Clearing conditions]

• When DMAC is activated by TGIA interrupt.
• When DTC is activated by TGIA interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFA after reading TGFA = 1* [Setting conditions]
• When TCNT = TGRA and TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. After reading 1, when the next flag set is generated before writing 0, the flag will not be cleared by writing 0. Read 1 again and write 0 in this case.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 480 of 1692 REJ09B0393-0100

• TSR2_0 Bit: Initial value: R/W: 7654321 0 11000000 RRRRRR Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. R/(W)*1 R/(W)*1 - - - - - - TGFF TGFE Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGFF 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Clearing condition]

• When 0 is written to TGFF after reading TGFF = 1* [Setting condition]
• When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register

0 TGFE 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Clearing condition]

• When 0 is written to TGFE after reading TGFE = 1* [Setting condition]
• When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. After reading 1 when the next flag set is generated before writing 0, the flag will not be cleared by writing 0. Read 1 again and write 0 in this case.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 481 of 1692 REJ09B0393-0100

• TSR_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/(W) *1 R/(W)*1R/(W)*1 Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1. - - - - - CMFU5 CMFV5 CMFW5 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMFU5 0 R/(W) *

Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Clearing condition]

• When DTC is activated by TGIU_5 interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to CMFU5 after reading CMFU5 = 1 [Setting conditions]
• When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register
• When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control registers U_5, V_5, and W_5 (TIORU_5, TIORV_5, and TIORW_5).*

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 482 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

1 CMFV5 0 R/(W) *

Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Clearing condition]

• When DTC is activated by TGIV_5 interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to CMFV5 after reading CMFV5 = 1 [Setting conditions]
• When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register
• When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control registers U_5, V_5, and W_5 (TIORU_5, TIORV_5, and TIORW_5).*

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 483 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 CMFW5 0 R/(W) *

Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. Only 0 can be written to clear this flag. [Clearing condition]

• When DTC is activated by TGIW_5 interrupt, and the DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to CMFW5 after reading CMFW5 = [Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register
• When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal. * Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Timing for transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5 (TIORU_5/V_5/W_5).

11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)

The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- TTSE TTSB TTSA

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 484 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TTSE 0 R/W Timing Select E

Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. When channel 0 is used in a mode other than PWM mode, do not set this bit to 1. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared

1 TTSB 0 R/W Timing Select B

Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When the channel is used in a mode other than PWM mode, do not set this bit to 1. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel

0 TTSA 0 R/W Timing Select A

Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When the channel is used in a mode other than PWM mode, do not set this bit to 1. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 485 of 1692 REJ09B0393-0100

11.3.8 Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R/W R/W R/W R/W ---- I2BE I2AE I1BE I1AE Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 I2BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions

2 I2AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions

1 I1BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 486 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 I1AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions

11.3.9 Timer Synchronous Clear Register (TSYCR)

TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in channel 3 but the MTU2 has no TSYCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Bit Bit Name Initial Value R/W Description

7 CE0A 0 R/W Clear Enable 0A

Enables or disables counter clearing when the TGFA flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_0 1: Enables counter clearing by the TGFA flag in TSR_0

6 CE0B 0 R/W Clear Enable 0B

Enables or disables counter clearing when the TGFB flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_0 1: Enables counter clearing by the TGFB flag in TSR_0

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 487 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 CE0C 0 R/W Clear Enable 0C

Enables or disables counter clearing when the TGFC flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFC flag in TSR_0 1: Enables counter clearing by the TGFC flag in TSR_0

4 CE0D 0 R/W Clear Enable 0D

Enables or disables counter clearing when the TGFD flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFD flag in TSR_0 1: Enables counter clearing by the TGFD flag in TSR_0

3 CE1A 0 R/W Clear Enable 1A

Enables or disables counter clearing when the TGFA flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_1 1: Enables counter clearing by the TGFA flag in TSR_1

2 CE1B 0 R/W Clear Enable 1B

Enables or disables counter clearing when the TGFB flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_1 1: Enables counter clearing by the TGFB flag in TSR_1

1 CE2A 0 R/W Clear Enable 2A

Enables or disables counter clearing when the TGFA flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_2 1: Enables counter clearing by the TGFA flag in TSR_2

0 CE2B 0 R/W Clear Enable 2B

Enables or disables counter clearing when the TGFB flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_2 1: Enables counter clearing by the TGFB flag in TSR_2

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 488 of 1692 REJ09B0393-0100

11.3.10 Timer A/D Converter Start Request Control Register (TADCR)

TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 000000000 0 * 00 * 0* 0* 0* 0* R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Note: Do not set to 1 when complementary PWM mode is not selected.* BF[1:0] - - - - - - UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 11.29. 13 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 UT4AE 0 R/W Up-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation

6 DT4AE 0 * R/W Down-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 489 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 UT4BE 0 R/W Up-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation

4 DT4BE 0 * R/W Down-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation

3 ITA3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

2 ITA4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping

1 ITB3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 490 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 ITB4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabl ed while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 11.29 Setting of Transfer Timing by Bits BF1 and BF0 Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.* 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.* 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set bu ffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when co mplementary PWM mode is not selected.

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11.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and

TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4

and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 492 of 1692 REJ09B0393-0100

11.3.13 Timer Counter (TCNT)

The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.

11.3.14 Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF .

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 493 of 1692 REJ09B0393-0100

11.3.15 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

• TSTR Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W CST4 CST3 - - - CST2 CST1 CST0 Bit Bit Name Initial Value R/W Description

7 CST4 0 R/W

6 CST3 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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2 CST2 0 R/W

1 CST1 0 R/W

0 CST0 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation

• TSTR_5 Bit : Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- CSTU5 CSTV5 CSTW5 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CSTU5 0 R/W Counter Start U5

Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation

1 CSTV5 0 R/W Counter Start V5

Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation

0 CSTW5 0 R/W Counter Start W5

Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 495 of 1692 REJ09B0393-0100

11.3.16 Timer Synchronous Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W SYNC4 SYNC3 - - - SYNC2 SYNC1 SYNC0 Bit Bit Name Initial Value R/W Description

7 SYNC4 0 R/W

6 SYNC3 0 R/W

Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 496 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 SYNC2 0 R/W

1 SYNC1 0 R/W

0 SYNC0 0 R/W

Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 497 of 1692 REJ09B0393-0100

11.3.17 Timer Counter Synchronous Start Register (TCSYSTR)

TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and MTU2S counters. Note that the MTU2S does not have TCSYSTR. Bit: Initial value: R/W: 7654321 0 00000000 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W) * R/(W)* Note: Only 1 can be written to set the register.* SCH0 SCH1 SCH2 SCH3 SCH4 - SCH3S SCH4S Bit Bit Name Initial Value R/W Description

7 SCH0 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition]

• When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1

6 SCH1 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition]

• When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 498 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 SCH2 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition]

• When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1

4 SCH3 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition]

• When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1

3 SCH4 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition]

• When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1 2 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

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1 SCH3S 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_3S in the MTU2S. 0: Does not specify synchronous start for TCNT_3S in the MTU2S 1: Specifies synchronous start for TCNT_3S in the MTU2S [Clearing condition]

• When 1 is set to the CST3 bit of TSTRS in MTU2S while SCH3S = 1

0 SCH4S 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_4S in the MTU2S. 0: Does not specify synchronous start for TCNT_4S in the MTU2S 1: Specifies synchronous start for TCNT_4S in the MTU2S [Clearing condition]

• When 1 is set to the CST4 bit of TSTRS in MTU2S while SCH4S = 1 Note: Only 1 can be written to set the register.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 500 of 1692 REJ09B0393-0100

11.3.18 Timer Read/Write Enable Register (TRWER)

TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / W Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 RWE 1 R/W Read/Write Enable

Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition]

• When 0 is written to the RWE bit after reading RWE = 1
• Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 501 of 1692 REJ09B0393-0100

11.3.19 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit: Initial value: R/W: 7654321 0 11000000 R R R/W R/W R/W R/W R/W R/W - - OE4D OE4C OE3D OE4B OE4A OE3B Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1.

5 OE4D 0 R/W Master Enable TIOC4D

This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

4 OE4C 0 R/W Master Enable TIOC4C

This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

3 OE3D 0 R/W Master Enable TIOC3D

This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

2 OE4B 0 R/W Master Enable TIOC4B

This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

1 OE4A 0 R/W Master Enable TIOC4A

This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 502 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 OE3B 0 R/W Master Enable TIOC3B

This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the se ttings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 11.3.20, Timer Output Control Register 1 (TOCR1), and section 11.3.21, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or reset- synchronized PWM mode. When these bits are set to 0, low level is output.

11.3.20 Timer Output Control Register 1 (TOCR1)

TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7654321 0 00000000 R R/W R R R/(W) * R/W R/W R/W Note: This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.* - PSYE - - TOCL TOCS OLSN OLSP Bit Bit Name Initial value R/W Description 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 PSYE 0 R/W PWM Synchronous Output Enable

This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 503 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

3 TOCL 0 R/(W) * TOC Register Write Protection *

This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled

2 TOCS 0 R/W TOC Select

This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected

1 OLSN 0 R/W Output Level Select N *

This bit selects the reverse phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 11.30.

0 OLSP 0 R/W Output Level Select P *

This bit selects the positive phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 11.31. Notes: 1. Setting the TOCL bit to 1 prevents acci dental modification when the CPU goes out of control. 2. Clearing the TOCS0 bit to 0 makes this bit setting valid. Table 11.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count

0 High level Low level High level Low level

1 Low level High level Low level High level

Note: The reverse phase waveform initial output val ue changes to active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 504 of 1692 REJ09B0393-0100 Table 11.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count

0 High level Low level Low level High level

1 Low level High level High level Low level

Figure 11.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TGRA_4 TDDR H'0000 Time TCNT_4 TCNT_3 Positive phase output Reverse phase output Active level Compare match output (up count) Initial output Initial output Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 11.2 Complementary PWM Mode Output Level Example

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 505 of 1692 REJ09B0393-0100

11.3.21 Timer Output Control Register 2 (TOCR2)

TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Bu ffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 11.32.

5 OLS3N 0 R/W Output Level Select 3N *

This bit selects the output level on TIOC4D in reset- synchronized PWM mode/complementary PWM mode. See table 11.33.

4 OLS3P 0 R/W Output Level Select 3P *

This bit selects the output level on TIOC4B in reset- synchronized PWM mode/complementary PWM mode. See table 11.34.

3 OLS2N 0 R/W Output Level Select 2N *

This bit selects the output level on TIOC4C in reset- synchronized PWM mode/complementary PWM mode. See table 11.35.

2 OLS2P 0 R/W Output Level Select 2P *

This bit selects the output level on TIOC4A in reset- synchronized PWM mode/complementary PWM mode. See table 11.36.

1 OLS1N 0 R/W Output Level Select 1N *

This bit selects the output level on TIOC3D in reset- synchronized PWM mode/complementary PWM mode. See table 11.37.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 506 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

0 OLS1P 0 R/W Output Level Select 1P *

This bit selects the output level on TIOC3B in reset- synchronized PWM mode/complementary PWM mode. See table 11.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 11.32 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode Reset-Synchronized PWM Mode 0 0 Does not transfer data from the buffer register (TOLBR) to TOCR2. Does not transfer data from the buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Table 11.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output va lue changes to the active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 507 of 1692 REJ09B0393-0100 Table 11.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count Down Count Table 11.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output va lue changes to the active level after elapse of the dead time after count start. Table 11.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count Table 11.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output va lue changes to the active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 508 of 1692 REJ09B0393-0100 Table 11.38 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count Down Count

11.3.22 Timer Output Level Buffer Register (TOLBR)

TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R R R/W R/W R/W R/W R/W R/W - - OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

5 OLS3N 0 R/W Specifies the buffer value to be transferred to the

OLS3N bit in TOCR2.

4 OLS3P 0 R/W Specifies the buffer value to be transferred to the

OLS3P bit in TOCR2.

3 OLS2N 0 R/W Specifies the buffer value to be transferred to the

OLS2N bit in TOCR2.

2 OLS2P 0 R/W Specifies the buffer value to be transferred to the

OLS2P bit in TOCR2.

1 OLS1N 0 R/W Specifies the buffer value to be transferred to the

OLS1N bit in TOCR2.

0 OLS1P 0 R/W Specifies the buffer value to be transferred to the

OLS1P bit in TOCR2.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 509 of 1692 REJ09B0393-0100 Figure 11.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS Set TOCR2 Set TOLBR [1] [2] [3] [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Figure 11.3 PWM Output Level Setting Procedure in Buffer Operation

11.3.23 Timer Gate Control Register (TGCR)

TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/reset- synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 10000000 R R/W R/W R/W R/W R/W R/W R/W - BDC N P FB WF VF UF Bit Bit Name Initial value R/W Description 7 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

6 BDC 0 R/W Brushless DC Motor

This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 510 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

5 N 0 R/W Reverse Phase Output (N) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

4 P 0 R/W Positive Phase Output (P) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

3 FB 0 R/W External Feedback Signal Enable

This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (setting values of UF, VF, and WF in TGCR).

2 WF 0 R/W

1 VF 0 R/W

0 UF 0 R/W

Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 11.39.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 511 of 1692 REJ09B0393-0100 Table 11.39 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF

1 ON OFF OFF OFF OFF ON

1 OFF ON OFF OFF OFF ON

1 0 0 OFF OFF ON OFF ON OFF

1 ON OFF OFF OFF ON OFF

1 OFF OFF OFF OFF OFF OFF

11.3.24 Timer Subcounter (TCNTS)

TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 512 of 1692 REJ09B0393-0100

11.3.25 Timer Dead Time Data Register (TDDR)

TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.

11.3.26 Timer Cycle Data Register (TCDR)

TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 513 of 1692 REJ09B0393-0100

11.3.27 Timer Cycle Buffer Register (TCBR)

TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.

11.3.28 Timer Interrupt Skipping Set Register (TITCR)

TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] Bit Bit Name Initial value R/W Description

7 T3AEN 0 R/W T3AEN

Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W T hese bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 11.40.

3 T4VEN 0 R/W T4VEN

Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 514 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description 2 to 0 4VCOR[2:0] 000 R/W T hese bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 11.41. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TICNT). Table 11.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 11.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 515 of 1692 REJ09B0393-0100

11.3.29 Timer Interrupt Skipping Counter (TITCNT)

TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRRR - 3ACNT[2:0] - 4VCNT[2:0] Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions]

• When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR
• When the T3AEN bit in TITCR is cleared to 0
• When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 — 0 R Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions]
• When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR
• When the T4VEN bit in TITCR is cleared to 0
• When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the bi ts T3AEN and T4VEN in TITCR to 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 516 of 1692 REJ09B0393-0100

11.3.30 Timer Buffer Transfer Set Register (TBTER)

TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRR R / W R / W Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W Thes e bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 11.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 517 of 1692 REJ09B0393-0100 Table 11.42 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer r egisters to the temporary registers* and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer r egisters to the temporary registers. 1 0 Links transfer from the buffer regi sters to the temporary registers with interrupt skipping operation.* 1 1 Setting prohibited Note: 1. Data is transferred acco rding to the MD3 to MD0 bit setting in TMDR. For details, refer to section 11.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 518 of 1692 REJ09B0393-0100

11.3.31 Timer Dead Time Enable Register (TDER)

TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / ( W ) Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 TDER 1 R/(W) Dead Time Enable

Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition]

• When 0 is written to TDER after reading TDER = 1 Note: * TDDR must be set to 1 or a larger value.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 519 of 1692 REJ09B0393-0100

11.3.32 Timer Waveform Control Register (TWCR)

TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 Note: Do not set to 1 when complementary PWM mode is not selected.* 0* 0000000 R/(W) R R R R R R/(W) R/(W) C C E ----- S C C W R E Bit Bit Name Initial Value R/W Description

7 CCE 0 * R/(W) Compare Match Clear Enable

Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition]

• When 1 is written to CCE after reading CCE = 0 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 520 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

1 SCC 0 R/(W) Synchronous Clearing Control

Specifies whether to clear TCNT_3 and TCNT_4 in the MTU2S when synchronous counter clearing between the MTU2 and MTU2S occurs in complementary PWM mode. When using this control, place the MTU2S in complementary PWM mode. When modifying the SCC bit while the counters are operating, do not modify the CCE or WRE bits. Counter clearing synchronized with the MTU2 is disabled by the SCC bit setting only when synchronous clearing occurs outside the Tb interval at the trough. When synchronous clearing occurs in the Tb interval at the trough including the period immediately after TCNT_3 and TCNT_4 start operation, TCNT_3 and TCNT_4 in the MTU2S are cleared. For the Tb interval at the trough in complementary PWM mode, see figure 11.40. In the MTU2, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: Enables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation 1: Disables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation [Setting condition]

• When 1 is written to SCC after reading SCC = 0

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 521 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 WRE 0 R/(W) Waveform Retain Enable

Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 11.40. 0: Outputs the initial value specified in TOCR 1: Retains the waveform output immediately before synchronous clearing [Setting condition]

• When 1 is written to WRE after reading WRE = 0 Note: * Do not set to 1 when complementary PWM mode is not selected.

11.3.33 Bus Master Interface

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8- bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 522 of 1692 REJ09B0393-0100

11.4 Operation

11.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). (1) Counter Operation When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure Figure 11.4 shows an example of the count operation setting procedure. Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free-running counter Start count operation <Free-running counter> <Periodic counter> Start count operation [1] [2] [3] [4] [5] [5] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 11.4 Example of Counter Operation Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 528 of 1692 REJ09B0393-0100

11.4.2 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 11.12 shows an example of the synchronous operation setting procedure. No Yes Set synchronous operation <Synchronous presetting> <Counter clearing> <Synchronous clearing> Clearing source generation channel? Select counter clearing source Start count Set synchronous counter clearing Start count [1] [3] [5] [4] [5] [2] Synchronous operation selection [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Set TCNT Synchronous presetting Synchronous clearing Figure 11.12 Example of Synchronous Operation Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 530 of 1692 REJ09B0393-0100

11.4.3 Buffer Operation

Buffer operation, provided for channels 0, 3, and 4 enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designat ed as an input capture register and can only operate as a compare match register. Table 11.43 shows the register combinations used in buffer operation. Table 11.43 Register Combinations in Buffer Operation Channel Timer General Re gister Buffer Register

0 TGRA_0 TGRC_0

TGRB_0 TGRD_0 TGRE_0 TGRF_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3

4 TGRA_4 TGRC_4

TGRB_4 TGRD_4

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.14. Buffer register Timer general register TCNTComparator Compare match signal Figure 11.14 Compare Match Buffer Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 534 of 1692 REJ09B0393-0100 TCNT_0 value H'0000 TGRA_0 Time TIOCA TGRC_0 H'0520 H'0520 H'0450 H'0450 H'0200 H'0520H'0450H'0200 H'0200 TGRB_0 TGRA_0 Transfer Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing

11.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase counting mode. Table 11.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 11.44 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 539 of 1692 REJ09B0393-0100

11.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.

• PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.46.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 540 of 1692 REJ09B0393-0100 Table 11.46 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TGRB_0 TIOC0A TIOC0B TGRC_0 TIOC0C TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A 1 TGRB_1 TIOC1A TIOC1B TGRA_2 TIOC2A 2 TGRB_2 TIOC2A TIOC2B TGRA_3 Cannot be set TGRB_3 TIOC3A Cannot be set TGRC_3 Cannot be set TGRD_3 TIOC3C Cannot be set TGRA_4 Cannot be set TGRB_4 TIOC4A Cannot be set TGRC_4 Cannot be set TGRD_4 TIOC4C Cannot be set Note: In PWM mode 2, PWM output is not possible fo r the TGR register in which the period is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 544 of 1692 REJ09B0393-0100

11.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 11.47 shows the correspondence between external clock pins and channels. Table 11.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 11.29 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 11.29 Example of Phase Counting Mode Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 549 of 1692 REJ09B0393-0100 (3) Phase Counting Mode Application Example Figure 11.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 550 of 1692 REJ09B0393-0100 TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed period capture) TGRA_0 (speed control period) TGRB_1 (position period capture) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 11.34 Phase Counting Mode Application Example

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 551 of 1692 REJ09B0393-0100

11.4.7 Reset-Synchronized PWM Mode

In reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 11.52 shows the PWM output pins used. Table 11.53 shows the settings of the registers. Table 11.52 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description

3 TIOC3B PWM output pin 1

TIOC3D PWM output pin 1' (negativ e-phase waveform of PWM output 1)

4 TIOC4A PWM output pin 2

TIOC4C PWM output pin 2' (negativ e-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negativ e-phase waveform of PWM output 3) Table 11.53 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM wavefo rm output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM wavefo rm output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM wavefo rm output by the TIOC4B and TIOC4D pins

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 554 of 1692 REJ09B0393-0100

11.4.8 Complementary PWM Mode

In complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without non- overlapping interval are also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 11.54 shows the PWM output pins used. Table 11.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 11.54 Output Pins for Complementary PWM Mode Channel Output Pin Description

3 TIOC3A Toggle output synchroni zed with PWM period (or I/O port)

TIOC3C I/O port * TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) Note: * Avoid setting the TIOC3C pin as a ti mer I/O pin in complementary PWM mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 555 of 1692 REJ09B0393-0100 Table 11.55 Register Settings for Complementary PWM Mode Channel Counter/Register Descri ption Read/Write from CPU

3 TCNT_3 Start of up-count from value set

setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable

4 TCNT_4 Up-count start, initialized to

H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register).

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 556 of 1692 REJ09B0393-0100 TGRC_3 TDDR TCNT_3 TGRD_3 TGRD_4TGRC_4 TGRB_3 Temp 1 TGRA_4 Temp 2 TGRB_4 Temp 3 TCNTS TCNT_4 TGRA_3 TCDR TCBR Comparator Comparator Match signal Match signal Output controller Output protection circuit PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE2 POE3 External cutoff input External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) TGRA_3 compare- match interrupt TCNT_4 underflow interrupt Figure 11.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 557 of 1692 REJ09B0393-0100 (1) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 11.38. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting TCNT setting Inter-channel synchronization setting TGR setting Enable/disable dead time generation Start count operation [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2-CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 10.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting Enable waveform output Start count operation <Complementary PWM mode> [10] PFC setting [12] [13] Figure 11.38 Example of Complementary PWM Mode Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 558 of 1692 REJ09B0393-0100 (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 11.39 illustrates counter operation in complementary PWM mode, and figure 11.40 shows an example of complementary PWM mode operation. (a) Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 559 of 1692 REJ09B0393-0100 Counter value TGRA_3 TCDR TDDR H'0000 TCNT_4 TCNTS TCNT_3 TCNT_3 TCNT_4 TCNTS Time Figure 11.39 Complementary PWM Mode Counter Operation (b) Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 11.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (tb1 in figure 11.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 560 of 1692 REJ09B0393-0100 with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS— and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 561 of 1692 REJ09B0393-0100 TGRA_3 TCDR TGRA_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS (Output waveform is active-low) H'6400 H'0080 H'6400 H'6400 H'0080 H'0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 11.40 Example of Complementary PWM Mode Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 562 of 1692 REJ09B0393-0100 (c) Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 11.56 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 563 of 1692 REJ09B0393-0100 (d) PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6- phase output. Complementary PWM mode should be cleared before setting or changing output levels. (e) Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. (f) Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 11.41 shows an example of operation without dead time.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 564 of 1692 REJ09B0393-0100 TGRA_3=TCDR+1 TCDR TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Initial output Initial output T a Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active-low. Data1 Data2 Data1 Data2 Data1 Data2 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 11.41 Example of Operation without Dead Time

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 565 of 1692 REJ09B0393-0100 (g) PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 11.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TGRA_3 TCNT_3 TCNT_4 Time Figure 11.42 Example of PWM Cycle Updating

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 566 of 1692 REJ09B0393-0100 (h) Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 567 of 1692 REJ09B0393-0100 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6Temp_R GR Time : Compare register : Buffer register Figure 11.43 Example of Data Update in Complementary PWM Mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 568 of 1692 REJ09B0393-0100 (i) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 11.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 11.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Dead time Time Active level Active level TCNT_3, 4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 11.44 Example of Initial Output in Complementary PWM Mode (1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 569 of 1692 REJ09B0393-0100 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3, 4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 11.45 Example of Initial Output in Complementary PWM Mode (2)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 570 of 1692 REJ09B0393-0100 (j) Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non- overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 11.46 to 11.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as shown in figure 11.46. If compare-matches deviate from the a → b → c → d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 11.47, compare- match b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 11.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 575 of 1692 REJ09B0393-0100 (k) Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 11.49 to 11.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. (l) Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 11.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 H'0000 Toggle output TIOC3A pin TCNT_4 TCNT_3 Figure 11.54 Example of Toggle Output Waveform Synchronized with PWM Output

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 577 of 1692 REJ09B0393-0100 (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 11.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 11.56) immediately after the counters start operation, initial value output is not suppressed. This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2 can cause counter clearing. Tb intervalTb interval Tb interval TGRA_3 TGRB_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low Counter start Figure 11.56 Timing for Synchronous Counter Clearing

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 578 of 1692 REJ09B0393-0100

• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 11.57. Stop count operation Output waveform control at synchronous counter clearing Set TWCR and complementary PWM mode Start count operation Output waveform control at synchronous counter clearing [1] [2] [3] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Figure 11.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode
• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 11.58 to 11.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 11.58 to 11.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56, respectively. In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in complementary PWM mode and synchronous counter clearing is generated while the SCC bit is cleared to 0 and the WRE bit is set to 1 in TWCR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 579 of 1692 REJ09B0393-0100 TGRA_3 TGRB_3 TCDR TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Synchronous clearing TCNT_3 (MTU2) TCNT_4 (MTU2) Bit WRE = 1 Figure 11.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 11.56; Bit WRE of TWCR in MTU2 is 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 580 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. Synchronous clearing Bit WRE = 1 TCNT_3 (MTU2) TCNT_4 (MTU2) TGRA_3 TGRB_3 TCDR TDDR H'0000 Figure 11.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 11.56; Bit WRE of TWCR in MTU2 is 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 581 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. Synchronous clearing Bit WRE = 1 TCNT_3 (MTU2) TCNT_4 (MTU2) TGRA_3 TGRB_3 TCDR TDDR H'0000 Figure 11.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 11.56; Bit WRE of TWCR is 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 582 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. Synchronous clearingBit WRE = 1 TGRA_3 TGRB_3 TCDR TDDR H'0000 Initial value output is suppressed. TCNT_3 (MTU2) TCNT_4 (MTU2) Figure 11.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 11.56; Bit WRE of TWCR is 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 583 of 1692 REJ09B0393-0100 (o) Suppressing MTU2-MTU2S Synchronous Counter Clearing In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused by the MTU2. Synchronous counter clearing is suppressed only within the interval shown in figure 11.62. When using this function, the MTU2S should be set to complementary PWM mode. For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter clearing) in section 11.4.10, MTU2-MTU2S Synchronous Operation. Tb interval at the crest Tb interval at the trough Tb interval at the crest Tb interval at the trough TGRA_3 TGRB_3 TCDR TDDR H'0000 Tb interval immediately after counter operation starts MTU2-MTU2S synchronous counter clearing is suppressed. MTU2-MTU2S synchronous counter clearing is suppressed. Figure 11.62 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 584 of 1692 REJ09B0393-0100

• Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing An example of the procedure for suppressing MTU2-MTU2S synchronous counter clearing is shown in figure 11.63. Stop count operation (MTU2 and MTU2S) MTU2-MTU2S synchronous counter clearing suppress Start count operation (MTU2 and MTU2S) Output waveform control at synchronous counter clearing and synchronous counter clearing suppress [1] [3]
• Set the following.
• Complementary PWM mode (MTU2S)
• Compare match/input capture operation (MTU2)
• Bit WRE in TWCR (MTU2S) [2] Set bit SCC in TWCR (MTU2S) [4] [1] Clear bits CST of the timer start register (TSTR) in the MTU2S to 0, and halt count operation. Clear bits CST of TSTR in the MTU2 to 0, and halt count operation. [2] Set the complementary PWM mode in the MTU2S and compare match/input capture operation in the MTU2. When bit WRE in TWCR should be set, make appropriate setting here. [3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start count operation. For MTU2-MTU2S synchronous counter clearing, set bits CST of TSTR in the MTU2 to 1 to start count operation in any one of TCNT_0 to TCNT_2. [4] Read TWCR and then set bit SCC in TWCR to 1 to suppress MTU2-MTU2S synchronous counter clearing*. Here, do not modify the CCE and WRE bit values in TWCR of the MTU2S. MTU2-MTU2S synchronous counter clearing is suppressed in the intervals shown in figure 10.62. Note: * The SCC bit value can be modified during counter operation. However, if a synchronous clearing occurs when bit SCC is modified from 0 to 1, the synchronous clearing may not be suppressed. If a synchronous clearing occurs when bit SCC is modified from 1 to 0, the synchronous clearing may be suppressed. Figure 11.63 Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing
• Examples of Suppression of MTU2-MTU2S Synchronous Counter Clearing Figures 11.64 to 11.67 show examples of operation in which the MTU2S operates in complementary PWM mode and MTU2-MTU2S synchronous counter clearing is suppressed by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 11.64 to 11.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56, respectively. In these examples, the WRE bit in TWCR of the MTU2S is set to 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 585 of 1692 REJ09B0393-0100 TGRA_3 TGRB_3 TCDR TDDR H'0000 Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing TCNT_3 (MTU2S) TCNT_4 (MTU2S) Bit WRE = 1 Bit SCC = 1 Counters are not cleared Figure 11.64 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 586 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 Counters are not cleared TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Figure 11.65 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 587 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 Counters are not cleared TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Figure 11.66 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 588 of 1692 REJ09B0393-0100 Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Counters are cleared Initial value output is suppressed. Figure 11.67 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 590 of 1692 REJ09B0393-0100 (q) Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 11.69 to 11.72 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 11.69 Example of Output Phase Switching by External Input (1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 592 of 1692 REJ09B0393-0100 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 11.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (r) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 596 of 1692 REJ09B0393-0100 Buffer register Temporary register General register TCNT_3 TCNT_4 Data1 Data2 Data* Data2 Data* Data2 (1) (2) (3) Buffer transfer is suppressed Note: * When buffer transfer at the crest is selected. data1 Bit BTE1 in TBTER Bit BTE0 in TBTER (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. [Legend] Figure 11.76 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 597 of 1692 REJ09B0393-0100 TGIA_3 interrupt generation TGIA_3 interrupt generation TGIA_3 interrupt generation TGIA_3 interrupt generation (1) When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt (2) When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt Buffer register rewrite timing Buffer register rewrite timing Buffer register rewrite timing TCNT_4 TCNT_3 TCNT_4 TCNT_3 Buffer transfer-enabled period TITCR[6:4] TITCNT[6:4] Buffer register Temporary register General register Buffer transfer-enabled period TITCR[6:4] TITCNT[6:4] Buffer register Temporary register General register 01201 01201 Data Data Data Data1 Data Data Data Data1 Data1 Data1 Data1 Data1 Data2 Data2 Data2 Note: * Buffer transfer at the crest is selected. The skipping count is set to two. T3AEN is set to 1. Figure 11.77 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 598 of 1692 REJ09B0393-0100 Note: * The skipping count is set to three. Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) 00 1230123 01230123 Skipping counter 3ACNT Skipping counter 4VCNT Figure 11.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period (4) Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. (a) Register and Counter Miswrite Prevention Function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following:

• TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 599 of 1692 REJ09B0393-0100 (b) Halting of PWM Output by External Signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 13, Port Output Enable 2 (POE2), for details. (c) Halting of PWM Output by Oscillation Stop The 6-phase PWM output pins can detect the clock stop and set the output pin automatically to the high-impedance state. However, the pin state is not guaranteed when the clock starts oscillation again. See section 4.7, Oscillation Stop Detection, for details.

11.4.9 A/D Converter Start Request Delaying Function

A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR.

• Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 11.79 shows an example of procedure for specifying the A/D converter start request delaying function.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 600 of 1692 REJ09B0393-0100 Set A/D converter start request cycle A/D converter start request delaying function

• Set the timing of transfer from cycle set buffer register
• Set linkage with interrupt skipping
• Enable A/D converter start request delaying function A/D converter start request delaying function [1] [2] [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register.
• Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 11.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 602 of 1692 REJ09B0393-0100 Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TADCORA_4 TCNT_4 A/D converter start request (TRG4AN) Note: * When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping 00 01 00 01 02 00 01 00 01 02 (UT4AE/DT4AE = 1) Figure 11.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 603 of 1692 REJ09B0393-0100 A/D converter start request (TRG4AN) Note: * When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping TADCORA_4 TCNT_4 00 01 00 01 02 00 01 00 01 02 UT4AE = 1 DT4AE = 0 Figure 11.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 604 of 1692 REJ09B0393-0100

11.4.10 MTU2-MTU2S Synchronous Operation

(1) MTU2-MTU2S Synchronous Counter Start The counters in the MTU2 and MTU2S which operate at different clock systems can be started synchronously by making the TCSYSTR settings in the MTU2. (a) Example of MTU2-MTU2S Synchronous Counter Start Setting Procedure Figure 11.83 shows an example of synchronous counter start setting procedure. Stop count operation MTU2-MTU2S synchronous counter start Set the necessary operation <Counter operation starts> [1] [2] Set TCSYSTR [3] [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for synchronous start operation. [2] Specify necessary operation with appropriate registers such as TCR and TMDR. [3] In TCSYSTR in the MTU2, set the bits corresponding to the counters to be started synchronously to 1. The TSTRs are automatically set appropriately and the counters start synchronously. Notes: 1. Even if a bit in TCSYSTR corresponding to an operating counter is cleared to 0, the counter will not stop. To stop the counter, clear the corresponding bit in TSTR to 0 directly. 2. To start channels 3 and 4 in reset-synchronized PWM mode or complementary PWM mode, make appropriate settings in TCYSTR according to the TSTR setting for the respective mode. For details, refer to section 11.4.7, Reset-Synchronized PWM Mode, and section 11.4.8, Complementary PWM Mode. Figure 11.83 Example of Synchronous Counter Start Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 605 of 1692 REJ09B0393-0100 (b) Examples of Synchronous Counter Start Operation Figures 11.84 (1) to (4) show examples of synchronous counter start operation when the clock frequency ratios between the MTU2 and MTU2S are 1:1, 1:2, 1:3, and 1:4, respectively. In these examples, the count clock is set to Pφ/1. MTU2 clock MTU2S clock MTU2/TSTR MTU2S/TSTR H'51TCSYSTR H'00 H'42H'00 H'80H'00 H'00 H'0001MTU2/TCNT_1 H'0000 H'0002 H'0001 H'0002MTU2S/TCNT_4 H'0000 Automatically cleared after TCSYSTR setting is made Figure 11.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 607 of 1692 REJ09B0393-0100 Automatically cleared after TCSYSTR setting is made MTU2 clock MTU2S clock MTU2/TSTR MTU2S/TSTR H'51TCSYSTR H'00 H'42H'00 H'80H'00 H'00 H'0001MTU2/TCNT_1 H'0000 H'0002 H'0001 H'0002 H'0003 H'0004 MTU2S/TCNT_4 H'0000 Figure 11.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 610 of 1692 REJ09B0393-0100

11.4.11 External Pulse Width Measurement

The pulse widths of up to three external input lines can be measured in channel 5. (1) Example of External Pulse Width Measurement Setting Procedure [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. Select counter clock External pulse width measurement Select pulse width measuring conditions Start count operation <External pulse width measurement> [1] [2] [3] Figure 11.87 Example of External Pulse Width Measurement Setting Procedure (2) Example of External Pulse Width Measurement 0000 0001 0002 0003 0004 0005 0006 0007 0007 0008 0009 000A 000B TIC5U TCNT5_U Pφ Figure 11.88 Example of External Pulse Width Measurement (Measuring High Pulse Width)

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11.4.12 Dead Time Compensation

By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Tdelay Upper arm signal Lower arm signal Inverter output detection signal Dead time delay signal Figure 11.89 Delay in Dead Time in Complementary PWM Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 613 of 1692 REJ09B0393-0100 MTU ch3/4 ch5 Complementary PWM output Dead time delay input Inverter output monitor signals U V W U V W U V W Motor≠ Level conversion DC Figure 11.91 Example of Motor Control Circuit Configuration

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11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation

The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 11.92 shows an example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). Tdead Tdelay Upper arm signal Lower arm signal Inverter output monitor signal Dead time delay signal TGRA_4 3DE7 3E5B 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF3DE7 TCNT[15:0] TGR[15:0] Up-count/down-count signal (udflg) Figure 11.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation

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11.5 Interrupt Sources

11.5.1 Interrupt Sources and Priorities

There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 11.57 lists the MTU2 interrupt sources.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 616 of 1692 REJ09B0393-0100 Table 11.57 MTU2 Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation Priority

0 TGIA_0 TGRA_0 input capture/co mpare match TGFA_0 Possible High

TGIB_0 TGRB_0 input capture/compare match TGFB_0 Not possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Not possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Not possible TCIV_0 TCNT_0 overflow TCFV_0 Not possible TGIE_0 TGRE_0 compare match TGFE_0 Not possible TGIF_0 TGRF_0 compare ma tch TGFF_0 Not possible

1 TGIA_1 TGRA_1 input capture/co mpare match TGFA_1 Possible

TGIB_1 TGRB_1 input capture/compare match TGFB_1 Not possible TCIV_1 TCNT_1 overflow TCFV_1 Not possible TCIU_1 TCNT_1 underflow TCFU_1 Not possible

2 TGIA_2 TGRA_2 input capture/co mpare match TGFA_2 Possible

TGIB_2 TGRB_2 input capture/compare match TGFB_2 Not possible TCIV_2 TCNT_2 overflow TCFV_2 Not possible TCIU_2 TCNT_2 underflow TCFU_2 Not possible

3 TGIA_3 TGRA_3 input capture/co mpare match TGFA_3 Possible

TGIB_3 TGRB_3 input capture/compare match TGFB_3 Not possible TGIC_3 TGRC_3 input capture/compare match TGFC_3 Not possible TGID_3 TGRD_3 input capture/compare match TGFD_3 Not possible TCIV_3 TCNT_3 overflow TCFV_3 Not possible

4 TGIA_4 TGRA_4 input capture/co mpare match TGFA_4 Possible

TGIB_4 TGRB_4 input capture/compare match TGFB_4 Not possible TGIC_4 TGRC_4 input capture/compare match TGFC_4 Not possible TGID_4 TGRD_4 input capture/compare match TGFD_4 Not possible TCIV_4 TCNT_4 overflow/underflow TCFV_4 Not possible

5 TGIU_5 TGRU_5 input capture/compare match TGFU_5 Not possible

TGIV_5 TGRV_5 input capture/compare match TGFV_5 Not possible TGIW_5 TGRW_5 input capture/compare match TGFW_5 Not possible Low Note: This table shows the initia l state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 617 of 1692 REJ09B0393-0100 (1) Input Capture/Comp are Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.

11.5.2 DMAC and DTC Activation

(1) DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt in each channel and the overflow interrupt of channel 4. For details, see section 8, Data Transfer Controller (DTC). In the MTU2, a total of twenty input capture/compare match interrupts and overflow interrupts can be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, five for channel 4 and three for channel 5. (2) DMAC Activation The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 10, Direct Memory Access Controller (DMAC). In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC activation sources, one each for channels 0 to 4. When the DMAC is activation by MTU2, the activation sources are cleared when the DMAC requests the internal bus mastership. Accordingly, depending on the internal bus state, a wait state

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 618 of 1692 REJ09B0393-0100 of the DMAC transfer may be generated even if the activation sources are cleared. Also, when transferring DMAC burst by MTU2, the setting of bus function extension register (BSCEHR) is required. See section 9.4.8, Bus Function Extending Register (BSCEHR), for details.

11.5.3 A/D Converter Activation

The A/D converter can be activated by one of the following three methods in the MTU2. Table 11.58 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions.

• When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1
• When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. (2) A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 619 of 1692 REJ09B0393-0100 (3) A/D Converter Activation by A/D Converter Start Request Delaying Function The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 11.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated. Table 11.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 Input capture/compare match TCNT_4 TCNT_4 Trough in complementary PWM mode TRGAN TGRE_0 and TCNT_0 TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 Compare match TRG4BN

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11.6 Operation Timing

11.6.1 Input/Output Timing

(1) TCNT Count Timing Figures 11.93 and 94 show TCNT count timing in internal clock operation, and figure 11.95 shows TCNT count timing in external clock operation (normal mode), and figure 11.96 shows TCNT count timing in external clock operation (phase counting mode). TCNT TCNT input clock Internal clock Pφ Falling edge Rising edge N - 1 N N + 1 Figure 11.93 Count Timing in Internal Clock Operation (Channels 0 to 4) TCNT TCNT input clock Internal clock Pφ Rising edge N - 1 N Figure 11.94 Count Timing in Internal Clock Operation (Channel 5) Pφ TCNT TCNT input clock External clock Falling edge Rising edge N - 1 N N + 1 Figure 11.95 Count Timing in External Clock Operation (Channels 0 to 4)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 627 of 1692 REJ09B0393-0100 Temporary register Buffer transfer signal TCNTS Pφ Compare register N n N P − 1 P H'0000 Figure 11.108 Transfer Timing from Temporary Register to Compare Register

11.6.2 Interrupt Signal Timing

(1) TGF Flag Setting Timing in Case of Compare Match Figures 11.109 and 110 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TGR TCNT TCNT input clock N N N + 1 Compare match signal TGF flag TGI interrupt Pφ Figure 11.109 TGI Interrupt Timing (Compare Match)

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11.7 Usage Notes

11.7.1 Module Standby Mode Setting

MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 28, Power-Down Modes.

11.7.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.120 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- enceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 11.120 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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11.7.3 Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

• Channel 0 to 4 f = Pφ (N + 1)
• Channel 5 f = Pφ N Where f: Counter frequency P φ: Peripheral clock operating frequency N: TGR set value

11.7.4 Contention between TC NT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.121 shows the timing in this case. Couter area signal Write signal Address Pφ TCNT address TCNT TCNT write cycle T1 T2 N H'0000 Figure 11.121 Contention between TCNT Write and Clear Operations

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11.7.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.122 shows the timing in this case. TCNT input clock Write signal Address TCNT address TCNT TCNT write cycle T1 T2 NM TCNT write data Pφ Figure 11.122 Contention between TCNT Write and Increment Operations

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11.7.6 Contention between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 11.123 shows the timing in this case. Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 NM TGR write data TGR N N + 1 Pφ Figure 11.123 Contention between TGR Write and Compare Match

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11.7.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data after write. Figure 11.124 shows the timing in this case. Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2Buffer register address N N M Buffer register write data Buffer register TGR Pφ Figure 11.124 Contention between Buffer Register Write and Compare Match

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11.7.8 Contention between Buffer Register Write and TCNT Clear

When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 11.125 shows the timing in this case. Address Write signal TCNT clear signal Buffer transfer signal TGR write cycle T1 T2Buffer register address N N M Buffer register write data Buffer register TGR Pφ Figure 11.125 Contention between Buffer Register Write and TCNT Clear

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11.7.9 Contention between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 11.126 and 127 show the timing in this case. Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address Pφ N N M Figure 11.126 Contention between TGR Read and Input Capture (Channels 0 to 4) Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address Pφ M NM Figure 11.127 Contention between TGR Read and Input Capture (Channel 5)

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11.7.10 Contention between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 11.128 and 129 show the timing in this case. Input capture signal Write signal Address TCNT TGR write cycle T1 T2 MTGR M TGR address Pφ Figure 11.128 Contention between TGR Write and Input Capture (Channels 0 to 4) Input capture signal Write signal Address TCNT TGR write cycle T1 T2 NTGR M TGR address Pφ TGR write data Figure 11.129 Contention between TGR Write and Input Capture (Channel 5)

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11.7.11 Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.130 shows the timing in this case. Input capture signal Write signal Address TCNT Buffer register write cycle T1 T2 NTGR N M MBuffer register Buffer register address Pφ Figure 11.130 Contention between Buffer Register Write and Input Capture

11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 11.131. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 642 of 1692 REJ09B0393-0100 T1 T2 H'FFFE H'FFFF N N + 1 H'FFFF M M N P QP M Disabled TCNT_2 write data TCNT_2 address TCNT write cycle Address Write signal TCNT_2 TGRA_2 to TGRB_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D Pφ Figure 11.131 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection

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11.7.13 Counter Value during Complementary PWM Mode Stop

When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 11.132. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TDDR H'0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 11.132 Counter Value during Complementary PWM Mode Stop

11.7.14 Buffer Operation Setting in Complementary PWM Mode

In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register.

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11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 11.133 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD TGRA_3, TGRC_3 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 Buffer transfer with compare match A3TCNT3 Not set Not set Point a Point b Figure 11.133 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode

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11.7.16 Overflow Flags in Reset Synchronous PWM Mode

When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 11.134 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. TGRA_3 (H'FFFF) H'0000 TCFV_3 TCFV_4 TCNT_3 = TCNT_4 Counter cleared by compare match 3A Not set Not set Figure 11.134 Reset Synchronous PWM Mode Overflow Flag

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11.7.17 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.135 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. Counter clear signal TCNT TCNT input clock H'FFFF H'0000 TGF TCFV Disabled Pφ Figure 11.135 Contention between Overflow and Counter Clearing

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11.7.18 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.136 shows the operation timing when there is contention between TCNT write and overflow. Disabled Write signal Address TCNT address TCNT TCNT write cycle T1 T2 H'FFFF M TCNT write data TCFV flag Pφ Figure 11.136 Contention between TCNT Write and Overflow

11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-

When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset- synchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to reset- synchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 648 of 1692 REJ09B0393-0100

11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode

When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00.

11.7.21 Interrupts in Module Standby Mode

If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module standby mode.

11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection

When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input-capture as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time. For details, see section 11.3.8, Timer Input Capture Control Register (TICCR).

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 649 of 1692 REJ09B0393-0100

11.8 MTU2 Output Pin Initialization

11.8.1 Operating Modes

The MTU2 has the following six operating modes. Waveform output is possible in all of these modes.

• Normal mode (channels 0 to 4)
• PWM mode 1 (channels 0 to 4)
• PWM mode 2 (channels 0 to 2)
• Phase counting modes 1 to 4 (channels 1 and 2)
• Complementary PWM mode (channels 3 and 4)
• Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section.

11.8.2 Reset Start Operation

The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 650 of 1692 REJ09B0393-0100 11.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 11.59. Table 11.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 651 of 1692 REJ09B0393-0100

11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error

during Operation, etc.

• When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
• In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.
• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2.
• In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.
• In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.
• When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 11.59. The active level is assumed to be low.

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 681 of 1692 REJ09B0393-0100 Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) This LSI has an on-chip multi-function timer pulse unit 2S (MTU2S) that comprises three 16-bit timer channels. The MTU2S includes channels 3 to 5 of the MTU2. For details, refer to section 11, Multi-Function Timer Pulse Unit 2 (MTU2). To distinguish from the MTU2, "S" is added to the end of the MTU2S input/output pin and register names. For example, TIOC3A is called TIOC3AS and TGRA_3 is called TGRA_3S in this section. The MTU2S can operate at 100 MHz max. for complementary PWM output functions or at 50 MHz max. for the other functions. Table 12.1 MTU2S Functions Item Channel 3 Channel 4 Channel 5 Count clock M φ/1 Mφ/4 Mφ/16 Mφ/64 Mφ/256 Mφ/1024 Mφ/1 Mφ/4 Mφ/16 Mφ/64 Mφ/256 Mφ/1024 Mφ/1 Mφ/4 Mφ/16 Mφ/64 General registers TGRA_3S TGRB_3S TGRA_4S TGRB_4S TGRU_5S TGRV_5S TGRW_5S General registers/ buffer registers TGRC_3S TGRD_3S TGRC_4S TGRD_4S I/O pins TIOC3AS TIOC3BS TIOC3CS TIOC3DS TIOC4AS TIOC4BS TIOC4CS TIOC4DS Input pins TIC5US TIC5VS TIC5WS Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output √ √ — 1 output √ √ — Compare match output Toggle output √ √ — Input capture function √ √ √ Synchronous operation √ √ —

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 682 of 1692 REJ09B0393-0100 Item Channel 3 Channel 4 Channel 5 PWM mode 1 √ √ — PWM mode 2 — — — Complementary PWM mode √ √ — Reset PWM mode √ √ — AC synchronous motor drive mode — — — Phase counting mode — — — Buffer operation √ √ — Counter function of compensation for dead time — — DTC activation TGR compare match or input capture TGR compare match or input capture, or TCNT overflow or underflow TGR compare match or input capture A/D converter start trigger TGRA_3S compare match or input capture TGRA_4S compare match or input capture TCNT_4S underflow (trough) in complementary PWM mode Interrupt sources 5 sources

• Compare match or input capture 3AS
• Compare match or input capture 3BS
• Compare match or input capture 3CS
• Compare match or input capture 3DS
• Overflow 5 sources
• Compare match or input capture 4AS
• Compare match or input capture 4BS
• Compare match or input capture 4CS
• Compare match or input capture 4DS
• Overflow or underflow 3 sources
• Compare match or input capture 5US
• Compare match or input capture 5VS
• Compare match or input capture 5WS

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 683 of 1692 REJ09B0393-0100 Item Channel 3 Channel 4 Channel 5 A/D converter start request delaying function — • A/D converter start request at a match between TADCORA_4S and TCNT_4S

• A/D converter start request at a match between TADCORB_4S and TCNT_4S Interrupt skipping function
• Skips TGRA_3S compare match interrupts
• Skips TCIV_4S interrupts [Legend] √: Possible —: Not possible

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 684 of 1692 REJ09B0393-0100

12.1 Input/Output Pins

Table 12.2 Pin Configuration Channel Symbol I/O Function

3 TIOC3AS I/O TGRA_3S input capture inpu t/output compare output/PWM output pin

TIOC3BS I/O TGRB_3S input capture inpu t/output compare output/PWM output pin TIOC3CS I/O TGRC_3S input capture inpu t/output compare output/PWM output pin TIOC3DS I/O TGRD_3S input capture inpu t/output compare output/PWM output pin

4 TIOC4AS I/O TGRA_4S input capture inpu t/output compare output/PWM output pin

TIOC4BS I/O TGRB_4S input capture inpu t/output compare output/PWM output pin TIOC4CS I/O TGRC_4S input capture inpu t/output compare output/PWM output pin TIOC4DS I/O TGRD_4S input capture inpu t/output compare output/PWM output pin

5 TIC5US Input TGRU_5S input capt ure input/external pulse input pin

TIC5VS Input TGRV_5S input captur e input/external pulse input pin TIC5WS Input TGRW_5S input capt ure input/external pulse input pin

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 685 of 1692 REJ09B0393-0100

12.2 Register Descriptions

The MTU2S has the following registers. For details on register addresses and register states during each process, refer to section 30, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 3 is expressed as TCR_3S. Table 12.3 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size Timer control register_3S TCR_3S R/W H' 00 H'FFFE4A00 8, 16, 32 Timer control register_4S TCR_4S R/W H'00 H'FFFE4A01 8 Timer mode register_3S TMDR_3S R/W H'00 H'FFFE4A02 8, 16 Timer mode register_4S TMDR_4S R/W H'00 H'FFFE4A03 8 Timer I/O control register H_3S TIORH_3S R/W H'00 H'FFFE4A04 8, 16, 32 Timer I/O control register L_3S TIORL_3S R/W H'00 H'FFFE4A05 8 Timer I/O control register H_4S TIORH_4S R/W H'00 H'FFFE4A06 8, 16 Timer I/O control register L_4S TIORL_4S R/W H'00 H'FFFE4A07 8 Timer interrupt enable register_3S TIER_3S R/ W H'00 H'FFFE4A08 8, 16 Timer interrupt enable register_4S TIER_4S R/W H'00 H'FFFE4A09 8 Timer output master enable register S TOERS R/W H'C0 H'FFFE4A0A 8 Timer gate control register S TGCRS R/W H'80 H'FFFE4A0D 8 Timer output control register 1S TOCR1S R/W H'00 H'FFFE4A0E 8, 16 Timer output control register 2S TOCR2S R/W H'00 H'FFFE4A0F 8 Timer counter_3S TCNT_3S R/W H'0000 H'FFFE4A10 16, 32 Timer counter_4S TCNT_4S R/W H'0000 H'FFFE4A12 16 Timer cycle data register S TCDRS R/W H'FFFF H'FFFE4A14 16, 32 Timer dead time data register S TDDRS R/W H'FFFF H'FFFE4A16 16 Timer general register A_3S TGRA_3S R/W H'FFFF H'FFFE4A18 16, 32 Timer general register B_3S TGRB_3S R/W H'FFFF H'FFFE4A1A 16 Timer general register A_4S TGRA_4S R/W H'FFFF H'FFFE4A1C 16, 32 Timer general register B_4S TGRB_4S R/W H'FFFF H'FFFE4A1E 16 Timer subcounter S TCNT SS R H'0000 H'FFFE4A20 16, 32 Timer cycle buffer register S TCBRS R/W H'FFFF H'FFFE4A22 16

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 686 of 1692 REJ09B0393-0100 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer general register C_3S TGRC_3S R/W H'FFFF H'FFFE4A24 16, 32 Timer general register D_3S TGRD_3S R/W H'FFFF H'FFFE4A26 16 Timer general register C_4S TGRC_4S R/W H'FFFF H'FFFE4A28 16, 32 Timer general register D_4S TGRD_4S R/W H'FFFF H'FFFE4A2A 16 Timer status register_3S TSR_3S R/W H'C0 H'FFFE4A2C 8, 16 Timer status register_4S TSR_4S R/W H'C0 H'FFFE4A2D 8 Timer interrupt skipping set register S TITCRS R/W H'00 H'FFFE4A30 8, 16 Timer interrupt skipping counter S TITCNTS R H'00 H'FFFE4A31 8 Timer buffer transfer set register S TBTERS R/W H'00 H'FFFE4A32 8 Timer dead time enable register S TDERS R/W H'01 H'FFFE4A34 8 Timer output level buffer register S TOLBRS R/W H'00 H'FFFE4A36 8 Timer buffer operation transfer mode register_3S TBTM_3S R/W H'00 H'FFFE4A38 8, 16 Timer buffer operation transfer mode register_4S TBTM_4S R/W H'00 H'FFFE4A39 8 Timer A/D converter start request control register S TADCRS R/W H'0000 H'FFFE4A40 16 Timer A/D converter start request cycle set register A_4S TADCORA_4S R/W H'FFFF H'FFFE4A44 16, 32 Timer A/D converter start request cycle set register B_4S TADCORB_4S R/W H'FFFF H'FFFE4A46 16 Timer A/D converter start request cycle set buffer register A_4S TADCOBRA_4S R/W H'FFFF H'FFFE4A48 16, 32 Timer A/D converter start request cycle set buffer register B_4S TADCOBRB_4S R/W H'FFFF H'FFFE4A4A 16 Timer synchronous clear register S TSYCRS R/W H'00 H'FFFE4A50 8 Timer waveform control register S TWCRS R/W H'00 H'FFFE4A60 8 Timer start register S TSTRS R/W H'00 H'FFFE4A80 8, 16 Timer synchronous register S TSYRS R/W H'00 H'FFFE4A81 8 Timer read/write enable register S TRWERS R/W H'01 H'FFFE4A84 8

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 687 of 1692 REJ09B0393-0100 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer counter U_5S TCNTU _5S R/W H'0000 H'FFFE4880 16, 32 Timer general register U_5S TGRU_5S R/W H'FFFF H'FFFE4882 16 Timer control register U_5S TCRU_5S R/W H'00 H'FFFE4884 8 Timer I/O control register U_5S TIORU_5S R/W H'00 H'FFFE4886 8 Timer counter V_5S TCNTV _5S R/W H'0000 H'FFFE4890 16, 32 Timer general register V_5S TGRV_5S R/W H'FFFF H'FFFE4892 16 Timer control register V_5S TCRV_5S R/W H'00 H'FFFE4894 8 Timer I/O control register V_5S TIORV_5S R/W H'00 H'FFFE4896 8 Timer counter W_5S TCNTW_5S R/W H'0000 H'FFFE48A0 16, 32 Timer general register W_5S TGRW_5S R/W H'FFFF H'FFFE48A2 16 Timer control register W_5S TCRW_5S R/W H'00 H'FFFE48A4 8 Timer I/O control register W_5S TIORW_5S R/W H'00 H'FFFE48A6 8 Timer status register_5S TSR_5S R/W H'00 H'FFFE48B0 8 Timer interrupt enable register_5S TIER_5S R/W H'00 H'FFFE48B2 8 Timer start register_5S TSTR_5S R/W H'00 H'FFFE48B4 8 Timer compare match clear register S TCNTCMPCLRS R/W H'00 H'FFFE48B6 8

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Rev. 1.00 Jun. 26, 2008 Page 688 of 1692 REJ09B0393-0100

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 689 of 1692 REJ09B0393-0100 Section 13 Port Output Enable 2 (POE2) The port output enable 2 (POE2) can be used to place the high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, PE15/TIOC4D, PE0/TIOC4AS, PE1/TIOC4BS, PE2/TIOC4CS, PE3/TIOC4DS, PE5/TIOC3BS, PE6/TIOC3DS, PD15/TIOC4DS, PD14/TIOC4CS, PD13/TIOC4BS, PD12/TIOC4AS, PD11/TIOC3DS, PD10/TIOC3BS, PD24/TIOC4DS, PD25/TIOC4CS, PD26/TIOC4BS, PD27/TIOC4AS, PD28/TIOC3DS, and PD29/TIOC3BS) and the pins for channel 0 of the MTU2 (PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and PE3/TIOC0D) in high-impedance state, depending on the change on the POE0 to POE8* input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests.

13.1 Features

• Each of the POE0 to POE8* input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0 to POE8* pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE2 register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results. The POE2 has input level detection circuits, output level comparison circuits, and a high- impedance request/interrupt request generating circuit as shown in the block diagram of figure 13.1. Note: * Only POE8, POE4, POE3, and POE0 are available in the SH7243.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 691 of 1692 REJ09B0393-0100

13.2 Input/Output Pins

Table 13.1 Pin Configuration Pin Name Symbol I/O Function Port output enable input pins 0 to 3 POE0 to POE3 Input Input request signals to place high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, and PE15/TIOC4D) for MTU2 in high-impedance state Port output enable input pins 4 to 7 POE4 to POE7 Input Input request signals to place high-current pins (PE5/TIOC3BS, PE6/TIOC3DS, PE0/TIOC4AS, PE1/TIOC4BS, PE2/TIOC4CS, PE3/TIOC4DS, PD10/TIOC3BS, PD11/TIOC3DS, PD12/TIOC4AS, PD13/TIOC4BS, PD14/TIOC4CS, PD15/TIOC4DS, PD29/TIOC3BS, PD28/TIOC3DS, PD27/TIOC4AS, PD26/TIOC4BS, PD25/TIOC4CS, and PD24/TIOC4DS) for MTU2S in high-impedance state Port output enable input pin 8 POE8 Input Inputs a request signal to place pins (PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and PA3/TIOC0D) for channel 0 in MTU2 in high- impedance state

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 692 of 1692 REJ09B0393-0100 Table 13.2 shows output-level comparisons with pin combinations. Table 13.2 Pin Combinations Pin Combination I/O Description PE9/TIOC3B and PE11/TIOC3D PE12/TIOC4A and PE13/TIOC4C PE14/TIOC4B and PE15/TIOC4D Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level for one or more cycles of the peripheral clock (Pφ). (In the case of TOCS = 0 in timer output control register 1 (TOCR1) in the MTU2, low level when the output level select P (OLSP) bit is 0, or high level when the OLSP bit is 1. In the case of TOCS = 1, low level when the OLS3N, OLS3P, OLS2N, OLS2P, OLS1N, and OLS1P bits are 0 in TOCR2, or high level when these bits are 1.) This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and high- impedance control can be selected by POE2 registers. PE5/PD10/PD29/TIOC3BS and PE6/PD11/PD28/TIOC3DS PE0/PD12/PD27/TIOC4AS and PE2/PD14/PD25/TIOC4CS PE1/PD13/PD26/TIOC4BS and PE3/PD15/PD24/TIOC4DS Output The high-current pins for the MTU2S are placed in high-impedance state when the pins simultaneously output an active level for one or more cycles of the peripheral clock (Pφ). (In the case of TOCS = 0 in timer output control register 1S (TOCR1S) in the MTU2S, low level when the output level select P (OLSP) bit is 0, or high level when the OLSP bit is 1. In the case of TOCS = 1, low level when the OLS3N, OLS3P, OLS2N, OLS2P, OLS1N, and OLS1P bits are 0 in TOCR2S, or high level when these bits are 1.) This active level comparison is done when the MTU2S output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and high- impedance control can be selected by POE2 registers.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 693 of 1692 REJ09B0393-0100

13.3 Register Descriptions

The POE2 has the following registers. All these registers are initialized by a power-on reset, but are not initialized by a manual reset or in sleep mode, software standby mode, or module standby mode. Table 13.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Input level control/status register 1 ICSR1 R/W H'0000 H'FFFE5000 16 Output level control/status register 1 OCSR1 R/W H'0000 H'FFFE5002 16 Input level control/status register 2 ICSR2 R/W H'0000 H'FFFE5004 16 Output level control/status register 2 OCSR2 R/W H'0000 H'FFFE5006 16 Input level control/status register 3 ICSR3 R/W H'0000 H'FFFE5008 16 Software port output enable register SPOER R/W H'00 H'FFFE500A 8 Port output enable control register 1 POECR1 R/W H'00 H'FFFE500B 8 Port output enable control register 2 POECR2 R/W H'7700 H'FFFE500C 16

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 694 of 1692 REJ09B0393-0100

13.3.1 Input Level Control/Status Register 1 (ICSR1)

ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1 , POE2 , and POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: Notes: Only 0 can be written to clear the flag after 1 is read. Can be modified only once after a power-on reset. 0000000000000000 R/(W)*1R/(W)*1 R/(W)*1 R/(W)*1 R R R R/W R/W *2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 POE3F POE2F POE1F POE0F - - - PIE1 POE3M[1:0] POE2M[1:0] POE1M[1:0] POE0M[1:0] Bit Bit Name Initial Value R/W Description

15 POE3F 0 R/(W) *

Indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions]

• By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1)
• By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) [Setting condition]
• When the input set by bits 7 and 6 in ICSR1 occurs at the POE3 pin

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 695 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

14 POE2F 0 R/(W) *

Indicates that a high impedance request has been input to the POE2 pin. [Clearing conditions]

• By writing 0 to POE2F after reading POE2F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR1)
• By writing 0 to POE2F after reading POE2F = 1 after a high level input to POE2 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR1) [Setting condition]
• When the input set by bits 5 and 4 in ICSR1 occurs at the POE2 pin

13 POE1F 0 R/(W) *

Indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions]

• By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1)
• By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) [Setting condition]
• When the input set by bits 3 and 2 in ICSR1 occurs at the POE1 pin

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 696 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

12 POE0F 0 R/(W) *

Indicates that a high impedance request has been input to the POE0 pin. [Clear conditions]

• By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1)
• By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) [Set condition]
• When the input set by bits 1 and 0 in ICSR1 occurs at the POE0 pin 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 PIE1 0 R/W Port Interrupt Enable 1

Enables or disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W * POE3 Mode These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 Pφ/128 clock pulses and all are low level.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 697 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 5, 4 POE2M[1:0] 00 R/W * POE2 Mode These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE2 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE2 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 3, 2 POE1M[1:0] 00 R/W * POE1 Mode These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 1, 0 POE0M[1:0] 00 R/W * POE0 Mode These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. 3. POE1 and POE2 are not available in the SH7243.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 698 of 1692 REJ09B0393-0100

13.3.2 Output Level Control/Status Register 1 (OCSR1)

OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/(W)*1 RRRRR R / W *2 R / W RRRRRRRR Notes: Only 0 can be written to clear the flag after 1 is read. Can be modified only once after a power-on reset. Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description

15 OSF1 0 R/(W) *

Indicates that any one of the three pairs of MTU2 2- phase outputs to be compared has simultaneously become an active level. [Clearing condition]

• By writing 0 to OSF1 after reading OSF1 = 1 [Setting condition]
• When any one of the three pairs of 2-phase outputs has simultaneously become an active level 14 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 OCE1 0 R/W *

Output Short High-Impedance Enable 1 Specifies whether to place the pins in high-impedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 OIE1 0 R/W Output Short Interrupt Enable 1

Enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 699 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset.

13.3.3 Input Level Control/Status Register 2 (ICSR2)

ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7 pin input modes, controls the enable/disable of interrupts, and indicates status. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R R R R/W R/W *2 R/W*2 R/W*2 R/W*2R/W*2 R/W*2R/W*2 R/W*2 POE7F POE6F POE5F POE4F - - - PIE2 POE7M[1:0] POE4M[1:0] POE5M[1:0]POE6M[1:0] Notes: Only 0 can be written to clear the flag after 1 is read. Can be modified only once after a power-on reset. 3. Only POE4 is available in the SH7243. Bit Bit Name Initial Value R/W Description

15 POE7F 0 R/(W) *

Indicates that a high impedance request has been input to the POE7 pin. [Clearing conditions]

• By writing 0 to POE7F after reading POE7F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR2)
• By writing 0 to POE7F after reading POE7F = 1 after a high level input to POE7 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR2) [Setting condition]
• When the input condition set by bits 7 and 6 in ICSR2 occurs at the POE7 pin

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 700 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

14 POE6F 0 R/(W) *

Indicates that a high impedance request has been input to the POE6 pin. [Clearing conditions]

• By writing 0 to POE6F after reading POE6F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR2)
• By writing 0 to POE6F after reading POE6F = 1 after a high level input to POE6 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR2) [Setting condition]
• When the input condition set by bits 5 and 4 in ICSR2 occurs at the POE6 pin

13 POE5F 0 R/(W) *

Indicates that a high impedance request has been input to the POE5 pin. [Clearing conditions]

• By writing 0 to POE5F after reading POE5F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR2)
• By writing 0 to POE5F after reading POE5F = 1 after a high level input to POE5 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR2) [Setting condition]
• When the input condition set by bits 3 and 2 in ICSR2 occurs at the POE5 pin

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 701 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

12 POE4F 0 R/(W) *

Indicates that a high impedance request has been input to the POE4 pin. [Clearing conditions]

• By writing 0 to POE4F after reading POE4F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR2)
• By writing 0 to POE4F after reading POE4F = 1 after a high level input to POE4 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR2) [Setting condition]
• When the input condition set by bits 1 and 0 in ICSR2 occurs at the POE4 pin 11 to 9 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 PIE2 0 R/W Port Interrupt Enable 2

Enables or disables interrupt requests when any one of the POE4F to POE7F bits of the ICSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE7M[1:0] 00 R/W * POE7 Mode These bits select the input mode of the POE7 pin. 00: Accept request on falling edge of POE7 input 01: Accept request when POE7 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE7 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE7 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 702 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 5, 4 POE6M[1:0] 00 R/W * POE6 Mode These bits select the input mode of the POE6 pin. 00: Accept request on falling edge of POE6 input 01: Accept request when POE6 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE6 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE6 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. 3, 2 POE5M[1:0] 00 R/W * POE5 Mode These bits select the input mode of the POE5 pin. 00: Accept request on falling edge of POE5 input 01: Accept request when POE5 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE5 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE5 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. 1, 0 POE4M[1:0] 00 R/W * POE4 Mode These bits select the input mode of the POE4 pin. 00: Accept request on falling edge of POE4 input 01: Accept request when POE4 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE4 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE4 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 703 of 1692 REJ09B0393-0100

13.3.4 Output Level Control/Status Register 2 (OCSR2)

OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/(W)*1 RRRRR R / W *2 R / W RRRRRRRR Notes: Only 0 can be written to clear the flag after 1 is read. Can be modified only once after a power-on reset. Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description

15 OSF2 0 R/(W) *

Indicates that any one of the three pairs of MTU2S 2- phase outputs to be compared has simultaneously become an active level. [Clearing condition]

• By writing 0 to OSF2 after reading OSF2 = 1 [Setting condition]
• When any one of the three pairs of 2-phase outputs has simultaneously become an active level 14 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 OCE2 0 R/W *

Output Short High-Impedance Enable 2 Specifies whether to place the pins in high-impedance state when the OSF2 bit in OCSR2 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 704 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

8 OIE2 0 R/W Output Short Interrupt Enable 2

Enables or disables interrupt requests when the OSF2 bit in OCSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset.

13.3.5 Input Level Control/Status Register 3 (ICSR3)

ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRR R/(W)*1 R R R/W *2 R/W R R R R R R R/W *2 R/W*2 POE8F - - POE8E - - - - -- - - PIE3 - POE8M[1:0] Notes: Only 0 can be written to clear the flag after 1 is read. Can be modified only once after a power-on reset. Bit Bit Name Initial Value R/W Description 15 to 13 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 705 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

12 POE8F 0 R/(W) *

Indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions]

• By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3)
• By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) [Setting condition]
• When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 POE8E 0 R/W *

POE8 High-Impedance Enable Specifies whether to place the pins in high-impedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 PIE3 0 R/W Port Interrupt Enable 3

Enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 706 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 POE8M[1:0] 00 R/W * POE8 Mode These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset.

13.3.6 Software Port Output Enable Register (SPOER)

SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. 7654321 0 00000000 RRRRR R / W R / W R / W Bit: Initial value: R/W: ----- MTU2S HIZ MTU2 CH0HIZ MTU2 CH34HIZ Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 707 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 MTU2SHIZ 0 R/W MTU2S Output High-Impedance

Specifies whether to place the high-current pins for the MTU2S in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2SHIZ after reading MTU2SHIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2SHIZ

1 MTU2CH0HIZ 0 R/W MTU2 Chan nel 0 Output High-Impedance

Specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH0HIZ

0 MTU2CH34HIZ 0 R/W MTU2 Channel 3 and 4 Output High-Impedance

Specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH34HIZ

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 708 of 1692 REJ09B0393-0100

13.3.7 Port Output Enable Control Register 1 (POECR1)

POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. 7654321 0 00000000 RRRR R / W * R/W* R/W* R/W* Bit: Initial value: R/W: Note: Can be modified only once after a power-on reset.* ---- MTU2 PE2ZE MTU2 PE3ZE MTU2 PE1ZE MTU2 PE0ZE Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 MTU2PE3ZE 0 R/W * MTU2PE3 High-Impedance Enable

Specifies whether to place the PE3/TIOC0D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

2 MTU2PE2ZE 0 R/W * MTU2PE2 High-Impedance Enable

Specifies whether to place the PE2/TIOC0C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

1 MTU2PE1ZE 0 R/W * MTU2PE1 High-Impedance Enable

Specifies whether to place the PE1/TIOC0B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 709 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 MTU2PE0ZE 0 R/W * MTU2PE0 High-Impedance Enable

Specifies whether to place the PE0/TIOC0A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

13.3.8 Port Output Enable Control Register 2 (POECR2)

POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: R/W* R/W* R/W* 01110 00000000 R R/W * R/W* R/W* 111 R/W* R/W* R/W* R/W* R/W* R/W*RRR MTU2S P7CZE MTU2S P8CZE MTU2S P9CZE- MTU2 P1CZE MTU2 P2CZE MTU2 P3CZE MTU2S P1CZE MTU2S P2CZE MTU2S P3CZE MTU2S P4CZE MTU2S P5CZE MTU2S P6CZE--- Note: Can be modified only once after a power-on reset.* Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

14 MTU2P1CZE 1 R/W * MTU2 Port 1 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 710 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

13 MTU2P2CZE 1 R/W * MTU2 Port 2 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

12 MTU2P3CZE 1 R/W * MTU2 Port 3 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 711 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

10 MTU2SP1CZE 1 R/W * MTU2S Port 1 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PE5/TIOC3BS and PE6/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

9 MTU2SP2CZE 1 R/W * MTU2S Port 2 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PE0/TIOC4AS and PE2/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 712 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

8 MTU2SP3CZE 1 R/W * MTU2S Port 3 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PE1/TIOC4BS and PE3/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state. 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 MTU2SP4CZE 0 R/W * MTU2S Port 4 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD10/TIOC3BS and PD11/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 713 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 MTU2SP5CZE 0 R/W * MTU2S Port 5 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD12/TIOC4AS and PD14/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

4 MTU2SP6CZE 0 R/W * MTU2S Port 6 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD13/TIOC4BS and PD15/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state. 3 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 714 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 MTU2SP7CZE 0 R/W * MTU2S Port 7 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD29/TIOC3BS and PD28/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

1 MTU2SP8CZE 0 R/W * MTU2S Port 8 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD27/TIOC4AS and PD25/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state.

0 MTU2SP9CZE 0 R/W * MTU2S Port 9 Output Comparison/High-Impedance

Specifies whether to compare output levels for the MTU2S high-current PD26/TIOC4BS and PD24/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state. 1: Compares output levels and places the pins in high-impedance state. Note: * Can be modified only once after a power-on reset.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 715 of 1692 REJ09B0393-0100

13.4 Operation

Table 13.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 13.4 Target Pins and Conditions for High-Impedance Control Pins Conditions De tailed Conditions MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) Input level detection, output level comparison, or SPOER setting MTU2P1CZE ((POE3F+POE2F+POE1F+POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) Input level detection, output level comparison, or SPOER setting MTU2P2CZE ((POE3F+POE2F+POE1F+POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) Input level detection, output level comparison, or SPOER setting MTU2P3CZE ((POE3F+POE2F+POE1F+POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2S high-current pins (PE5/TIOC3BS and PE6/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP1CZE ((POE4F+POE5F+POE6F+POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PE0/TIOC4A and PE2/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP2CZE ((POE4F+POE5F+POE6F+POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PE1/TIOC4BS and PE3/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP3CZE ((POE4F+POE5F+POE6F+POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD10/TIOC3BS and PD11/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP4CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD12/TIOC4AS and PD14/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP5CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD13/TIOC4BS and PD15/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP6CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD29/TIOC3BS and PD28/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP7CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ))

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 716 of 1692 REJ09B0393-0100 Pins Conditions De tailed Conditions MTU2S high-current pins (PD27/TIOC4AS and PD25/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP8CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD26/TIOC4BS and PD24/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP9CZE ((POE4F+POE5F+POE6F+POE7F) +(OSF2 • OCE2) + (MTU2SHIZ)) MTU2 CH0 pins (PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and PE3/TIOC0D) Input level detection or SPOER setting MTU2PE0ZE to MTU2PE3ZE (POE8F • POE8E) +(MTU2CH0HIZ)

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 717 of 1692 REJ09B0393-0100

13.4.1 Input Level Detection Operation

If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function, MTU2 function, or MTU2S function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 13.2 shows the sample timing after the level changes in input to the POE0 to POE8 pins until the respective pins enter high-impedance state. Pφ PE9/ TIOC3B POE input Pφ rising edge Falling edge detection High-impedance state Note: The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing. Figure 13.2 Falling Edge Detection

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 718 of 1692 REJ09B0393-0100 (2) Low-Level Detection Figure 13.3 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this interval, the low level is not accepted. The timing when the high-current pins enter the high-impedance state after the sampling clock is input is the same in both falling-edge detection and in low-level detection. PE9/TIOC3B (1) (2) (3) (16) (1) (2) (13) Pφ Sampling clock POE input When low level is sampled at all points When high level is sampled at least once Flag set (POE received) Flag not set High-impedance state* 8/16/128 clock cycles Note: * The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing. Figure 13.3 Low-Level Detection Operation

13.4.2 Output-Level Compare Operation

Figure 13.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. PE9/ TIOC3B PE11/ TIOC3D Pφ Low level overlapping detected High impedance state Figure 13.4 Output-Level Compare Operation

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 719 of 1692 REJ09B0393-0100

13.4.3 Release from High-Impedance State

High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 15 to 12 (POE8F to POE0F) of ICSR1 to ICSR3. However, note that when low- level sampling is selected by bits 7 to 0 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to one of the POE0 to POE8 pins and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S internal registers.

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 720 of 1692 REJ09B0393-0100

13.5 Interrupts

The POE2 issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 13.5 shows the interrupt sources and their conditions. Table 13.5 Interrupt Sources and Conditions Name Interrupt Source Interrupt Flag Condition OEI1 Output enable interrupt 1 POE3F, POE2F, POE1F, POE0F, and OSF1 PIE1 • (POE3F + POE2F + POE1F + POE0F) + OIE1 • OSF1 OEI2 Output enable interrupt 2 POE8F PIE3 • POE8F OEI3 Output enable interrupt 3 POE4F, POE5F, POE6F, POE7F, and OSF2 PIE2 • (POE4F + POE5F + POE6F + POE7F) + OIE2 • OSF2

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 721 of 1692 REJ09B0393-0100

13.6 Usage Notes

13.6.1 Pins States when the Watchdog Timer has Issued a Power-on Reset

A power-on reset issued from the watchdog timer (WDT) initializes the pin-function controller (PFC) and all I/O port pins thus become general-purpose inputs in accord with the initial PFC settings. However, when a power-on reset is issued while the port-output enable (POE) setting is for high-impedance handling by the pins, the pins remain in the output state for an interval of one cycle of the peripheral clock (Pφ) before switching to operation as general-purpose inputs. The same condition applies when the WDT issues a power-on reset and short-circuit detection by the MTU2 has led to high-impedance handling by a pin. Figure 13.5 shows the situation where timer output has been selected and the WDT issues a power-on reset while high-impedance handling is in progress due to the POE input. Timer output General-purpose input General-purpose input Timer output Timer output High-impedance state 1 period of 1Pφ Pφ POE input Pin state PFC setting Power-on reset by the WDT Figure 13.5 Pin States when the Watchdog Timer Issues a Power-on Reset

Section 13 Port Output Enable 2 (POE2) Rev. 1.00 Jun. 26, 2008 Page 722 of 1692 REJ09B0393-0100

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 723 of 1692 REJ09B0393-0100 Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals.

14.1 Features

• Independent selection of four counter input clocks at two channels Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
• Selection of DTC/DMA transfer request or interrupt request generation on compare match by DTC/DMA setting
• When not in use, the CMT can be stopped by halting its clock supply to reduce power consumption. Figure 14.1 shows a block diagram of CMT. CMSTR CMCSR_0 CMCOR_0 CMCNT_0 CMT CMI0 Pφ/8 P φ/32 P φ/128 Pφ/512 CMI1 CMCSR_1 CMCOR_1 CMCNT_1 Pφ/8 P φ/32 P φ/128 Pφ/512 Control circuit Clock selection Channel 0 Channel 1 Clock selectionControl circuit CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match constant register Compare match counter Compare match interrupt [Legend] Module bus Bus interface Internal bus Comparator Comparator Figure 14.1 Block Diagram of CMT

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 724 of 1692 REJ09B0393-0100

14.2 Register Descriptions

The CMT has the following registers. Table 14.1 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size Common Compare match timer start register CMSTR R/W H'0000 H'FFFEC000 16 Compare match timer control/ status register_0 CMCSR_0 R/(W) * H'0000 H'FFFEC002 16 Compare match counter_0 CMCNT_0 R/W H'0000 H'FFFEC004 16 Compare match constant register_0 CMCOR_0 R/W H'FFFF H'FFFEC006 16 Compare match timer control/ status register_1 CMCSR_1 R/(W) * H'0000 H'FFFEC008 16 Compare match counter_1 CMCNT_1 R/W H'0000 H'FFFEC00A 16 Compare match constant register_1 CMCOR_1 R/W H'FFFF H'FFFEC00C 16

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 725 of 1692 REJ09B0393-0100

14.2.1 Compare Match Tim er Start Register (CMSTR)

CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. CMSTR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 RRRRRRRRRRRRRR R / W R / W Bit Bit Name Initial Value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 STR1 0 R/W Count Start 1

Specifies whether compare match counter_1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started

0 STR0 0 R/W Count Start 0

Specifies whether compare match counter_0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 726 of 1692 REJ09B0393-0100

14.2.2 Compare Match Timer Co ntrol/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates compare match generation, enables or disables interrupts, and selects the counter input clock. CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/(W) * R/W R R R R R/W R/W Bit: Initial value: R/W: Note: Only 0 can be written to clear the flag after 1 is read.* Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 CMF 0 R/(W) * Compare Match Flag

Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match. [Clearing condition]

• When 0 is written to CMF after reading CMF = 1
• When data is transferred after the DTC has been activated by CMI (except when the DTC transfer counter value has become H'000).
• When data is transferred after the DMAC has been activated by CMI 1: CMCNT and CMCOR values match

Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 727 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS[1:0]. 00: Pφ/8 01: Pφ/32 10: Pφ/128 11: Pφ/512 Note: * Only 0 can be written to clear the flag after 1 is read.

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 728 of 1692 REJ09B0393-0100

14.2.3 Compare Matc h Counter (CMCNT)

CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W:

14.2.4 Compare Match Co nstant Register (CMCOR)

CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset or in software standby mode, but retains its previous value in module standby mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W:

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 729 of 1692 REJ09B0393-0100 When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 14.2 shows the operation of the compare match counter. CMCOR H'0000 CMCNT value Time Counter cleared by compare match with CMCOR Figure 14.2 Counter Operation

14.3.2 CMCNT Count Timing

One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock (Pφ) can be selected with the CKS[1:0] bits in CMCSR. Figure 14.3 shows the timing. Peripheral clock (Pφ) Clock N Clock N + 1 Count clock CMCNT NN + 1 Figure 14.3 Count Timing

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 730 of 1692 REJ09B0393-0100

14.4 Interrupts

14.4.1 Interrupt Sources and DTC/DMA Transfer Requests

The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt. When both the interrupt request flag (CMF) and the interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 6, Interrupt Controller (INTC). Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out, another interrupt will be generated. The direct memory access controller (DMAC) can be set to be activated when a compare match interrupt is requested. In this case, an interrupt is not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC. The data transfer controller (DTC) can be activated by an interrupt request. In this case, the priority between channels is fixed. For details, refer to section 8, Data Transfer Controller (DTC).

14.4.2 Timing of Compare Match Flag Setting

When CMCOR and CMCNT match, a compare match signal is generated at the last state in which the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 14.4 shows the timing of CMF bit setting.

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 731 of 1692 REJ09B0393-0100 Peripheral clock (Pφ) Counter clock CMCNT CMCOR CMF N Clock N + 1 N Figure 14.4 Timing of CMF Setting

14.4.3 Timing of Compare Match Flag Clearing

The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by the DMAC.

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 732 of 1692 REJ09B0393-0100

14.5 Usage Notes

14.5.1 Conflict between Write and Compare-Match Pro cesses of CMCNT

When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows the timing to clear the CMCNT counter. CMCNT T1 T2 CMCNT H'0000N Peripheral clock (Pφ) Address signal Internal write signal Counter clear signal CMCSR write cycle Figure 14.5 Conflict between Write and Compare Match Processes of CMCNT

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 733 of 1692 REJ09B0393-0100

14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the timing to write to CMCNT in words. CMCNT T1 T2 CMCNT MN Peripheral clock (Pφ) Address signal Internal write signal CMCNT count-up enable signal CMCSR write cycle Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT

Section 14 Compare Match Timer (CMT) Rev. 1.00 Jun. 26, 2008 Page 734 of 1692 REJ09B0393-0100

14.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has priority over the count-up. In this case, the count-up is not performed. The byte data on the other side, which is not written to, is also not counted and the previous contents are retained. Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNTH in bytes. CMCNTH T1 T2 CMCNTH MN CMCNTL XX Peripheral clock (Pφ) Address signal Internal write signal CMCNT count-up enable signal CMCSR write cycle Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT

14.5.4 Compare Match between CMCNT and CMCOR

Do not set a same value to CMCNT and CMCOR while the count operation of CMCNT is stopped.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 735 of 1692 REJ09B0393-0100 Section 15 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT can simultaneously generate an internal reset signal for the entire LSI. The WDT is a single channel timer that counts up the clock oscillation settling period when the system leaves the temporary standby periods that occur when the clock frequency is changed. It can also be used as a general watchdog timer or interval timer.

15.1 Features

• Can be used to ensure the clock oscillation settling time The WDT is used in leaving the temporary standby periods that occur when the clock frequency is changed.
• Can switch between watchdog timer mode and interval timer mode.
• Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type.
• Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows.
• Choice of eight counter input clocks Eight clocks (Pφ × 1 to Pφ × 1/16384) that are obtained by dividing the peripheral clock can be selected.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 737 of 1692 REJ09B0393-0100

15.2 Input/Output Pin

Table 15.1 shows the pin configuration of the WDT. Table 15.1 Pin Configuration Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs the count er overflow signal in watchdog timer mode

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 738 of 1692 REJ09B0393-0100

15.3 Register Descriptions

The WDT has the following registers. Table 15.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFE0002 16 * Watchdog timer control/status register WTCSR R/W H'18 H'FFFE0000 16 * Watchdog reset control/status register WRCSR R/W H'1F H'FFFE0004 16 * Note: * For the access size, see section 15.3.4, Notes on Register Access.

15.3.1 Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a power-on reset caused by the RES pin or in software standby mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 15.3.4, Notes on Register Access, for details. 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W:

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 739 of 1692 REJ09B0393-0100

15.3.2 Watchdog Timer Contro l/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby mode. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 15.3.4, Notes on Register Access, for details. 7654321 0 00011000 R/(W) R/W R/W R R R/W R/W R/W Bit: Initial value: R/W: IOVF WT/ IT TME - - CKS[2:0] Bit Bit Name Initial Value R/W Description

7 IOVF 0 R/(W) Interval Timer Overflow

Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition]

• When 0 is written to IOVF after reading IOVF

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 740 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

6 WT/ IT 0 R/W Timer Mode Select

Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when the WDT is running, the up-count may not be performed correctly.

5 TME 0 R/W Timer Enable

Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 741 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown in the table is the value when the peripheral clock (Pφ) is 40 MHz. Bits 2 to 0 Clock Ratio Overflow Cycle 000: 1 × Pφ 6.4 µs 001: 1/64 × Pφ 409.6 µs 010: 1/128 × Pφ 819.2 ms 011: 1/256 × Pφ 1.64 ms 100: 1/512 × Pφ 3.3 ms 101: 1/1024 × Pφ 6.6 ms 110: 1/4096 × Pφ 26.2 ms 111: 1/16384 × Pφ 104.9 ms 2 to 0 CKS[2:0] 000 R/W Note: If bits CKS[2:0] are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 742 of 1692 REJ09B0393-0100

15.3.3 Watchdog Reset Cont rol/Status Register (WRCSR)

WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in software standby mode. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 15.3.4, Notes on Register Access, for details. 7654321 0 00011111 R/(W) R/W R/W R R R R R Bit: Initial value: R/W: WOVF RSTE RSTS - - - - - Bit Bit Name Initial Value R/W Description

7 WOVF 0 R/(W) Watchdog Timer Overflow

Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition]

• When 0 is written to WOVF after reading WOVF

6 RSTE 0 R/W Reset Enable

Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * LSI not reset internally, but WTCNT and WTCSR reset within WDT.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 743 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 RSTS 0 R/W Reset Select

Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 to 0  All 1 R Reserved These bits are always read as 1. The write value should always be 1.

15.3.4 Notes on Register Access

The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 15.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. H'5A 15 8 7 0 H'A5 15 8 7 0 Write dataAddress: H'FFFE0002 WTCNT write Write dataAddress: H'FFFE0000 WTCSR write Figure 15.2 Writing to WTCNT and WTCSR

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 744 of 1692 REJ09B0393-0100 (2) Writing to WRCSR WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 15.3. To write 0 to the WOVF bit, write H'A5 to the upper byte and write the write data to the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Address: H'FFFE0004 Address: H'FFFE0004 H'A5 Write data 15 8 7 0 H'5A 15 8 7 0 Writing 0 to the WOVF bit Writing to the RSTE and RSTS bits Write data Figure 15.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 745 of 1692 REJ09B0393-0100

15.4 WDT Usage

15.4.1 Changing the Frequency

To change the frequency used by the PLL, use the WDT. 1. Before changing the frequenc y, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resu mes supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 5. The counter stops at the value of H'00. 6. Before changing WTCNT after execution of the frequency change instruction, always confirm that the value of WTCNT is H'00 by reading from WTCNT.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 746 of 1692 REJ09B0393-0100

15.4.2 Using Watchdog Timer Mode

1. Set the WT/ IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 15.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64 × Pφ clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for 128 × Pφ clock cycles. 6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 747 of 1692 REJ09B0393-0100 H'FF H'00 Overflow H'00 written in WTCNT Internal reset signal* WDTOVF signal WTCNT value WDTOVF and internal reset generated WT/IT: TME: Timer mode select bit Timer enable bit H'00 written in WTCNT Time 128 × Pφ clock cycles 64 × Pφ clock cycles Note: * Internal reset signal occurs only when the RSTE bit is set to 1. [Legend] WT/IT = 1 TME = 1 WOVF = 1 WT/IT = 1 TME = 1 Figure 15.4 Operation in Watchdog Timer Mode

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 748 of 1692 REJ09B0393-0100

15.4.3 Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/ IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. H'FF ITI ITI ITI ITI H'00 WTCNT value ITI: Interval timer interrupt request generation WT/IT = 0 TME = 1 Time Overflow Overflow Overflow Overflow [Legend] Figure 15.5 Operation in Interval Timer Mode

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 749 of 1692 REJ09B0393-0100

15.5 Usage Notes

Pay attention to the following points when using the WDT in either the interval timer or watchdog timer mode.

15.5.1 Timer Variation

After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation.

15.5.2 Prohibition against Setting H'FF to WTCNT

When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits.

15.5.3 System Reset by WDTOVF Signal

If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 15.6. RES WDTOVF Reset input Reset signal to entire system Figure 15.6 Example of System Reset Circuit Using WDTOVF Signal

Section 15 Watchdog Timer (WDT) Rev. 1.00 Jun. 26, 2008 Page 750 of 1692 REJ09B0393-0100

15.5.4 Manual Reset in Watchdog Timer Mode

When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be pended until the CPU acquires the bus mastership. However, if the duration from generation of the manual reset to the bus cycle end is equal to or longer than the duration of the internal manual reset activated, the occurrence of the internal manual reset source is ignored instead of being pended, and the manual reset exception handling is not executed.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 751 of 1692 REJ09B0393-0100 Section 16 Serial Communication Interface (SCI) This LSI has four channels (SH7286 and SH7285) or two channels (SH7243) of independent serial communication interface (SCI). The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function).

16.1 Features

• Choice of asynchronous or clock synchronous serial communication mode
• Asynchronous mode:  Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are twelve selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Multiprocessor communications  Receive error detection: Parity, overrun, and framing errors  Break detection: Break is detected by reading the RXD pin level directly when a framing error occurs.
• Clock synchronous mode:  Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function.  Data length: 8 bits  Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so high- speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal clock) or SCK pin (external clock)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 753 of 1692 REJ09B0393-0100

16.2 Input/Output Pins

The SCI has the serial pins summarized in table 16.1. Table 16.1 Pin Configuration Channel Pin Name * I/O Function

0 SCK0 I/O SCI0 clock input/output

RXD0 Input SCI0 receive data input TXD0 Output SCI0 transmit data output

1 SCK1 I/O SCI1 clock inpu t/output (SH7286 and SH7285)

RXD1 Input SCI1 receive data input (SH7286 and SH7285) TXD1 Output SCI1 transmit data output (SH7286 and SH7285)

2 SCK2 I/O SCI2 clock input/output

RXD2 Input SCI2 receive data input TXD2 Output SCI2 transmit data output

4 SCK4 I/O SCI4 clock inpu t/output (SH7286 and SH7285)

RXD4 Input SCI4 receive data input (SH7286 and SH7285) TXD4 Output SCI4 transmit data output (SH7286 and SH7285) Note: * Pin names SCK, RXD, and TXD are used in the description for all channels, omitting the channel designation.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 754 of 1692 REJ09B0393-0100

16.3 Register Descriptions

The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to section 30, List of Registers. Table 16.2 Register Configuration Channel Register Name Abbrevia- tion R/W Initial Value Address Access Size Serial mode register_0 SCSMR_0 R/W H'00 H'FFFF8000 8 Bit rate register_0 SCBRR_0 R/W H'FF H'FFFF8002 8 Serial control register_0 SCSCR_0 R/W H'00 H'FFFF8004 8 Transmit data register_0 SCTDR_0   H'FFFF8006 8 Serial status register_0 SCSSR_0 R/W H'84 H'FFFF8008 8 Receive data register_0 SCRDR_0   H'FFFF800A 8 Serial direction control register_0 SCSDCR_0 R/W H'F2 H'FFFF800C 8 Serial port register_0 SC SPTR_0 R/W H'0x H'FFFF800E 8 Serial mode register_1 SCSMR_1 R/W H'00 H'FFFF8800 8 Bit rate register_1 SCBRR_1 R/W H'FF H'FFFF8802 8 Serial control register_1 SCSCR_1 R/W H'00 H'FFFF8804 8 Transmit data register_1 SCTDR_1   H'FFFF8806 8 Serial status register_1 SCSSR_1 R/W H'84 H'FFFF8808 8 Receive data register_1 SCRDR_1   H'FFFF880A 8 Serial direction control register_1 SCSDCR_1 R/W H'F2 H'FFFF880C 8 (only for SH7286 and SH7285) Serial port register_1 SC SPTR_1 R/W H'0x H'FFFF880E 8 Serial mode register_2 SCSMR_2 R/W H'00 H'FFFF9000 8 Bit rate register_2 SCBRR_2 R/W H'FF H'FFFF9002 8 Serial control register_2 SCSCR_2 R/W H'00 H'FFFF9004 8 Transmit data register_2 SCTDR_2   H'FFFF9006 8 Serial status register_2 SCSSR_2 R/W H'84 H'FFFF9008 8 Receive data register_2 SCRDR_2   H'FFFF900A 8 Serial direction control register_2 SCSDCR_2 R/W H'F2 H'FFFF900C 8 Serial port register_2 SC SPTR_2 R/W H'0x H'FFFF900E 8

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 755 of 1692 REJ09B0393-0100 Channel Register Name Abbrevia- tion R/W Initial Value Address Access Size Serial mode register_4 SCSMR_4 R/W H'00 H'FFFFA000 8 Bit rate register_4 SCBRR_4 R/W H'FF H'FFFFA002 8 Serial control register_4 SCSCR_4 R/W H'00 H'FFFFA004 8 Transmit data register_4 SCTDR_4   H'FFFFA006 8 Serial status register_4 SCSSR_4 R/W H'84 H'FFFFA008 8 Receive data register_4 SCRDR_4   H'FFFFA00A 8 Serial direction control register_4 SCSDCR_4 R/W H'F2 H'FFFFA00C 8 (only for SH7286 and SH7285) Serial port register_4 SCSPTR_4 R/W H'0x H'FFFFA00E 8

16.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. Bit: Initial value: R/W: 7654321 0

16.3.2 Receive Data Register (SCRDR)

SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and completes operation. After that, SCRSR is ready to receive data. Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously. SCRDR is a read-only register and cannot be written to by the CPU. Bit: Initial value: R/W: 7654321 0

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 756 of 1692 REJ09B0393-0100

16.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to SCTSR directly. Bit: Initial value: R/W: 7654321 0

16.3.4 Transmit Data Register (SCTDR)

SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be written or read to by the CPU. Bit: Initial value: R/W: 7654321 0

16.3.5 Serial Mode Register (SCSMR)

SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W C/A CHR PE O/ E STOP MP CKS[1:0]

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 757 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

7 C/ A 0 R/W Communication Mode

Selects whether the SCI operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode

6 CHR 0 R/W Character Length

Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. 0: 8-bit data 1: 7-bit data

5 PE 0 R/W Parity Enable

Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 758 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

4 O/ E 0 R/W Parity mode

Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity 1: Odd parity If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.

3 STOP 0 R/W Stop Bit Length

Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. 0: One stop bit* 1: Two stop bits* When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1 bits are added at the end of each transmitted character.

2 MP 0 R/W Multiprocessor Mode (only in asynchronous mode)

Enables or disables multiprocessor mode. The PE and O/E bit settings are ignored in multiprocessor mode. 0: Multiprocessor mode disabled 1: Multiprocessor mode enabled

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 759 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available; Pφ, Pφ/4, Pφ/16, and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.10, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: P φ: Peripheral clock

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 760 of 1692 REJ09B0393-0100

16.3.6 Serial Control Register (SCSCR)

SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TIE RIE TE RE MPIE TEIE CKE[1:0] Bit Bit Name Initial value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

Enables or disables a transmit-data-empty interrupt (TXI) to be issued when the TDRE flag in the serial status register (SCSSR) is set to 1 after serial transmit data is sent from the transmit data register (SCTDR) to the transmit shift register (SCTSR). TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE = 1 or by clearing the TIE bit to 0. 0: Transmit-data-empty interrupt request (TXI) is disabled 1: Transmit-data-empty interrupt request (TXI) is enabled

6 RIE 0 R/W Receive Interrupt Enable

Enables or disables a receive-data-full interrupt (RXI) and a receive error interrupt (ERI) to be issued when the RDRF flag in SCSSR is set to 1 after the serial data received is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR). RXI can be canceled by clearing the RDRF flag after reading RDRF =1. ERI can be canceled by clearing the FER, PER, or ORER flag to 0 after reading 1 from the flag. Both RXI and ERI can also be canceled by clearing the RIE bit to 0. 0: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 761 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

5 TE 0 R/W Transmit Enable

Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled. Select the transmit format in the serial mode register (SCSMR) before setting TE to 1.

4 RE 0 R/W Receive Enable

Enables or disables the SCI serial receiver. 0: Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR before setting RE to 1.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (only when MP = 1 in

SCSMR in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF, FER, and ORER status flags in SCSSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared to 0 and normal receiving operation is resumed. For details, refer to section 16.4.4, Multiprocessor Communication Function.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 762 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

2 TEIE 0 R/W Transmit End Interrupt Enable

Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled 1: Transmit end interrupt request (TEI) is enabled 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. When selecting the clock output in clock synchronous mode, set the C/A bit in SCSMR to 1 and then set bits CKE1 and CKE0. For details on clock source selection, refer to table 16.14.

• Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored.) 01: Internal clock, SCK pin used for clock output* 10: External clock, SCK pin used for clock input* 11: External clock, SCK pin used for clock input*
• Clock synchronous mode 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 763 of 1692 REJ09B0393-0100

16.3.7 Serial Status Register (SCSSR)

SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The TEND flag is a read-only bit and cannot be modified. Bit: Initial value: R/W: 7654321 0 10000100 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W TDRE RDRF ORER FER PER TEND MPB MPBT Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* Bit Bit Name Initial value R/W Description

7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether data has been transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR) and SCTDR has become ready to be written with next serial transmit data. 0: Indicates that SCTDR holds valid transmit data [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and transmit data is transferred to SCTDR while the DISEL bit of MRB in the DTC is 0 (except when the DTC transfer counter value has become H'0000). 1: Indicates that SCTDR does not hold valid transmit data [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When data is transferred from SCTDR to SCTSR and data can be written to SCTDR

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 764 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to RDRF after reading RDRF =
• When the DTC is activated by an RXI interrupt and data is transferred from SCRDR while the DISEL bit of MRB in the DTC is 0 (except when the DTC transfer counter value has become H'0000). 1: Indicates that valid received data is stored in SCRDR [Setting condition]
• When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note: SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register (SCSCR) is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the received data will be lost.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 765 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to ORER after reading ORER = 1: Indicates that an overrun error occurred during reception* [Setting condition]
• When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR, and the data received subsequently is lost. Subsequent serial reception cannot be continued while the ORER flag is set to 1.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 766 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

4 FER 0 R/(W) * Framing Error

Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to FER after reading FER = 1 1: Indicates that a framing error occurred during reception [Setting condition]
• When the SCI founds that the stop bit at the end of the received data is 0 after completing reception* Notes: 1. The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the FER flag is set to 1.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 767 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

3 PER 0 R/(W) * Parity Error

Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to PER after reading PER = 1 1: Indicates that a parity error occurred during reception* [Setting condition]
• When the number of 1s in the received data and parity does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the PER flag is set to 1.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 768 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

2 TEND 1 R Transmit End

Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition]

• When 0 is written to TDRE after reading TDRE = 1 1: Indicates that transmission has ended [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When TDRE = 1 during transmission of the last bit of a 1-byte serial transmit character Note: The TEND flag value becomes undefined if data is written to SCTDR by activating the DTC by a TXI interrupt. In this case, do not use the TEND flag as the transmit end flag.

1 MPB 0 R Multiprocessor Bit

Stores the multiprocessor bit found in the receive data. When the RE bit in SCSCR is cleared to 0, its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Specifies the multiprocessor bit value to be added to the transmit frame. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 769 of 1692 REJ09B0393-0100

16.3.8 Serial Port Register (SCSPTR)

SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to SCSPTR. When reading the value on the SCI pins, use the respective port register. For details, refer to section 24, I/O Ports. Bit: Initial value: R/W: 7654321 0 00000-01 R/W - - - R/W R/W W - EIO - - - SPB1IO SPB1DT SPB0DT- Bit Bit Name Initial value R/W Description

7 EIO 0 R/W Error Interrupt Only

Enables or disables RXI interrupts. While the EIO bit is set to 1, the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1. 0: The RIE bit enables or disables RXI and ERI interrupts. While the RIE bit is 1, RXI and ERI interrupts are sent to the INTC. 1: While the RIE bit is 1, only the ERI interrupt is sent to the INTC. 6 to 4  All 0  Reserved These bits are always read as 0. The write value should always be 0.

3 SPB1IO 0 R/W Clock Port Inpu t/Output in Serial Port

Specifies the input/output direction of the SCK pin in the serial port. To output the data specified in the SPB1DT bit through the SCK pin as a port output pin, set the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0. 0: Does not output the SPB1DT bit value through the SCK pin. 1: Outputs the SPB1DT bit value through the SCK pin.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 770 of 1692 REJ09B0393-0100 Bit Bit Name Initial value R/W Description

2 SPB1DT Undefined R/W Clock Port Data in Serial Port

Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output 1  0  Reserved This bit is always read as 0. The write value should always be 0. Serial Port Break Data Controls the TXD pin by the TE bit in SCSCR. However, TXD pin function should be selected by the pin function controller (PFC). This is a read-only bit. The read value is undefined. TE bit setting in SCSCR SPB0DT bit setting TXD pin state 0 0 Low output 0 1 High output (initial state) 1 * Transmit data output in accord with serial core logic.

0 SPB0DT 1 W

Note: * Don’t care

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 771 of 1692 REJ09B0393-0100

16.3.9 Serial Direction Control Register (SCSDCR)

The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: Initial value: R/W: 7654321 0 11110010 RRRR R / W RRR ---- D I R --- Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These bits are always read as 1. The write value should always be 1.

3 DIR 0 R/W Data Transfer Direction

Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: SCTDR contents are transmitted in LSB-first order Receive data is stored in SCRDR in LSB-first 1: SCTDR contents are transmitted in MSB-first order Receive data is stored in SCRDR in MSB-first 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1  1 R Reserved This bit is always read as 1. The write value should always be 1. 0  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 772 of 1692 REJ09B0393-0100

16.3.10 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. The SCBRR setting is calculated as follows: Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W Asynchronous mode:

• When the ABCS bit in serial extended mode register (SCSEMR) is 0 N = × 106 - 164 × 22n-1 × B Pφ
• When the ABCS bit in serial extended mode register (SCSEMR) is 1 N = × 106 - 132 × 22n-1 × B Pφ Clock synchronous mode: N = × 106 - 18 × 22n-1 × B Pφ B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 773 of 1692 REJ09B0393-0100 Table 16.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0

0 P φ 0 0

1 P φ/4 0 1

2 P φ/16 1 0

3 P φ/64 1 1

Note: The bit rate error in asynchro nous is given by the following formula:

• When the ABCS bit in serial extended mode register (SCSEMR) is 0 Pφ × 106
• When the ABCS bit in serial extended mode register (SCSEMR) is 1 Pφ × 106 Tables 16.4 to 16.6 show examples of SCBRR settings in asynchronous mode, and tables 16.7 to 16.9 show examples of SCBRR settings in clock synchronous mode.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 774 of 1692 REJ09B0393-0100 Table 16.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) Pφ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 775 of 1692 REJ09B0393-0100 Table 16.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) Pφ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 776 of 1692 REJ09B0393-0100 Table 16.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) Pφ (MHz) 34 36 38 40 50 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 31250 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 0 49 0

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 777 of 1692 REJ09B0393-0100 Table 16.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) P φ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N n N n N n N n N n N 250 3 155 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 3 140 3 155 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 500000 0 4 0 5 0 6 0 7 0 8 0 9 1000000   0 2   0 3   0 4

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 778 of 1692 REJ09B0393-0100 Table 16.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) P φ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N n N n N n N n N n N 250 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000   0 5   0 6   0 7

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 779 of 1692 REJ09B0393-0100 Table 16.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) P φ (MHz) 34 36 38 40 50 Bit Rate (bits/s) n N n N n N n N n N 250 500 1000 3 132 3 140 3 147 3 155 3 194 2500 2 212 2 224 2 237 2 249 3 77 5000 2 105 2 112 2 118 2 124 2 155 10000 1 212 1 224 1 237 1 249 2 77 25000 1 84 1 89 1 94 1 99 1 124 50000 0 169 0 179 0 189 0 199 0 249 100000 0 84 0 89 0 94 0 99 0 124 250000 0 33 0 35 0 37 0 39 0 49 500000 0 16 0 17 0 18 0 19 0 24 [Legend] Blank: No setting possible : Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 780 of 1692 REJ09B0393-0100 Table 16.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 16.11 and 16.12 list the maximum rates for external clock input. Table 16.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 1187500 0 0 40 1250000 0 0 50 1562500 0 0

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 781 of 1692 REJ09B0393-0100 Table 16.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MH z) Maximum Bit Rate (bits/s) 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000 50 12.5000 781250

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 782 of 1692 REJ09B0393-0100 Table 16.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) External Input Clock (MH z) Maximum Bit Rate (bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7 50 8.3333 8333333.3

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 783 of 1692 REJ09B0393-0100

16.4 Operation

16.4.1 Overview

For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 16.13. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 16.14. (1) Asynchronous Mode

• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks.
• An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the clock supplied by the on- chip baud rate generator and can output a clock with a frequency 16 times the bit rate.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 784 of 1692 REJ09B0393-0100 Table 16.13 SCSMR Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit Asynchronous 2 bits 1 x x x Clock synchronous 8-bit Not set None [Legend] x: Don't care Table 16.14 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use the SCK pin.

1 Clock with a frequency 16 times the bit rate

is output. 1 0 External Input a clock with frequency 16 times the bit rate. 1 0 0 Internal Serial clock is output. Clock synchronous 1 0 External Input the serial clock.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 785 of 1692 REJ09B0393-0100

16.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 16.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 786 of 1692 REJ09B0393-0100 (1) Transmit/Receive Formats Table 16.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 16.15 Serial Transfer Formats (Asynchronous Mode) PE x x x x S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SCSMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit x: Don't care

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 787 of 1692 REJ09B0393-0100 (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.14). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. (3) Transmitting and Receiving Data

• SCI Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 788 of 1692 REJ09B0393-0100 Wait Yes [1] Start initialization Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0* [2] No Set value in SCBRR [3] [4] [5] 1-bit interval elapsed? < Initialization completed> [1] Set the clock selection in SCSCR. [2] Set the data transfer format in SCSMR and SCSDCR. [3] Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [5] Set the TE bit or RE bit in SCSCR to 1. * Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting, and RXD pin is in an idle state for waiting the start bit during receiving. Set data transfer format in SCSMR and SCSDCR Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 16.3 Sample Flowchart for SCI Initialization

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 790 of 1692 REJ09B0393-0100 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. (A format in which neither parity nor multiprocessor bit is output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 791 of 1692 REJ09B0393-0100 Figure 16.5 shows an example of the operation for transmission.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

(mark state) Data Parity bit Stop bit TXI interrupt request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request TEI interrupt request Figure 16.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 793 of 1692 REJ09B0393-0100 <End> Error processing Parity error processing Yes No Clear ORER, PER, and FER flags in SCSSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER = 1? FER = 1? Break? PER = 1? Clear RE bit in SCSCR to 0 Figure 16.6 Sample Flowchart for Receiving Serial Data (2)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 794 of 1692 REJ09B0393-0100 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. A. Parity check: The SCI counts the number of 1s in the received data and checks whether the count matches the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). B. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. C. Status check: The SCI checks whether the RD RF flag is 0 and the received data can be transferred from the receive shift register (SCRSR) to SCRDR. If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in SCRDR. If a receive error is detected, the SCI operates as shown in table 16.16. Note: When a receive error occurs, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0. 4. If the EIO bit in SCSPTR is cleared to 0 and th e RIE bit in SCSCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Table 16.16 Receive Errors and Error Conditions Receive Error Abbreviation Erro r Condition Data Transfer Overrun error ORER When the next data reception is completed while the RDRF flag in SCSSR is set to 1 The received data is not transferred from SCRSR to SCRDR. Framing error FER When the stop bit is 0 The received data is transferred from SCRSR to SCRDR. Parity error PER When the received data does not match the even or odd parity specified in SCSMR The received data is transferred from SCRSR to SCRDR.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 795 of 1692 REJ09B0393-0100 Figure 16.7 shows an example of the operation for reception.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/1 1

Figure 16.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 796 of 1692 REJ09B0393-0100

16.4.3 Clock Synchronous Mode

In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 16.8 shows the general format in clock synchronous serial communication. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High level except in continuous transfer Figure 16.8 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 797 of 1692 REJ09B0393-0100 In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source, see table 16.14. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. (3) Transmitting and Receiving Data

• SCI Initialization (Clock Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Figure 16.9 shows a sample flowchart for initializing the SCI.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 798 of 1692 REJ09B0393-0100 Wait No Yes <Transfer starts> Start initialization Set data transfer format in SCSMR Set value in SCBRR Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCSCR to 0* [2] [3] [4] [5] 1-bit interval elapsed? Set the PFC for the external pins to be used (SCK, TXD, RXD) Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) [1] [1] Set the clock selection in SCSCR. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. [5] Set the TE bit or RE bit in SCR to 1. * Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in clock synchronous mode, outputting clocks from the SCK pin starts. Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR Figure 16.9 Sample Flowchart for SCI Initialization

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 802 of 1692 REJ09B0393-0100 Error handling Clear ORER flag in SCSSR to 0 End Overrun error handling ORER = 1? Yes No Figure 16.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the received data in SCRDR. If a receive error is detected, the SCI operates as shown in table 16.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the RDRF flag to 0. 3. After setting RDRF to 1, if the receive-data- full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI).

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 804 of 1692 REJ09B0393-0100 Yes No Start of transmission and reception Error processing No Yes ORER = 1? All data received? Read TDRE flag in SCSSR No Yes TDRE = 1? Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 No Yes RDRF = 1? Read ORER flag in SCSSR Read RDRF flag in SCSSR [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [3] SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to SCTDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the SCRDR value is read. Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Clear TE and RE bits in SCSCR to 0 Write transmit data to SCTDR, and clear TDRE flag in SCSSR to 0 End of transmission and reception Figure 16.14 Sample Flowchart for Transmitting/Receiving Serial Data

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 805 of 1692 REJ09B0393-0100

16.4.4 Multiprocessor Co mmunication Function

Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 16.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCSCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 806 of 1692 REJ09B0393-0100 Transmitting station Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial transmission line Serial data ID transmission cycle = receiving station specification Data transmission cycle = Data transmission to receiving station specified by ID (MPB = 1) (MPB = 0) H'01 H'AA [Legend] MPB: Multiprocessor bit Figure 16.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 807 of 1692 REJ09B0393-0100

16.4.5 Multiprocessor Seri al Data Transmission

Figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. Keep MPBT at 1 until the ID is actually transmitted. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. No <End> [1] Yes Initialization Start transmission Read TDRE flag in SCSSR [2] No Yes No Yes Read TEND flag in SCSSR [3] No Yes [4] Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC TDRE = 1? All data transmitted? TEND = 1? Break output? Clear TDRE flag to 0 [1] SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write data for transmission to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. After initializing the SCI, when an ID is written to SCTDR register so as to transmit the ID, data is immediately transferred, and then the TDRE flag is set to 1. The MPBT bit must be held 1 because the ID is not transmitted from the TXD pin at this time. When the TDRE flag is set to 1 after data following the ID is written to SCTDR, clear the MPBT bit to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Write transmit data to SCTDR and set MPBT bit in SCSSR Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart

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16.4.6 Multiprocessor S erial Data Reception

Figure 16.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 16.17 shows an example of SCI operation for multiprocessor format reception. MPIE RXD RXD SCRDR value

0 D0 D1 D7 1 1 0 D0 D1 D7 01

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit Data (ID2)Start bit Stop bit Start bit Data (Data2) Stop bit RXI interrupt request (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and SCRDR retains its state ID1 (a) Data does not match station’s ID MPIE SCRDR value (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt processing routine MPIE bit is set to 1 again ID2 (b) Data matches station’s ID Data2ID1 MPIE = 0 MPIE = 0 Figure 16.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 809 of 1692 REJ09B0393-0100 Yes <End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCSCR to 0 Error processing (Continued on next page) [5] No Yes FER = 1? or ORER = 1? RDRF = 1? All data received? Set MPIE bit in SCSCR to 1 [2] Read ORER and FER flags in SCSSR Read RDRF flag in SCSSR [3] Read receive data in SCRDR No Yes This station’s ID? Read ORER and FER flags in SCSSR Yes No Read RDRF flag in SCSSR No Yes FER = 1? or ORER = 1? Read receive data in SCRDR RDRF = 1? [1] SCI initialization: Set the RXD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCSCR to 1. [3] SCI status check, ID reception and comparison: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SCSSR and check that the RDRF flag is set to 1, then read the data in SCRDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD pin value. Figure 16.18 Sample Multiprocessor Serial Reception Flowchart (1)

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 810 of 1692 REJ09B0393-0100 <End> Error processing Yes No Clear ORER and FER flags in SCSSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER = 1 FER = 1 Break? Clear RE bit in SCSCR to 0 [5] Figure 16.18 Sample Multiprocessor Serial Reception Flowchart (2)

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16.5 SCI Interrupt Sources and DTC

The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 16.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt request is generated. This request can be used to activate the data transfer controller (DTC) to transfer data. The TDRE flag is automatically cleared to 0 when data is written to the transmit data register (SCTDR) through the DTC. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request can be used to activate the DTC to transfer data. The RDRF flag is automatically cleared to 0 when data is read from the receive data register (SCRDR) through the DTC. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. This request cannot be used to activate the DTC. When processing the received data through the DTC and handling the receive error by an interrupt requested to the CPU, set the RIE bit to 1 and set the EIO bit in SCSPTR to 1 to issue an interrupt to the CPU only when a receive error is detected. If the EIO bit is cleared to 0, an interrupt is issued to the CPU even when correct data is received. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request cannot be used to activate the DTC. The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that transmission has been completed. Table 16.17 SCI Interrupt Sources Interrupt Source Description DTC Activation ERI Interrupt caused by receive error (ORER, FER, or PER) Not possible RXI Interrupt caused by receive data full (RDRF) Possible TXI Interrupt caused by transmit data empty (TDRE) Possible TEI Interrupt caused by transmit end (TENT) Not possible

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16.6 Serial Port Register (SCSPTR) and SCI Pins

The relationship between SCSPTR and the SCI pins is shown in figures 16.19 and 16.20. SPTRW: SCSPTR write Note: * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Reset Internal data bus Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* Bit 3 Bit 2 Reset QD R SCKIO SCK C QD R SCKDT SPTRW SPTRW C [Legend] Figure 16.19 SCKIO Bit, SCKDT Bit, and SCK Pin

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 813 of 1692 REJ09B0393-0100 [Legend] SPTRW: SCSPTR write Internal data bus Transmit enable signal Bit 0 Reset Serial transmit data TXD QD R SPBDT SPTRW C Figure 16.20 SPBDT Bit and TXD Pin

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16.7 Usage Notes

16.7.1 SCTDR Writing and TDRE Flag

The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that the TDRE flag is set to 1.

16.7.2 Multiple Receive Error Occurrence

If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in table 16.18. When an overrun error occurs, data is not transferred from the receive shift register (SCRSR) to the receive data register (SCRDR) and the received data will be lost. Table 16.18 SCSSR Status Flag Values and Transfer of Received Data SCSSR Status Flags Receive Errors Generated RDRF ORER FER PER Receive Data Transfer from SCRSR to SCRDR Overrun error 1 1 0 0 Not transferred Framing error 0 0 1 0 Transferred Parity error 0 0 0 1 Transferred Overrun error + framing error 1 1 1 0 Not transferred Overrun error + parity error 1 1 0 1 Not transferred Framing error + parity error 0 0 1 1 Transferred Overrun error + framing error + parity error 1 1 1 1 Not transferred

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16.7.3 Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCRDR is halted in the break state, the SCI receiver continues to operate.

16.7.4 Sending a Break Signal

The I/O condition and level of the TXD pin are determined by SPB0DT bit in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin.

16.7.5 Receive Data Sampling Timing an d Receive Margin (Asynchronous Mode)

The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.21.

Section 16 Serial Communication Interface (SCI) Rev. 1.00 Jun. 26, 2008 Page 816 of 1692 REJ09B0393-0100 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 D0 D1 16 clocks 8 clocks Base clock Receive data (RXD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Figure 16.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: D - 0.5 N Where: M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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16.7.6 Note on Using DTC

When the external clock source is used for the clock for synchronization, input the external clock after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified through the DTC. If a transmit clock is input within four cycles after SCTDR is modified, a malfunction may occur (figure 16.22). SCK TDRE TXD D0 D2 D6 D1 D3 D4 D5 D7 t Note: When using the external clock, t must be set to larger than 4 cycles. Figure 16.22 Example of Clock Synchronous Transfer Using DTC When data is written to SCTDR by activating the DTC by a TXI interrupt, the TEND flag value becomes undefined. In this case, do not use the TEND flag as the transmit end flag.

16.7.7 Note on Using External Clock in Clock Synchronous Mode

TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1.

16.7.8 Module Standby Mode Setting

SCI operation can be disabled or enabled using the standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 28, Power-Down Modes.

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Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 819 of 1692 REJ09B0393-0100 Section 17 Serial Communication Interface with FIFO (SCIF) This LSI has one channel of serial communication interface with FIFO (SCIF) that supports both asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication.

17.1 Features

• Asynchronous serial communication:  Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Receive error detection: Parity, framing, and overrun errors  Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RXD level directly from the serial port register when a framing error occurs.
• Clocked synchronous serial communication:  Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clocked synchronous communication function. There is one serial data communication format.  Data length: 8 bits  Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external)

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17.2 Input/Output Pins

Table 17.1 shows the pin configuration of the SCIF. Table 17.1 Pin Configuration Channel Pin Name Symbol I/O Function Serial clock pins SCK3 I/O Clock I/O Receive data pins RXD3 Input Receive data input Transmit data pins TXD3 Ou tput Transmit data output

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17.3 Register Descriptions

The SCIF has the following registers. Table 17.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size Serial mode register_3 SCSMR_3 R/W H'0000 H'FFFE9800 16 Bit rate register_3 SCBRR_3 R/W H'FF H'FFFE9804 8 Serial control register_3 SCSCR_3 R/W H'0000 H'FFFE9808 16 Transmit FIFO data register_3 SCFTDR_3 W Undefined H'FFFE980C 8 Serial status register_3 SCFSR_3 R/(W) * H'0060 H'FFFE9810 16 Receive FIFO data register_3 SCFRDR_3 R Undefined H'FFFE9814 8 FIFO control register_3 SCFCR_3 R/W H'0000 H'FFFE9818 16 FIFO data count register_3 SCFDR_3 R H'0000 H'FFFE981C 16 Serial port register_3 SCSPTR_3 R/W H'0050 H'FFFE9820 16 Line status register_3 SCLSR_3 R/(W) * H'0000 H'FFFE9824 16 Serial extended mode register_3 SCSEMR_3 R/W H'00 H'FFFE9900 8 Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified. 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified.

17.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO data register (SCFRDR). The CPU cannot read or write to SCRSR directly. 7654321 0 Bit: Initial value: R/W:

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17.3.2 Receive FIFO Da ta Register (SCFRDR)

SCFRDR is a register that stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When SCFRDR is full of receive data, subsequent serial data is lost. SCFRDR is initialized to an undefined value by a power-on reset. 7654321 0 RRRRRRRR Bit: Initial value: R/W:

17.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly. 7654321 0 Bit: Initial value: R/W:

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17.3.4 Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. SCFTDR is initialized to an undefined value by a power-on reset. 7654321 0 WWWWWWWW Bit: Initial value: R/W:

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 825 of 1692 REJ09B0393-0100

17.3.5 Serial Mode Register (SCSMR)

SCSMR specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/W R/W R/W R/W R/W R R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Selects whether the SCIF operates in asynchronous or clocked synchronous mode. 0: Asynchronous mode 1: Clocked synchronous mode Selects 7-bit or 8-bit data length in asynchronous mode. In clocked synchronous mode, the data length is always 8 bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 826 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clocked synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clocked synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity* Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 827 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clocked synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select Select the internal clock source of the on-chip baud rate generator. For further information on the clock source, bit rate register settings, and baud rate, see section 17.3.8, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: P φ: Peripheral clock

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 828 of 1692 REJ09B0393-0100

17.3.6 Serial Control Register (SCSCR)

SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/W R/W R/W R/W R/W R R/W R/W Bit: Initial value: R/W: - - - - - - - - TIE RIE TE RE REIE - CKE[1:0] Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to 1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 829 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Enables or disables the receive FIFO data full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to 1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to 1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to 1. 0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Enables or disables the serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 830 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Enables or disables the serial receiver of the SCIF. 0: Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clocked synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1.

3 REIE 0 R/W Receive Error Interrupt Enable

Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. Set so If SCIF wants to inform INTC of ERI or BRI interrupt requests during DMA transfer.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 831 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on CKE[1:0], the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clocked synchronous mode, set the C/A bit in SCSMR to 1, and then set CKE[1:0].

• Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited
• Clocked synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 832 of 1692 REJ09B0393-0100

17.3.7 Serial Status Register (SCFSR)

SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. When receive data in the receive FIFO data register is transferred by using the DTC, the receive data is cleared in the receive FIFO data register. At the same time, the PER and FER bits in SCFSR are cleared. If DTC is used, an error is not judged by the FER or PER bit. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000001100000 R R R R R R R R R/(W) * R/(W)* R/(W)* R/(W)* R R R/(W) * R/(W)* Bit: Initial value: R/W: Note: Only 0 can be written to clear the flag after 1 is read.* PER[3:0] FER[3:0] ER TEND TDFE BRK FER PER RDF DR Bit Bit Name Initial Value R/W Description 15 to 12 PER[3:0] 0000 R Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 after the ER bit in SCFSR is set, represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER[3:0] shows 0000. 11 to 8 FER[3:0] 0000 R Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 after the ER bit in SCFSR is set, represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER[3:0] shows 0000.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 833 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

7 ER 0 R/(W) * Receive Error

Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity.* 0: Receiving is in progress or has ended normally [Clearing conditions]

• ER is cleared to 0 a power-on reset
• ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions]
• ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation*
• ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 834 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

6 TEND 1 R/(W) * Transmit End

Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition]

• TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR* 1: End of transmission [Setting conditions]
• TEND is set to 1 when the chip is a power-on reset
• TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR)
• TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: * Do not use this bit as a transmit end flag when the DMAC writes data to SCFTDR due to a TXI interrupt request.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 835 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

5 TDFE 1 R/(W) * Transmit FIFO Data Empty

Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions]

• TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written
• TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR by the DMAC.
• TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR by the DTC. (Except the transfer counter value of DTC has become H'0000) 1: The quantity of transmit data in SCFTDR is less than the specified transmission trigger number* [Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the quantity of transmit data in SCFTDR becomes less than the specified transmission trigger number as a result of transmission. Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 836 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

4 BRK 0 R/(W) * Break Detection

Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions]

• BRK is cleared to 0 when the chip is a power-on reset
• BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1: Break signal received* [Setting condition]
• BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes.

3 FER 0 R Framing Error Indication

Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions]

• FER is cleared to 0 when the chip undergoes a power-on reset
• FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition]
• FER is set to 1 when a framing error is present in the next data read from SCFRDR

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 837 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

2 PER 0 R Parity Error Indication

Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions]

• PER is cleared to 0 when the chip undergoes a power-on reset
• PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the next data read from SCFRDR [Setting condition]
• PER is set to 1 when a parity error is present in the next data read from SCFRDR

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 838 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

1 RDF 0 R/(W) * Receive FIFO Data Full

Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG[1:0] bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions]

• RDF is cleared to 0 by a power-on reset, standby mode
• RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written
• RDF is cleared to 0 when SCFRDR is read by the DMAC until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number.
• RDF is cleared to 0 when SCFRDR is read by the DTC until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number. (Except the transfer counter value of DTC has become H'0000) 1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition]
• RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is stored in SCFRDR* Note: * As SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 becomes the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 839 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

0 DR 0 R/(W) * Receive Data Ready

Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clocked synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions]

• DR is cleared to 0 when the chip undergoes a power-on reset
• DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written.
• DR is cleared to 0 when all receive data in SCFRDR are read by the DMAC. 1: Next receive data has not been received [Setting condition]
• DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 ETU from the last stop bit.* Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: elementary time unit) Note: * Only 0 can be written to clear the flag after 1 is read.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 840 of 1692 REJ09B0393-0100

17.3.8 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS[1:0] bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: The SCBRR setting is calculated as follows: Asynchronous mode:

• When the ABCS bit in serial extended mode register (SCSEMR) is 0 N = × 106 − 164 × 22n-1 × B Pφ
• When the ABCS bit in serial extended mode register (SCSEMR) is 1 N = × 106 − 132 × 22n-1 × B Pφ Clocked synchronous mode: N = × 106 − 18 × 22n-1 × B Pφ B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting must satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 17.3.)

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 841 of 1692 REJ09B0393-0100 Table 17.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0 The bit rate error in asynchronous is given by the following formula:

• When the ABCS bit in serial extended mode register (SCSEMR) is 0 Pφ × 106
• When the ABCS bit in serial extended mode register (SCSEMR) is 1 Pφ × 106 Table 17.4 lists examples of SCBRR settings in asynchronous mode, and table 17.5 lists examples of SCBRR settings in clocked synchronous mode.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 842 of 1692 REJ09B0393-0100 Table 17.4 Bit Rates and SCBRR Settings (Asynchronous Mode) P φ (MHz) 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) 110 2 177 –0.25 2 212 0.03 150 2 129 0.16 2 155 0.16 300 2 64 0.16 2 77 0.16 600 1 129 0.16 1 155 0.16 1200 1 64 0.16 1 77 0.16 2400 0 129 0.16 0 155 0.16 4800 0 64 0.16 0 77 0.16 9600 0 32 –1.36 0 38 0.16 19200 0 15 1.73 0 19 0.16 31250 0 9 0.00 0 11 0.00 38400 0 7 1.73 0 9 –2.34 P φ (MHz) 12.288 14.7456 16 19.6608 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 3 64 0.70 3 70 0.03 3 86 0.31 150 2 159 0.00 2 191 0.00 2 207 0.16 2 255 0.00 300 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00 600 1 159 0.00 1 191 0.00 1 207 0.16 1 255 0.00 1200 1 79 0.00 1 95 0.00 1 103 0.16 1 127 0.00 2400 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00 4800 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00 9600 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00 19200 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00 31250 0 11 2.40 0 14 –1.70 0 15 0.00 0 19 –1.70 38400 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 843 of 1692 REJ09B0393-0100 P φ (MHz) 20 24 24.576 28.7 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 88 –0.25 3 106 –0.44 3 108 0.08 3 126 0.31 150 3 64 0.16 3 77 0.16 3 79 0.00 3 92 0.46 300 2 129 0.16 2 155 0.16 2 159 0.00 2 186 –0.08 600 2 64 0.16 2 77 0.16 2 79 0.00 2 92 0.46 1200 1 129 0.16 1 155 0.16 1 159 0.00 1 186 –0.08 2400 1 64 0.16 1 77 0.16 1 79 0.00 1 92 0.46 4800 0 129 0.16 0 155 0.16 0 159 0.00 0 186 –0.08 9600 0 64 0.16 0 77 0.16 0 79 0.00 0 92 0.46 19200 0 32 –1.36 0 38 0.16 0 39 0.00 0 46 –0.61 31250 0 19 0.00 0 23 0.00 0 24 –1.70 0 28 –1.03 38400 0 15 1.73 0 19 –2.34 0 19 0.00 0 22 1.55 P φ (MHz) 30 33 40 50 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 132 0.13 3 145 0.33 3 117 –0.25 3 221 –0.02 150 3 97 –0.35 3 106 0.39 3 129 0.16 3 162 –0.15 300 2 194 0.16 2 214 –0.07 3 64 0.16 3 80 0.47 600 2 97 –0.35 2 106 0.39 2 129 0.16 2 162 –0.15 1200 1 194 0.16 1 214 –0.07 2 64 0.16 2 80 0.47 2400 1 97 –0.35 1 106 0.39 1 129 0.16 1 162 –0.15 4800 0 194 –1.36 0 214 –0.07 1 64 0.16 1 80 0.47 9600 0 97 –0.35 0 106 0.39 0 129 0.16 0 162 –0.15 19200 0 48 –0.35 0 53 –0.54 0 64 0.16 0 80 –0.47 31250 0 29 0.00 0 32 0.00 0 39 0.00 0 49 0 38400 0 23 1.73 0 26 –0.54 0 32 –1.36 0 40 –0.76 Note: Settings with an error of 1% or less are recommended.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 844 of 1692 REJ09B0393-0100 Table 17.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode) P φ (MHz) 16 28.7 30 33 40 50 Bit Rate (bit/s) n N n N n N n N n N n N 110 250 3 249 500 3 124 3 223 3 233 3 255 — — — — 1 k 2 249 3 111 3 116 3 125 3 152 3 194 2.5 k 2 99 2 178 2 187 2 200 2 243 3 77 5 k 1 199 2 89 2 93 2 100 2 121 2 155 10 k 1 99 1 178 1 187 1 200 2 60 2 77 25 k 0 159 1 71 1 74 1 80 1 97 1 124 50 k 0 79 0 143 0 149 0 160 1 48 0 249 100 k 0 39 0 71 0 74 0 80 0 97 0 124 250 k 0 15 — — 0 29 0 31 0 38 0 49 500 k 0 7 — — 0 14 0 15 0 19 0 24

1 M 0 3 0 7 0 9 — —

2 M 0 1 0 3 — —

[Legend] Blank: No setting possible —: Setting possible, but error occurs

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 845 of 1692 REJ09B0393-0100 Table 17.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 17.7 and 17.8 list the maximum bit rates when the external clock input is used. Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0 33 1031250 0 0 40 1250000 0 0 50 1562500 0 0

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 846 of 1692 REJ09B0393-0100 Table 17.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MH z) Maximum Bit Rate (bits/s) 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 33 8.2500 515625 40 10.0000 625000 50 12.5000 781250 Table 17.8 Maximum Bit Rates with External Clock Input Pφ (MHz) External Input Clock (MH z) Maximum Bit Rate (bits/s) 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0 33 5.5000 5500000.0 40 6.6667 6666666.7 50 8.3333 8333333.3

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 847 of 1692 REJ09B0393-0100

17.3.9 FIFO Control Register (SCFCR)

SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below.

• Asynchronous mode • Clocked synchronous mode 00: 1 01: 4 10: 8 11: 14 00: 1 01: 2 10: 8 11: 14 7, 6 RTRG[1:0] 00 R/W Note: In clock synchronous mode, to transfer the receive data using DMAC, set the receive trigger number to 1. If set to other than 1, CPU must read the receive data left in SCFRDR.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 848 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 5, 4 TTRG[1:0] 00 R/W Trans mit FIFO Data Trigger Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1. 3 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

2 TFRST 0 R/W Transmit FIFO Data Register Reset

Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.

1 RFRST 0 R/W Receive FIFO Data Register Reset

Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.

0 LOOP 0 R/W Loop-Back Test

Internally connects the transmit output pin (TXD) and receive input pin (RXD) and internally connects the RTS pin and CTS pin and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 849 of 1692 REJ09B0393-0100

17.3.10 FIFO Data Count Register (SCFDR)

SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a power on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 RRRRRRRRRRRRRRRR Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 15 to 13 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 8 T[4:0] 00000 R T4 to T0 bits i ndicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. 7 to 5 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 R[4:0] 00000 R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 850 of 1692 REJ09B0393-0100

17.3.11 Serial Port Register (SCSPTR)

SCSPTR controls input/output and data of pins multiplexed to SCIF function. Bits 3 and 2 can control input/output data of SCK pin. Bits 1 and 0 can input data from RXD pin and output data to TXD pin, so they control break of serial transmitting/receiving. The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'0050 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R R R R R/W R/W R/W R/W Bit: Initial value: R/W: - - - - - - - - - - - - SCKIO SCKDT SPB2IOSPB2DT Bit Bit Name Initial Value R/W Description 15 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 SCKIO 0 R/W SCK Port Input/Output

Indicates input or output of the serial port SCK pin. When the SCK pin is actually used as a port outputting the SCKDT bit value, the CKE[1:0] bits in SCSCR should be cleared to 0. 0: SCKDT bit value not output to SCK pin 1: SCKDT bit value output to SCK pin

2 SCKDT 0 R/W SCK Port Data

Indicates the input/output data of the serial port SCK pin. Input/output is specified by the SCKIO bit. For output, the SCKDT bit value is output to the SCK pin. The SCK pin status is read from the SCKDT bit regardless of the SCKIO bit setting. However, SCK input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 851 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

1 SPB2IO 0 R/W Serial Port Break Input/Output

Indicates input or output of the serial port TXD pin. When the TXD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value not output to TXD pin 1: SPB2DT bit value output to TXD pin

0 SPB2DT 0 R/W Serial Port Break Data

Indicates the input data of the RXD pin and the output data of the TXD pin used as serial ports. Input/output is specified by the SPB2IO bit. When the TXD pin is set to output, the SPB2DT bit value is output to the TXD pin. The RXD pin status is read from the SPB2DT bit regardless of the SPB2IO bit setting. However, RXD input and TXD output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level

17.3.12 Line Status Register (SCLSR)

The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R R R R R R R R/(W) * Bit: Initial value: R/W: Note: Only 0 can be written to clear the flag after 1 is read.*

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 852 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 15 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 ORER 0 R/(W) * Overrun Error

Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally* [Clearing conditions]

• ORER is cleared to 0 when the chip is a power-on reset
• ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred* [Setting condition]
• ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) retains the data before an overrun error has occurred, and the next received data is discarded. When the ORER bit is set to 1, the SCIF cannot continue the next serial reception.

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17.3.13 Serial Extended Mode Register (SCSEMR)

SCSEMR is an 8-bit register that extends the SCIF functions. The transfer rate can be doubled by setting the basic clock in asynchronous mode. Be sure to set this register to H'00 in clocked synchronous mode. SCSEMR is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W ABCS - - - - - - - Bit Bit Name Initial Value R/W Description

7 ABCS 0 R/W Asynchronous Basic Clock Select

Selects the basic clock for 1-bit period in asynchronous mode. Setting of ABCS is valid when the asynchronous mode bit (C/A in SCSMR) = 0. 0: Basic clock with a frequency of 16 times the transfer rate 1: Basic clock with a frequency of 8 times the transfer rate 6 to 0 — All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 854 of 1692 REJ09B0393-0100

17.4 Operation

17.4.1 Overview

For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead of the CPU, and enabling continuous high-speed communication. The transmission format is selected in the serial mode register (SCSMR), as shown in table 17.9. The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 17.10. (1) Asynchronous Mode

• Data length is selectable: 7 or 8 bits
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.  When an internal clock is selected, the SCIF operates using the clock of on-chip baud rate generator.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clocked Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCIF clock source.  When an internal clock is selected, the SCIF operates using the clock of the on-chip baud rate generator, and outputs this clock to external devices as the synchronous clock.  When an external clock is selected, the SCIF operates on the input synchronous clock not using the on-chip baud rate generator.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 855 of 1692 REJ09B0393-0100 Table 17.9 SCSMR Settings and SCIF Communication Formats SCSMR SCIF Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Pari ty Bit Stop Bit Length 0 0 0 0 8 bits Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7 bits Not set 1 bit 1 2 bits 1 0 Set 1 bit Asynchronous 2 bits 1 x x x Clocked synchronous 8 bits Not set None [Legend] x: Don't care Table 17.10 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR SCSCR Bit 7 Bit 1 Bit 0 C/A CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 SCIF does not use the SCK pin Internal Outputs a clock with a frequency 16 times the bit rate 1 0 External Inputs a clock with frequency 16 times the bit rate Asynchronous Setting prohibited 0 x Internal Outputs the serial clock 1 0 External Inputs the serial clock Clocked synchronous Setting prohibited [Legend] x: Don't care

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17.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 17.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. D0 D1 D3 D4 D5 D6D2 0/1 11 (LSB) (MSB) Start bit Idle state (mark state) Stop bit Transmit/receive data Serial data Parity bit 1 bit 1 or 2 bits7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 17.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 857 of 1692 REJ09B0393-0100 (1) Transmit/Receive Formats Table 17.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 17.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits Serial Transmit /Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8-bit data STOP 0 0 1 START 8-bit data STOP STOP 0 1 0 START 8-bit data P STOP 0 1 1 START 8-bit data P STOP STOP 1 0 0 START 7-bit data STOP 1 0 1 START 7-bit data STOP STOP 1 1 0 START 7-bit data P STOP 1 1 1 START 7-bit data P STOP STOP [Legend] START: Start bit STOP: Stop bit P: Parity bit (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE[1:0] in the serial control register (SCSCR). For clock source selection, refer to table 17.10. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The frequency of this output clock is 16 times the desired bit rate.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 860 of 1692 REJ09B0393-0100 In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started.

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• Receiving Serial Data (Asynchronous Mode) Figures 17.6 and 17.7 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR ER, DR, BRK or ORER = 1? Read RDF flag in SCFSR RDF = 1? Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling [1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF flag = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR. [1] [2] [3] Figure 17.6 Sample Flowchart for Receiving Serial Data

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 863 of 1692 REJ09B0393-0100 Error handling Receive error handling ER = 1? BRK = 1? Break handling DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR to 0 End Yes Yes Yes No Overrun error handling ORER = 1? Yes No No No

• Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register (SCFSR).
• When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. Figure 17.7 Sample Flowchart for Receiving Serial Data (cont)

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 864 of 1692 REJ09B0393-0100 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the st op bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK fl ag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing er ror occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when th e RDF or DR flag changes to 1, a receive-FIFO- data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 866 of 1692 REJ09B0393-0100

17.4.3 Operation in Clocked Synchronous Mode

In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 17.9 shows the general format in clocked synchronous serial communication. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 * * LSB MSB Don't careDon't care One unit of transfer data (character or frame) Serial data Serial clock Note: * High except in continuous transfer Figure 17.9 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the serial clock.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 867 of 1692 REJ09B0393-0100 (1) Transmit/Receive Formats The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number. (3) Transmitting and Receiving Data

• SCIF Initialization (Clocked Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 871 of 1692 REJ09B0393-0100

• Receiving Serial Data (Clocked Synchronous Mode) Figures 17.13 and 17.14 show sample flowcharts for receiving serial data. When switching from asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0. Start of reception Read ORER flag in SCLSR ORER = 1? Read RDF flag in SCFSR RDF = 1? Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling [1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. However, the RDF bit is cleared to 0 automatically when an RXI interrupt activates the DMAC to read the data in SCFRDR. [1] [2] [3] Figure 17.13 Sample Flowchart for Receiving Serial Data (1)

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 872 of 1692 REJ09B0393-0100 Error handling Clear ORER flag in SCLSR to 0 End Overrun error handling ORER = 1? Yes No Figure 17.14 Sample Flowchart for Receiving Serial Data (2) In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 875 of 1692 REJ09B0393-0100

17.5 SCIF Interrupts

The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive FIFO data full (RXI), and break (BRI). Table 17.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC or DTC can be activated and data transfer performed by this TXI interrupt request. At DMAC activation, an interrupt request is not sent to the CPU. When an RXI request is enabled by the RIE bit and the RDFE flag or the DR flag in SCFSR is set to 1, an RXI interrupt request is generated. The DMAC or DTC can be activated and data transfer performed by this RXI interrupt request. At DMAC activation, an interrupt request is not sent to the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous mode. When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt without requesting an RXI interrupt. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR. Table 17.12 SCIF Interrupt Sources Interrupt Source BRI Interrupt initiated by break (BRK) or overrun error (ORER) Not possible High ERI Interrupt initiated by receive error (ER) Not possible RXI Interrupt initiated by re ceive FIFO data full (RDF) or data ready (DR) Possible TXI Interrupt initiated by transmit FIFO data empty (TDFE) Possible Low

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17.6 Usage Notes

Note the following when using the SCIF.

17.6.1 SCFTDR Writing and TDFE Flag

The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG[1:0] in the FIFO control register (SCFCR). After the TDFE flag is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE flag clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR).

17.6.2 SCFRDR Reading and RDF Flag

The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG[1:0] in the FIFO control register (SCFCR). After RDF flag is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR).

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17.6.3 Restriction on DMAC and DTC Usage

When the DMAC or DTC writes data to SCFTDR due to a TXI interrupt request, the state of the TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in such a case.

17.6.4 Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate.

17.6.5 Sending a Break Signal

The I/O condition and level of the TXD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, the TXD pin does not work. During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 878 of 1692 REJ09B0393-0100

17.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCIF operates on a base clock with a frequency of 16 times the transfer rate.* In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 17.17. Note: * This is an example when ABCS = 0 in SCSEMR. When ABCS = 1, a frequency of 8 times the bit rate becomes the basic clock, and receive data is sampled at the fourth rising edge of the basic clock. D0 D1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clocks 8 clocks Base clock Receive data (RxD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Figure 17.17 Receive Data Sampling Timing in Asynchronous Mode

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 879 of 1692 REJ09B0393-0100 The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: D − 0.5 N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

17.6.7 FER Flag and PER Flag of Serial Status Register (SCFSR)

The FER flag and PER flag in the serial status register (SCFSR) are status flag that apply to next entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DMAC reads the receive FIFO data register, the flags of framing errors and parity errors will disappear. To check the received data for the states of framing errors and parity errors, only read the receive FIFO register after reading the serial status register.

Section 17 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Jun. 26, 2008 Page 880 of 1692 REJ09B0393-0100

Section 18 Synchronous Serial Communication Unit (SSU) SCISSU0A_000120020900 Rev. 1.00 Jun. 26, 2008 Page 881 of 1692 REJ09B0393-0100 Section 18 Synchronous Serial Communication Unit (SSU) This LSI (SH7286 or SH7285) has an independent synchronous serial communication unit (SSU) channel. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase.

18.1 Features

• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
• Five interrupt sources Transmit end, transmit data register empty, receive data full, overrun error, and conflict error. The data transfer controller (DTC) can be activated by a transmit data register empty request or a receive data full request to transfer data.
• Module standby mode can be set

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 883 of 1692 REJ09B0393-0100

18.2 Input/Output Pins

Table 18.1 shows the SSU pin configuration. Table 18.1 Pin Configuration Symbol I/O Function SSCK I/O SSU clock input/output SSI I/O SSU data input/output SSO I/O SSU data input/output SCS I/O SSU chip select input/output

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 884 of 1692 REJ09B0393-0100

18.3 Register Descriptions

The SSU has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 30, List of Registers. Table 18.2 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size SS control register H SSCRH R/W H'0D H'FFFFB000 8, 16 SS control register L SSCRL R/W H'00 H'FFFFB001 8 SS mode register SSMR R/W H'00 H'FFFFB002 8, 16 SS enable register SSER R/W H'00 H'FFFFB003 8 SS status register SSSR R/W H'04 H'FFFFB004 8, 16 SS control register 2 SSCR2 R/W H'00 H'FFFFB005 8 SS transmit data register 0 SSTDR0 R/W H'00 H'FFFFB006 8, 16 SS transmit data register 1 SSTDR1 R/W H'00 H'FFFFB007 8 SS transmit data register 2 SSTDR2 R/W H'00 H'FFFFB008 8, 16 SS transmit data register 3 SSTDR3 R/W H'00 H'FFFFB009 8 SS receive data register 0 SSRDR0 R H'00 H'FFFFB00A 8, 16 SS receive data register 1 SSRDR1 R H'00 H'FFFFB00B 8 SS receive data register 2 SSRDR2 R H'00 H'FFFFB00C 8, 16 SS receive data register 3 SSRDR3 R H'00 H'FFFFB00D 8

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 885 of 1692 REJ09B0393-0100

18.3.1 SS Control Register H (SSCRH)

SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit: Initial value: R/W: 7654321 0 00001101 R/W R/W R R/W R/W R R/W R/W MSS BIDE - SOL SOLP - CSS[1:0] Bit Bit Name Initial Value R/W Description

7 MSS 0 R/W Master/Slave Device Select

Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected.

6 BIDE 0 R/W Bidirectional Mode Enable

Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 18.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 886 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

4 SOL 0 R/W Serial Data Output Value Select

The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high.

3 SOLP 1 R/W SOL Bit Write Protect

When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1. 2  1 R Reserved This bit is always read as 1. The write value should always be 1. 1, 0 CSS[1:0] 01 R/W SCS Pin Select Select that the SCS pin functions as SCS input or output. 00: Setting prohibited 01: Setting prohibited 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 887 of 1692 REJ09B0393-0100

18.3.2 SS Control Register L (SSCRL)

SSCRL selects operating mode, software reset, and transmit/receive data length. Bit: Initial value: R/W: 7654321 0 00000000 R R/W R/W R R R R/W R/W - SSUMS SRES - - - DATS[1:0] Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved The bit is always read as 0. The write value should always be 0.

6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock

synchronous mode. 0: SSU mode 1: Clock synchronous mode

5 SRES 0 R/W Software Reset

Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 888 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 1, 0 DATS[1:0] 00 R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited

18.3.3 SS Mode Register (SSMR)

SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R R R/W R/W R/W MLS CPOS CPHS - - CKS[2:0] Bit Bit Name Initial Value R/W Description

7 MLS 0 R/W MSB First/LSB First Select

Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first

6 CPOS 0 R/W Clock Polarity Select

Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode

5 CPHS 0 R/W Clock Phase Select (Only for SSU Mode)

Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 889 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description 4, 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 CKS[2:0] 000 R/W Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved 001: Pφ/4 010: Pφ/8 011: Pφ/16 100: Pφ/32 101: Pφ/64 110: Pφ/128 111: Pφ/256

18.3.4 SS Enable Register (SSER)

SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R/W R/W R/W R/W TE RE - - TEIE TIE RIE CEIE Bit Bit Name Initial Value R/W Description

7 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

6 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 890 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

3 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, an SSTEI interrupt request is enabled.

2 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, an SSTXI interrupt request is enabled.

1 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, an SSRXI interrupt request and an SSOEI interrupt request are enabled.

0 CEIE 0 R/W Conflict Error Interrupt Enable

When this bit is set to 1, an SSCEI interrupt request is enabled.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 891 of 1692 REJ09B0393-0100

18.3.5 SS Status Register (SSSR)

SSSR is a status flag register for interrupts. Bit: Initial value: R/W: 7654321 0 00000100 R R/W R R R/W R/W R/W R/W - ORER - - TEND TDRE RDRF CE Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0.

6 ORER 0 R/W Overrun Error

If the next data is received while RDRF = 1 in data transfer mode (TE=RE=1), an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition]

• When one byte of the next serial reception is completed with RDRF = 1 in data transfer mode (TE=RE=1). [Clearing condition]
• When writing 0 after reading ORER = 1 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 892 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

3 TEND 0 R/W Transmit End

[Setting conditions]

• When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 [Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR

2 TDRE 1 R/W Transmit Data Empty

Indicates whether or not SSTDR contains transmit data. [Setting conditions]

• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
• When transmit data is written to SSTDR while the DMAC is activated by an SSTXI.
• When transmit data is written to SSTDR while the DISEL bit in MRB of the DTC is 0 if the DMAC/DTC is activated by an SSTXI interrupt and then DMAC is activated.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 893 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

1 RDRF 0 R/W Receive Data Register Full

Indicates whether or not SSRDR contains receive data. [Setting condition]

• When receive data is transferred from SSTRSR to SSRDR after successful serial data reception [Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
• When transmit data is read into SSRDR while the DISEL bit in MRB of the DTC is 0 if the DMAC/DTC is activated by an SSRXI interrupt and then DTC is activated

0 CE 0 R/W Conflict/Incomplete Error

Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave device), an incomplete error occurs because it is determined that a master device has terminated the transfer. In addition, an incomplete error occurs when the next serial reception starts as RDRF=1 in the state of SSUMS=0 (SSU mode) or MSS=0 (slave device), then the SCS pin is changed to 1 after the RDRF is cleared to 0 while the SSRDR was read before data reception is completed. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting conditions]

• When a low level is input to the SCS pin in master mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in slave mode (the MSS bit in SSCRH is cleared to 0)
• When the SCS pin is changed to 1, the next reception starts as RDRF=1, then after having read the SSRDR before data reception is completed during transfer in slave mode (the MSS bit in SSCRH is cleared to 0) [Clearing condition]
• When writing 0 after reading CE = 1

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 894 of 1692 REJ09B0393-0100

18.3.6 SS Control Register 2 (SSCR2)

SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R R SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS -- Bit Bit Name Initial Value R/W Description

7 SDOS 0 R/W Serial Data Pin Open Drain Select

Selects whether the serial data output pin is used as a TTL or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, see section 18.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: TTL output 1: NMOS open drain output

6 SSCKOS 0 R/W SSCK Pin Open Drain Select

Selects whether the SSCK pin is used as a TTL or an NMOS open drain output. 0: TTL output 1: NMOS open drain output

5 SCSOS 0 R/W SCS Pin Open Drain Select

Selects whether the SCS pin is used as a TTL or an NMOS open drain output. 0: TTL output 1: NMOS open drain output

4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU

and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 895 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description

3 SCSATS 0 R/W Selects the assertion timing of the SCS pin (valid in

SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 × tSUcyc

2 SSODTS 0 R/W Selects t he data output timing of the SSO pin (valid in

SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low 1, 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 896 of 1692 REJ09B0393-0100

18.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)

SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Do not access SSTDR that is not valid. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU and DTC/DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 0 All 0 R/W Serial transmit data Table 18.3 Setting of DATS Bits in SSCRL and Corresponding SSTDR DATS[1:0] Setting 00 01 10 11 (Invalid Setting) SSTDR0 Valid Valid Valid Invalid SSTDR1 Invalid Valid Valid Invalid SSTDR2 Invalid Invalid Valid Invalid SSTDR3 Invalid Invalid Valid Invalid

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 897 of 1692 REJ09B0393-0100

18.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)

SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Do not access SSRDR that is not valid. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRRR Bit Bit Name Initial Value R/W Description 7 to 0 All 0 R Serial receive data Table 18.4 Setting of DATS Bit in SSCRL and Corresponding SSRDR DATS[1:0] Setting 00 01 10 11 (Invalid Setting) SSRDR0 Valid Valid Valid Invalid SSRDR1 Invalid Valid Valid Invalid SSRDR2 Invalid Invalid Valid Invalid SSRDR3 Invalid Invalid Valid Invalid

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 898 of 1692 REJ09B0393-0100

18.3.9 SS Shift Register (SSTRSR)

SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU. Bit: Initial value: R/W: 7654321 0

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 899 of 1692 REJ09B0393-0100

18.4 Operation

18.4.1 Transfer Clock

A transfer clock can be selected from seven internal clocks and an external clock. Before using this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.

18.4.2 Relationship of Clock Phase, Polarity, and Data

The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 18.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB. SSCK (CPOS = 0) (1) When CPHS = 0 (2) When CPHS = 1 SSCK (CPOS = 1) SSI, SSO SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 18.2 Relationship of Clock Phase, Polarity, and Data

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 900 of 1692 REJ09B0393-0100

18.4.3 Relationship between Data Input/Output Pins and Shift Register

The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 18.3 shows the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 18.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 18.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 18.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 18.3 (5) and (6)).

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 901 of 1692 REJ09B0393-0100 SSCK Shift register (SSTRSR) Shift register (SSTRSR) Shift register (SSTRSR) Shift register (SSTRSR) SSO SSI SSCK SSO SSI SSCK SSO SSI SSCK SSO SSI (1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI SSCK Shift register (SSTRSR) SSO SSI (2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 (5) When SSUMS = 1 and MSS = 1 (6) When SSUMS = 1 and MSS = 0 Figure 18.3 Relationship between Data Input/Output Pins and the Shift Register

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 902 of 1692 REJ09B0393-0100

18.4.4 Communication Mo des and Pin Functions

The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. The input/output directions of the pins should be selected in the port I/O registers. The relationship of communication modes and input/output pin functions are shown in tables 18.5 to 18.7. Table 18.5 Communication Modes and Pin States of SSI and SSO Pins Register Setting Pin State Communication Mode SSUMS BIDE MSS TE RE SSI SSO 0 0 0 0 1  Input SSU communication mode 1 0 Output 

1 Output Input

1 0 1 Input  1 0  Output

1 Input Output

0 1 0 0 1  Input SSU (bidirectional) communication mode 1 0  Output 1 0 1  Input 1 0  Output 1 0 0 0 1 Input  Clock synchronous communication mode 1 0  Output 1 0 1 Input  1 0  Output [Legend] : Not used as SSU pin

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 903 of 1692 REJ09B0393-0100 Table 18.6 Communication Mode s and Pin States of SSCK Pin Register Setting Pin State Communication Mode SSUMS MSS SCKS SSCK 0 0 0  SSU communication mode 1 Input 1 0 

1 Output

1 0 0  Clock synchronous communication mode 1 Input 1 0  [Legend] : Not used as SSU pin Table 18.7 Communication Modes and Pin States of SCS Pin Register Setting Pin State Communication Mode SSUMS MSS CSS1 CSS0 SCS 0 0 x x Input SSU communication mode 1 0 0  0 1  1 0 Automatic input/output 1 1 Output Clock synchronous communication mode 1 x x x  [Legend] x: Don't care : Not used as SSU pin

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 904 of 1692 REJ09B0393-0100

18.4.5 SSU Mode

In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 18.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 905 of 1692 REJ09B0393-0100 Start setting initial values [1] [2] [3] [4] End Set PFC for external pins to be used (SSCK, SSI, SSO, and SCS) Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0 Specify MSS, BIDE, SOL, CSS1, and CSS0 bits in SSCRH Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify bits SDOS, SSCKOS, SCSOS, TENDSTS, STSATS, and SSODTS in SSCR2 Clear TE and RE bits in SSER to 0 [1] Make appropriate settings in the PFC for the external pins to be used. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [5] Specify open-drain output for the SSO, SSI, SSCK, and SCS pins. Specify timing of TEND bit setting, SCS pin assertion, and data output on the SSO pin. [6] Enables/disables interrupt requests to the CPU. [5] Specify bits TE, RE, TEIE, TIE, RIE, and CEIE in SSER simultaneously[6] Figure 18.4 Example of Initial Settings in SSU Mode

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 906 of 1692 REJ09B0393-0100 (2) Data Transmission Figure 18.5 shows an example of transmission operation, and figure 18.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0 before transmission.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 907 of 1692 REJ09B0393-0100 SCS SSCK (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 (3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 to to to to to to to toBit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSO TDRE TEND LSI operation User operation LSI operation User operation LSI operation User operation TXI interrupt generated TEI interrupt generated TEI interrupt generated TXI interrupt generated Data written to SSTDR0 Data written to SSTDR0 and SSTDR1 Data written to SSTDR0 SSTDR1 SCS SSCK TDRE TEND SSO (LSB first) SSO (MSB first) SSO (LSB first) SSO (MSB first) SSTDR0 SSTDR0 SSTDR1 SCS SSCK TDRE TEND SSTDR0 SSTDR3 SSTDR1 SSTDR2 SSTDR2 SSTDR1 SSTDR 3 SSTDR0 1 frame 1 frame 1 frame SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) 1 frame TXI interrupt generated TEI interrupt generated Data written to SSTDR0 to SSTDR3 TXI interrupt generated TEI interrupt generated Figure 18.5 Example of Transmission Operation (SSU Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 908 of 1692 REJ09B0393-0100 Yes Start [1] [2] [3] [1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Note: Hatching boxes represent SSU internal operations. Initial setting Read TDRE in SSSR TDRE = 1? Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission Consecutive data transmission? Read TEND in SSSR TEND = 1? Clear TEND to 0 Clear TE in SSER to 0 End transmission Yes No Confirm that TEND is cleared to 0 One bit time quantum elapsed?[4] Figure 18.6 Flowchart Example of Data Transmission (SSU Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 909 of 1692 REJ09B0393-0100 (3) Data Reception Figure 18.7 shows an example of reception operation, and figure 18.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. In continuous reception as the slave device in SSU mode, be sure to read SSRDR before reception of the next frame starts. If reception of a next frame starts before clearing RDRF to 0, then read SSRDR before completing the reception of the next frame, CE in SSSR will be set to 1 at the end of the next frame. If reception of the next frame starts before RDRF is cleared to 0 then SSRDR will not be read until the end of completion, neither CE nor ORER in SSSR will be set but the received data will be discarded.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 910 of 1692 REJ09B0393-0100 SCS SSCK (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 (3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SSI RDRF SSRDR1 SCS SSCK RDRF SSRDR0 SSRDR0 SSRDR1 SCS SSCK RDRF SSRDR0 SSRDR3 SSRDR1 SSRDR2 SSRDR2 SSRDR1 SSRDR3 SSRDR0 1 frame 1 frame 1 frame 1 frame Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LSI operation Dummy-read SSRDR0 Dummy-readSSRDR0 Read SSRDR0User operation LSI operation User operation LSI operation User operation SSRDR0 (LSB first transmission) SSRDR0 (MSB first transmission) RXI interrupt generated RXI interrupt generated RXI interrupt generated Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSI (LSB first) SSI (MSB first) Bit 0 to to to to to to to toBit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit SSI (LSB first) SSI (MSB first) Dummy-readSSRDR0 RXI interrupt generated Figure 18.7 Example of Reception Operation (SSU Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 911 of 1692 REJ09B0393-0100 Yes [1] [2] [3] [4] [5] [6] [1] Initial setting: Specify the receive data format. [2] Start reception: When SSRDR is dummy-read with RE = 1, reception is started. [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To continue single reception: When continuing single reception, wait for time of t SUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR. The next single reception starts after reading receive data in SSRDR. [5] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No Yes Yes No Start Initial setting Dummy-read SSRDR Read SSSR RDRF = 1? ORER = 1? Consecutive data reception? Read received data in SSRDR RDRF automatically cleared RE = 0 Read receive data in SSRDR End reception Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. No Figure 18.8 Flowchart Example of Data Reception (SSU Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 912 of 1692 REJ09B0393-0100 (4) Data Transmission/Reception Figure 18.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bit to 1. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 913 of 1692 REJ09B0393-0100 Yes Start Initial setting[1] [2] [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] [5] [3] Read TDRE in SSSR. TDRE = 1? Yes Yes Yes Yes No No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR RDRF = 1? ORER = 1? TEND = 1? Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Yes One-bit interval elapsed? No Read the TEND bit in SSSR Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Error processing End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 18.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 914 of 1692 REJ09B0393-0100

18.4.6 SCS Pin Control and Conflict Error

When bits CSS1 and CSS0 in SSCRH are set to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin becomes an input pin (Hi-Z) before the serial transfer is started and after the serial transfer is complete. Because of this, the SSU performs conflict error detection during these periods. If a low level signal is input to the SCS pin during these periods, it is detected as a conflict error. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception cannot be restarted. Clear the CE bit to 0 before restarting the transmission or reception. CE Data written to SSTDR Conflict error detection period Worst time for internal clocking of SCS MSS Internal signal for transfer enable SCS output External input to SCS Internally-clocked SCS (Hi-Z) Figure 18.10 Conflict Error Detection Timing (Before Transfer)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 915 of 1692 REJ09B0393-0100 Pφ SCS MSS CE (Hi-Z) Transfer end Conflict error detection period Internal signal for transfer enable Figure 18.11 Conflict Error Detection Timing (After Transfer End)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 916 of 1692 REJ09B0393-0100

18.4.7 Clock Synchronous Communication Mode

In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 18.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values [1] [2] [3] [4] Set PFC for external pins to be used (SSCK, SSI, SSO, and SCS) Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0 Specify MSS in SSCRH Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Clear TE and RE bits in SSER to 0 [1] Make appropriate settings in the PFC for the external pins to be used. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection. [5] Specify open-drain output for the SSO, SSI, SSCK, and SCS pins. Specify timing of TEND bit setting, SCS pin assertion, and data output on the SSO pin. [6] Enables/disables interrupt requests to the CPU. End Specify bits SDOS, SSCKOS, SCSOS, TENDSTS, STSATS, and SSODTS in SSCR2 [5] Specify bits TE, RE, TEIE, TIE, RIE, and CEIE in SSER simultaneously[6] Figure 18.12 Example of Initial Settings in Clock Synchronous Communication Mode

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 918 of 1692 REJ09B0393-0100 Yes Start [1] [2] [3] [1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Note: Hatched boxes represent SSU internal operations. Initial setting Read TDRE in SSSR TDRE = 1? Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission Consecutive data transmission? Read TEND in SSSR TEND = 1? Clear TE in SSER to 0 End transmission Yes No Confirm that TEND is cleared to 0 One-bit intreval elapsed? Clear TEND to 0 [4] Figure 18.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 920 of 1692 REJ09B0393-0100 Yes [1] [2] [3] [4] [5] [1] Initial setting: Specify the receive data format. [2] Start reception: When the RE bit is set to 1, reception is started. [3], [5] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No Yes Yes No Start Initial setting RE = 1 (reception started) Read SSSR RDRF = 1? ORER = 1? Consecutive data reception? Read received data in SSRDR RDRF automatically cleared RE = 0 Read receive data in SSRDR End reception Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. No Figure 18.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 921 of 1692 REJ09B0393-0100 (4) Data Transmission/Reception Figure 18.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bits to 1. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 922 of 1692 REJ09B0393-0100 Yes Start Initial setting[1] [2] [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] [5] [3] Read TDRE in SSSR. TDRE = 1? Yes Yes Yes No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR RDRF = 1? ORER = 1? Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Error processing End transmission/reception Note: Hatching boxes represent SSU internal operations. Yes TEND = 1? No Yes One-bit interval elapsed? No Read the TEND bit in SSSR No Figure 18.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)

Section 18 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Jun. 26, 2008 Page 923 of 1692 REJ09B0393-0100

18.5 SSU Interrupt Sources and DTC or DMAC

The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, and a transmit data register empty can activate the DTC or DMAC for data transfer. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 18.8 lists the interrupt sources. When an interrupt condition shown in table 18.8 is satisfied, an interrupt is requested. Clear the interrupt source by CPU, DTC, or DMAC data transfer. Table 18.8 SSU Interrupt Sources Abbreviation Interrupt Source Symbol Interrupt Condition DTC or DMAC Activation SSERI Overrun error SSOEI (RIE = 1) • (ORER = 1)  Conflict error SSCEI (CEIE = 1) • (CE = 1)  SSRXI Receive data register full SSRXI (RIE = 1) • (RDRF = 1) Yes SSTXI Transmit data regist er empty SSTXI (TIE = 1) • (TDRE = 1) Yes Transmit end SSTEI (TEIE = 1) • (TEND = 1) 

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