SH7124

SH7125 RENESAS | Alldatasheet

Document overview

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• PDF pages: 782

Technical content

Datasheet sections

• 1.1 Features of SH7125 and SH7124
• 1.2 Block Diagram
• 1.3 Pin Assignments
• 1.4 Pin Functions
• 2.1 Features
• 2.2 Register Configuration
• 2.2.1 General Registers (Rn)
• 2.2.2 Control Registers
• 2.2.3 System Registers
• 2.2.4 Initial Values of Registers
• 2.3 Data Formats
• 2.3.1 Register Data Format
• 2.3.2 Memory Data Formats
• 2.3.3 Immediate Data Formats
• 2.4.1 RISC Type
• 2.4.2 Addressing Modes
• 2.4.3 Instruction Formats
• 2.5 Instruction Set
• 2.5.1 Instruction Set by Type
• 2.5.2 Data Transfer Instructions
• 2.5.3 Arithmetic Operation Instructions
• 2.5.4 Logic Operation Instructions
• 2.5.5 Shift Instructions
• 2.5.6 Branch Instructions
• 2.5.7 System Control Instructions
• 2.6 Processing States
• 3.1 Selection of Operating Modes
• 3.2 Input/Output Pins
• 3.3 Operating Modes
• 3.3.1 Mode 3 (Single Chip Mode)

Revision Date: Sep. 27, 2007

32 Hardware Manual

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family SH7125 R5F7125 SH7124 R5F7124 Rev.3.00 REJ09B0243-0300 SH7125 Group, SH7124 Group

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Rev. 3.00 Sep. 27, 2007 Page iii of xx 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev. 3.00 Sep. 27, 2007 Page iv of xx General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.

Rev. 3.00 Sep. 27, 2007 Page v of xx Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules

• CPU and System-Control Modules  On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index

Rev. 3.00 Sep. 27, 2007 Page vi of xx Preface The SH7125 Group and SH7124 Group RISC (Reduced Instruction Set Computer) microcomputer include a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH7125 Group and SH7124 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7125 Group and SH7124 Group to the target users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual:

• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual.
• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/

Rev. 3.00 Sep. 27, 2007 Page vii of xx SH7125 Group and SH7124 Group manuals: Document Title Document No. SH7125 Group, SH7124 Group Hardware Manual This manual SH-1/SH-2/SH-DSP Software Manual REJ09B0171 User's manuals for development tools: Document Title Document No. SuperH TM RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User's Manual REJ10B0152 SuperH TM RISC engine High-performance Embedded Workshop 3 User's Manual REJ10B0025 SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial REJ10B0023 Application note: Document Title Document No. SuperH RISC engine C/C++ Compiler Package Application Note REJ05B0463 All trademarks and registered trademarks are the property of their respective owners.

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6.3.4 Interrupt Priority Registers A to F and H to M

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9.3.10 Timer A/D Converter Start Request Cycle Set Registers

9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers

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9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to

9.7.20 Output Level in Complementary PWM Mode and

9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of

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17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and

17.8.1 Specifications of the Standard Serial Communications Interface

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Rev. 3.00 Sep. 27, 2007 Page 1 of 758 REJ09B0243-0300 Section 1 Overview

1.1 Features of SH7125 and SH7124

This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a ROM, a RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. The version of the on-chip ROM is F-ZTAT TM (Flexible Zero Turn Around Time)* that includes flash memory. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board. The features of this LSI are listed in table 1.1. Note: * F-ZTAT TM is a trademark of Renesas Technology Corp.

Rev. 3.00 Sep. 27, 2007 Page 2 of 758 REJ09B0243-0300 Table 1.1 Features Items Specification CPU • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture

• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles
• C language-oriented 62 basic instructions Note: Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. For details, see section 5.8.4, Notes on Slot Illegal Instruction Exception Handling. Operating modes • Operating modes  Single chip mode
• Operating states  Program execution state  Exception handling state
• Power-down modes  Sleep mode  Software standby mode  Module standby mode User break controller (UBC)
• Addresses, data values, type of access, and data size can all be set as break conditions
• Supports a sequential break function
• Two break channels On-chip ROM • 128 kbytes (SH71253, SH71243)
• 64 kbytes (SH71252, SH71242)
• 32 kbytes (SH71241) On-chip RAM • 8 kbytes

Rev. 3.00 Sep. 27, 2007 Page 3 of 758 REJ09B0243-0300 Items Specification Interrupt controller (INTC)

• External interrupt pins  SH7125: Five pins (NMI and IRQ3 to IRQ0)  SH7124: Four pins (NMI and IRQ3 to IRQ1)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source User debugging interface (H-UDI)
• E10A emulator support Clock pulse generator (CPG)
• Clock mode: Input clock can be selected from external input or crystal resonator
• Four types of clocks generated:  CPU clock: Maximum 50 MHz  Bus clock: Maximum 40 MHz  Peripheral clock: Maximum 40 MHz  MTU2 clock: Maximum 40 MHz Watchdog timer (WDT)
• On-chip one-channel watchdog timer
• Interrupt generation is supported.

Rev. 3.00 Sep. 27, 2007 Page 4 of 758 REJ09B0243-0300 Items Specification Multi-function timer pulse unit 2 (MTU2)

• Maximum 16 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers (SH7125)
• Maximum 12 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers (SH7124)
• 21 output compare and input capture registers
• A total of 21 independent comparators
• Selection of eight counter input clocks
• Input capture function
• Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes
• Synchronization of multiple counters
• Complementary PWM output mode  Non-overlapping waveforms output for 6-phase inverter control  Automatic dead time setting  0% to 100% PWM duty cycle specifiable  Output suppression  A/D conversion delaying function  Dead time compensation  Interrupt skipping at crest or trough
• Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty cycle
• Phase counting mode Two-phase encoder pulse counting available Port output enable (POE)
• High-impedance control of waveform output pins and channel 0 pins in MTU2 Compare match timer (CMT)
• 16-bit counters
• Compare match interrupts can be generated
• Two channels Serial communication interface (SCI)
• Clock synchronous or asynchronous mode
• Three channels

Rev. 3.00 Sep. 27, 2007 Page 5 of 758 REJ09B0243-0300 Items Specification A/D converter (ADC) • 10 bits × 8 channels

• Conversion request by external triggers or MTU2
• Two sample-and-hold function units (two channels can be sampled simultaneously) I/O ports • 37 general input/output pins and eight general input pins (SH7125)
• 23 general input/output pins and eight general input pins (SH7124)
• Input or output can be selected for each bit
• LQFP-64 (0.5 pitch) (SH7125)
• LQFP-48 (0.65 pitch) (SH7124)
• VQFN-64 (0.4 pitch) (SH7125 and SH7124)
• VQFN-52 (0.4 pitch) (SH7124) Power supply voltage • Vcc: 4.0 to 5.5 V
• AVcc: 4.0 to 5.5 V

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1.2 Block Diagram

The block diagram of this LSI is shown in figure 1.1. [Legend] ROM: On-chip ROM RAM: On-chip RAM UBC: User break controller H-UDI: User debugging interface INTC: Interrupt controller CPG: Clock pulse generator WDT: Watchdog timer CPU: Central processing unit PFC: Pin function controller MTU2: Multi-function timer pulse unit 2 POE: Port output enable SCI: Serial communication interface CMT: Compare match timer ADC: A/D converter I/O port (PFC) Power- down mode control Peripheral bus (Pφ) I bus (Bφ) L bus (Iφ) Peripheral bus controller SH2 CPU UBC INTC WDT CPGH-UDI MTU2 POESCI CMT ADC Internal bus controller RAMROM Figure 1.1 Block Diagram

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1.3 Pin Assignments

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 V CL PA1/POE1/TXD0 VCC PA2/IRQ0/SCK0 V SS PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA5/IRQ3/SCK1 PA6/TCLKA PA7/TCLKB/SCK2/TCK PA8/TCLKC/RXD2/TDI PA9/TCLKD/TXD2/TDO/POE PA10/RXD0 VSS PA11/TXD0/ADTRG VCC PA12/SCK0 PA13/SCK1 PA14/RXD1 PA15/TXD1 PE0/TIOC0A 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D VCC PE9/TIOC3B VSS PE10/TIOC3C VCL PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A/SCK1 PE5/TIOC1B/TXD1 PE4/TIOC1A/RXD1 PE3/TIOC0D/SCK0 PE2/TIOC0C/TXD0 PE1/TIOC0B/RXD0 QFP-64 LQFP-64 (Top view) Pins for the system development tool. When these pins are used for an on-chip debugger, they are not available. Figure 1.2 (1) Pin Assignments of SH7125

Rev. 3.00 Sep. 27, 2007 Page 8 of 758 REJ09B0243-0300 PB3/IRQ1/POE1/TIC5V PB2/IRQ0/POE0 PB1/TIC5W AVSS PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 AV CC PB16/POE3 PB15/TIOC4D/IRQOUT PE14/TIOC4C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 V CL PA1/POE1/TXD0 VCC PA2/IRQ0/SCK0 V SS PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA5/IRQ3/SCK1 PA6/TCLKA PA7/TCLKB/SCK2/TCK PA8/TCLKC/RXD2/TDI PA9/TCLKD/TXD2/TDO/POE PA10/RXD0 VSS PA11/TXD0/ADTRG VCC PA12/SCK0 PA13/SCK1 PA14/RXD1 PA15/TXD1 PE0/TIOC0A 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D VCC PE9/TIOC3B VSS PE10/TIOC3C VCL PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A/SCK1 PE5/TIOC1B/TXD1 PE4/TIOC1A/RXD1 PE3/TIOC0D/SCK0 PE2/TIOC0C/TXD0 PE1/TIOC0B/RXD0 VQFN-64 (Top view) Figure 1.2 (2) Pin Assignments of SH7125

Rev. 3.00 Sep. 27, 2007 Page 9 of 758 REJ09B0243-0300 PB3/IRQ1/POE1/TIC5V PB1/TIC5W AVSS PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 AV CC 48 36 35 34 33 32 31 30 29 2827 26 PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKA K NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 V CL PA1/POE1/TXD0 PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA6/TCLKA PA7/TCLKB/SCK2/TCK V SS PA8/TCLKC/RXD2/TDI V CC PA9/TCLKD/TXD2/TDO/POE8 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 123456789 1 0 1 1 1 2 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES VCC PE12/TIOC4A VSS PE11/TIOC3D VCL PE9/TIOC3B PE10/TIOC3C PE8/TIOC3A PE3/TIOC0D/SCK0 LQFP-48 (Top view) Pins for the system development tool. When these pins are used for an on-chip debugger, they are not available. Figure 1.3 (1) Pin Assignments of SH7124

Rev. 3.00 Sep. 27, 2007 Page 10 of 758 REJ09B0243-0300 PB3/IRQ1/POE1/TIC5V PB1/TIC5W AVss PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 AVcc NC 39 38 37 36 35 34 33 32 31 30 29 28 27 PB5/IRQ3/TIC5U VSS PLLVSS MD1 FWE/ASEBRK/ASEBRKA K NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/TXD0 V CL PA1/POE1/TXD0 PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA6/TCLKA PA7/TCLKB/SCK2/TCK V SS VSS PA8/TCLKC/RXD2/TDI V CC PA9/TCLKD/TXD2/TDO/POE8 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 123456789 1 0 1 1 1 2 1 3 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES VCC PE12/TIOC4A VSS PE11/TIOC3D VCL PE9/TIOC3B PE10/TIOC3C PE8/TIOC3A PE3/TIOC0D/SCK0 NC VQFN-52 (Top view) Figure 1.3 (2) Pin Assignments of SH7124

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1.4 Pin Functions

Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Classification Symbol I/O Name Function Vcc I Power supply Power supply pin Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground pin Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. Power supply VCL O Power supply for internal power- down External capacitance pins for internal power-down power supply Connect these pins to Vss via a 0.1 to 0.47 µF capacitor (placed close to the pins). PLLVss I PLL ground Ground pin for the on-chip PLL oscillator EXTAL I External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. Clock XTAL O Crystal Connected to a crystal resonator. MD1 I Mode set Sets the operating mode. Do not change values on this pin during operation. Operating mode control FWE I Flash memory write enable Pin for flash memory Flash memory can be protected against programming or erasure through this pin.

Rev. 3.00 Sep. 27, 2007 Page 12 of 758 REJ09B0243-0300 Classification Symbol I/O Name Function RES I Power-on reset When low, this LSI enters the power- on reset state. MRES I Manual reset When low, this LSI enters the manual reset state. System control WDTOVF O Watchdog timer overflow Output signal for the watchdog timer overflow If this pin needs to be pulled down, use the resistor larger than 1 MΩ to pull this pin down. NMI I Non-maskable interrupt Non-maskable interrupt request pin Fix to high or low level when not in use. Interrupts IRQ3 to IRQ0 (SH7125) IRQ3 to IRQ1 (SH7124) I Interrupt requests 3 to 0 Maskable interrupt request pins Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. IRQOUT O Interrupt request output Shows that an interrupt cause has occurred. The interrupt cause can be recognized even in the bus release state. TCLKA, TCLKB, TCLKC, TCLKD I MTU2 timer clock input External clock input pins for the timer TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins TIOC1A, TIOC1B (only in SH7125) I/O MTU2 input capture/output compare (channel 1) The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins Multi function timer- pulse unit 2 (MTU2) TIOC2A, TIOC2B (only in SH7125) I/O MTU2 input capture/output compare (channel 2) The TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins

Rev. 3.00 Sep. 27, 2007 Page 13 of 758 REJ09B0243-0300 Classification Symbol I/O Name Function TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O MTU2 input capture/output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O MTU2 input capture/output compare (channel 4) The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins Multi function timer- pulse unit 2 (MTU2) TIC5U, TIC5V, TIC5W I MTU2 input capture (channel 5) The TGRU_5, TGRV_5, and TGRW_5 input capture input pins Port output enable (POE) POE8, POE3, POE1, POE0 (SH7125) POE8, POE1, POE0 (SH7124) I Port output enable Request signal input to place the waveform output pins and channel 0 pins of MTU2 in high impedance state. In the SH7125, while POE3 function is selected in the PFC, the pin is pulled up inside this LSI if no signals are input to them. TXD2 to TXD0 O Transmit data Transmit data output pins RXD2 to RXD0 I Receive data Receive data input pins Serial communication interface (SCI) SCK2 to SCK0 (SH7125) SCK2, SCK0 (SH7124) I/O Serial clock Clock input/output pins AN7 to AN0 I Analog input pins Analog input pins ADTRG (only in SH7125) I A/D conversion trigger input External trigger input pin for starting A/D conversion A/D converter (ADC) AVcc I Analog power supply Power supply pin for the A/D converter Connect all AVcc pins to the system power supply (Vcc) when the A/D converter is not used. The A/D converter does not work if any pin is open.

Rev. 3.00 Sep. 27, 2007 Page 14 of 758 REJ09B0243-0300 Classification Symbol I/O Name Function A/D converter AVss I Analog ground Ground pin for the A/D converter Connect it to the system ground (0 V). Connect all AVss pins to the system ground (0 V) correctly. The A/D converter does not work if any pin is open. PA15 to PA0 (SH7125) I/O General port 16-bit input/output port pins PA9 to PA6, PA4, PA3, PA1, PA0 (SH7124) 8-bit input/output port pins PB16, PB5, PB3 to PB1 (SH7125) I/O General port 5-bit input/output port pins PB5, PB3, PB1 (SH7124) 3-bit input/output port pins PE15 to PE0 (SH7125) I/O General port 16-bit input/output port pins PE15 to PE8, PE3 to PE0 (SH7124) 12-bit input/output port pins I/O ports PF7 to PF0 I General port 8-bit input port pins TCK I Test clock Test-clock input pin TMS I Test mode select Inputs the test-mode select signal. TDI I Test data input Serial input pin for instructions and data TDO O Test data output Serial output pin for instructions and data User debugging interface (H-UDI) TRST I Test reset Initialization-signal input pin

Rev. 3.00 Sep. 27, 2007 Page 15 of 758 REJ09B0243-0300 Classification Symbol I/O Name Function ASEMD0 I ASE mode Sets the ASE mode. When a low level is input, this LSI enters ASE mode. When a high level is input, this LSI enters the normal mode. The emulator functions are available in ASE mode. When no signal is input, this pin is pulled up inside this LSI. ASEBRK I Break request E10A emulator break input pin E10A interface ASEBRKAK O Break mode acknowledge Indicates that the E10A emulator has entered its break mode. Note: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down through a resistor of 1 MΩ or larger.

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CPUS200C_000020020700 Rev. 3.00 Sep. 27, 2007 Page 17 of 758 REJ09B0243-0300 Section 2 CPU

2.1 Features

• General registers: 32-bit register × 16
• Basic instructions: 62
• Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR) PC relative with displacement (@disp:8, PC) PC relative (disp:8/disp:12/Rn) Immediate (#imm:8)

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2.2 Register Configuration

There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). 31 0 R0*1 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)* 31 9 8 7 6 5 4 3 2 1 0 M GBR VBR QI 3I 2I 1 I 0 S T 31 0 MACH 31 0 PR 31 0 PC MACL Notes: 1. R0 can be used as an index register in index register indirect or index GBR indirect addressing mode. For some instructions, only R0 is used as the source or destination register. 2. R15 is used as a hardware stack pointer during exception handling. General register (Rn) Status register (SR) Global base register (GBR) Vector base register (VBR) Multiply and accumulate register (MAC) Procedure register (PR) Program counter (PC) Figure 2.1 CPU Internal Register Configuration

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2.2.1 General Registers (Rn)

There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the status register (SR) and program counter (PC) values.

2.2.2 Control Registers

There are three 32-bit control registers, designated status register (SR), global base register (GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers. VBR is used as a base address of the exception handling (including interrupts) vector table.

• Status register (SR) Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR 000000- -111100- - RRRRRR R / W R / W R / W R / W R / W R / W RR R / W R / W Bit Bit name Default Read/ Write

Description

31 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W Interrupt Mask 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Rev. 3.00 Sep. 27, 2007 Page 20 of 758 REJ09B0243-0300 Bit Bit name Default Read/ Write

1 S Undefined R/W S Bit

Used by the multiply and accumulate instruction.

0 T Undefined R/W T Bit

Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL

• Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations.
• Vector-base register (VBR) This register indicates the base address of the exception handling vector table.

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2.2.3 System Registers

There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC).

• Multiply and accumulate registers (MACH and MACL) This register stores the results of multiplication and multiply-and-accumulate operation.
• Procedure register (PR) This register stores the return-destination address from subroutine procedures.
• Program counter (PC) The PC indicates the point which is four bytes (two instructions) after the current execution instruction.

2.2.4 Initial Values of Registers

Table 2.1 lists the initial values of registers after a reset. Table 2.1 Initial Values of Registers Type of register Register Default General register R0 to R14 Undefined R15 (SP) SP value set in the exception handling vector table Control register SR I3 to I0: 1111 (H'F) Reserved bits: 0 Other bits: Undefined GBR Undefined VBR H'00000000 System register MACH, MACL, PR Undefined PC PC value set in the exception handling vector table

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2.3 Data Formats

2.3.1 Register Data Format

The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. Longword 31 0 Figure 2.2 Register Data Format

2.3.2 Memory Data Formats

Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Byte Byte Byte Byte Word Word Longword 31 23 15 7 Address m + 1 Address 2n Address 4n Address m Address m + 3 Address m + 2 Figure 2.3 Memory Data Format

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2.3.3 Immediate Data Formats

Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero- extended to longword and then calculated. Thus, if the immediate data is used for the AND instruction, the upper 24 bits in the destination register are always cleared. The immediate data of word or longword is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed by the MOV immediate data instruction in PC relative addressing mode with displacement.

2.4 Features of Instructions

2.4.1 RISC Type

The instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one cycle. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Byte or word data in memory is sign-extended to longword and then calculated. Immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword size for logical operations. Table 2.2 Word Data Sign Extension CPU in this LSI Description Example of Other CPUs MOV.W @(disp,PC),R1 ADD R1,R0 .DATA.W H'1234 Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. ADD.W #H'1234,R0 Note: * Immediate data is accessed by @(disp,PC).

Rev. 3.00 Sep. 27, 2007 Page 24 of 758 REJ09B0243-0300 Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. The conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. Table 2.3 Delayed Branch Instructions CPU in this LSI Description Example of Other CPUs BRA TRGET ADD R1,R0 ADD is executed before branch to TRGET. ADD.W R1,R0 BRA TRGET Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and- accumulate operation are each executed in two to four cycles. T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Table 2.4 T Bit CPU in this LSI Description Example of Other CPUs CMP/GE R1,R0 When R0 ≥ R1, the T bit is set. CMP.W R1,R0 BT TRGET0 When R0 ≥ R1, a branch is made to TRGET0. BGE TRGET0 BF TRGET1 When R0 < R1, a branch is made to TRGET1. BLT TRGET1 ADD # 1,R0 The T bit is not changed by ADD. SUB.W #1,R0 CMP/EQ #0,R0 When R0 = 0, the T bit is set. BEQ TRGET BT TRGET A branch is made when R0 = 0. Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword immediate data is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed with the MOV immediate data instruction using PC relative addressing mode with displacement.

Rev. 3.00 Sep. 27, 2007 Page 25 of 758 REJ09B0243-0300 Table 2.5 Access to Immediate Data Type This LSI's CPU Example of Other CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 .DATA.W H'1234 MOV.W #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 .DATA.L H'12345678 MOV.L #H'12345678,R0 Note: * Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute address, place the absolute address value in a table in memory beforehand. The absolute address value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register indirect addressing mode. Table 2.6 Access to Absolute Address Type CPU in this LSI Example of Other CPUs Absolute address MOV.L @(disp,PC),R1 MOV.B @R1,R0 .DATA.L H'12345678 MOV.B @H'12345678,R0 Note: * Immediate data is referenced by @(disp,PC). 16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indirect addressing mode.

Rev. 3.00 Sep. 27, 2007 Page 26 of 758 REJ09B0243-0300 Table 2.7 Access with Displacement Type CPU in this LSI Example of Other CPUs 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 .DATA.W H'1234 MOV.W @(H'1234,R1),R2 Note: * Immediate data is referenced by @(disp,PC).

2.4.2 Addressing Modes

Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn. (Operand is register Rn contents.) Register indirect @Rn Effective address is register Rn contents. Rn Rn Rn Register indirect with post-increment @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn 1/2/4 Rn + 1/2/4 Rn After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Register indirect with pre-decrement @–Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 Rn - 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation)

Rev. 3.00 Sep. 27, 2007 Page 27 of 758 REJ09B0243-0300 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register indirect with displacement @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. 1/2/4 disp (zero-extended) Rn + disp × 1/2/4+ Rn Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Index register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn Rn + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR 1/2/4 disp (zero-extended) GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × Longword: GBR + disp × 4 Index GBR indirect @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR GBR + R0 GBR + R0

Rev. 3.00 Sep. 27, 2007 Page 28 of 758 REJ09B0243-0300 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative with displacement @(disp:8, PC) Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC PC + disp × 2 or PC& H'FFFFFFFC + disp × 4 H'FFFFFFFC disp (zero-extended) *With longword operand Word: PC + disp × 2 Longword: PC&H'FFFFFFFC + disp × 4 PC relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) PC + disp × 2 PC + disp × 2 disp:12 Effective address is PC with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) PC + disp × 2 PC + disp × 2

Rev. 3.00 Sep. 27, 2007 Page 29 of 758 REJ09B0243-0300 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative Rn Effective address is sum of PC and Rn. PC PC + Rn Rn PC + Rn Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.

2.4.3 Instruction Formats

This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement

Rev. 3.00 Sep. 27, 2007 Page 30 of 758 REJ09B0243-0300 Table 2.9 Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0   NOP  nnnn: register direct MOVT Rn Control register or system register nnnn: register direct STS MACH,Rn n type xxxx nnnn xxxx xxxx 15 0 Control register or system register nnnn: pre- decrement register indirect STC.L SR,@-Rn mmmm: register direct Control register or system register LDC Rm,SR mmmm: post- increment register indirect Control register or system register LDC.L @Rm+,SR mmmm: register indirect  JMP @Rm m type xxxx mmmm xxxx xxxx 15 0 PC relative using Rm  BRAF Rm

Rev. 3.00 Sep. 27, 2007 Page 31 of 758 REJ09B0243-0300 Instruction Format Source Operand Destination Operand Sample Instruction mmmm: register direct nnnn: register direct ADD Rm,Rn mmmm: register direct nnnn: register indirect MOV.L Rm,@Rn mmmm: post- increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register indirect (multiply- and-accumulate operation) MACH, MACL MAC.W @Rm+,@Rn+ mmmm: post- increment register indirect nnnn: register direct MOV.L @Rm+,Rn mmmm: register direct nnnn: pre- decrement register indirect MOV.L Rm,@-Rn nm type xxxx nnnn mmmm xxxx 15 0 mmmm: register direct nnnn: index register indirect MOV.L Rm,@(R0,Rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 nd4 type xxxx xxxx nnnn dddd 15 0 R0 (register direct) nnnndddd: register indirect with displacement MOV.B R0,@(disp,Rn) mmmm: register direct nnnndddd: register indirect with displacement MOV.L Rm,@(disp,Rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmmdddd: register indirect with displacement nnnn: register direct MOV.L @(disp,Rm),Rn

Rev. 3.00 Sep. 27, 2007 Page 32 of 758 REJ09B0243-0300 Instruction Format Source Operand Destination Operand Sample Instruction dddddddd: GBR indirect with displacement R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (register direct) MOVA @(disp,PC),R0 d type xxxx xxxx dddd dddd 15 0  dddddddd: PC relative BF label d12 type xxxx dddd dddd dddd 15 0  dddddddddddd: PC relative BRA label (label=disp+PC) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd: PC relative with displacement nnnn: register direct MOV.L @(disp,PC),Rn iiiiiiii: immediate Index GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: immediate R0 (register direct) AND #imm,R0 i type xxxx xxxx iiii iiii 15 0 iiiiiiii: immediate  TRAPA #imm ni type xxxx nnnn iiii iiii 15 0 iiiiiiii: immediate nnnn: register direct ADD #imm,Rn Note: * In multiply and accumulate instructions, nnnn is the source register.

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2.5 Instruction Set

2.5.1 Instruction Set by Type

Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Kinds of Instruction Op Code Function Number of Instructions MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Upper/lower swap Data transfer instructions XTRCT Extraction of middle of linked registers ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP/cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double- precision multiply-and-accumulate Arithmetic operation instructions MUL Double-precision multiplication

Rev. 3.00 Sep. 27, 2007 Page 34 of 758 REJ09B0243-0300 Type Kinds of Instruction Op Code Function Number of Instructions MULS Signed multiplication MULU Unsigned multiplication NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry Arithmetic operation instructions SUBV Binary subtraction with underflow AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST T bit setting for logical AND Logic operation instructions XOR Exclusive logical OR ROTL 1-bit left shift ROTR 1-bit right shift ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift SHLR Logical 1-bit right shift Shift instructions SHLRn Logical n-bit right shift

Rev. 3.00 Sep. 27, 2007 Page 35 of 758 REJ09B0243-0300 Type Kinds of Instruction Op Code Function Number of Instructions BF Conditional branch, delayed conditional branch (T = 0) BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure Branch instructions RTS Return from subroutine procedure CLRT T bit clear CLRMAC MAC register clear LDC Load into control register LDS Load into system register NOP No operation RTE Return from exception handling SETT T bit setting SLEEP Transition to power-down mode STC Store from control register STS Store from system register System control instructions TRAPA Trap exception handling Total: 62 142

Rev. 3.00 Sep. 27, 2007 Page 36 of 758 REJ09B0243-0300 The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Summary of Operation Execution Cycles T Bit Indicated by mnemonic. Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* Indicated in MSB ↔ LSB order. Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Indicates summary of operation. Explanation of Symbols →, ←: Transfer direction (xx): Memory operand M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit –: Logical NOT of each bit <<n: n-bit left shift >>n: n-bit right shift Value when no wait cycles are inserted* Value of T bit after instruction is executed Explanation of Symbols : No change Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following:

• When there is contention between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used by the following instruction 2. Scaled ( ×1, ×2, or ×4) according to the instruction operand size, etc. For details, see SH-1/SH-2/SH-DSP Software Manual.

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2.5.2 Data Transfer Instructions

Table 2.11 Data Transfer Instructions Instruction Operation Code Execution Cycles T Bit MOV #imm,Rn imm → Sign extension → Rn 1110nnnniiiiiiii 1  MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign extension → Rn 1001nnnndddddddd 1  MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd 1  MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 1  MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 1  MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 1  MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 1  MOV.B @Rm,Rn (Rm) → Sign extension → Rn 0110nnnnmmmm0000 1  MOV.W @Rm,Rn (Rm) → Sign extension → Rn 0110nnnnmmmm0001 1  MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 1  MOV.B Rm,@–Rn Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 1  MOV.W Rm,@–Rn Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 1  MOV.L Rm,@–Rn Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1  MOV.B @Rm+,Rn (Rm) → Sign extension → Rn, Rm + 1 → Rm 0110nnnnmmmm0100 1  MOV.W @Rm+,Rn (Rm) → Sign extension → Rn, Rm + 2 → Rm 0110nnnnmmmm0101 1  MOV.L @Rm+,Rn (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 1  MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd 1  MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd 1  MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1  MOV.B @(disp,Rm),R0 (disp + Rm) → Sign extension → R0 10000100mmmmdddd 1  MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign extension → R0 10000101mmmmdddd 1  MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1 

Rev. 3.00 Sep. 27, 2007 Page 38 of 758 REJ09B0243-0300 Instruction Operation Code Execution Cycles T Bit MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 1  MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 1  MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 1  MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1100 1  MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1101 1  MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 1  MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd 1  MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1  MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1  MOV.B @(disp,GBR),R0 (disp + GBR) → Sign extension → R0 11000100dddddddd 1  MOV.W @(disp,GBR),R0 (disp × 2 + GBR) → Sign extension → R0 11000101dddddddd 1  MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1  MOVA @(disp,PC),R0 disp × 4 + PC → R0 11000111dddddddd 1  MOVT Rn T → Rn 0000nnnn00101001 1  SWAP.B Rm,Rn Rm → Swap lowest two bytes → Rn 0110nnnnmmmm1000 1  SWAP.W Rm,Rn Rm → Swap two consecutive words → Rn 0110nnnnmmmm1001 1  XTRCT Rm,Rn Rm: Middle 32 bits of Rn → Rn 0010nnnnmmmm1101 1 

Rev. 3.00 Sep. 27, 2007 Page 39 of 758 REJ09B0243-0300

2.5.3 Arithmetic Operation Instructions

Table 2.12 Arithmetic Operation Instructions Instruction Operation Code Execution Cycles T Bit ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 1  ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii 1  ADDC Rm,Rn Rn + Rm + T → Rn, Carry → T 0011nnnnmmmm1110 1 Carry ADDV Rm,Rn Rn + Rm → Rn, Overflow → T 0011nnnnmmmm1111 1 Overflow CMP/EQ #imm,R0 If R0 = imm, 1 → T 10001000iiiiiiii 1 Comparison result CMP/EQ Rm,Rn If Rn = Rm, 1 → T 0011nnnnmmmm0000 1 Comparison result CMP/HS Rm,Rn If Rn ≥ Rm with unsigned data, 1 → T 0011nnnnmmmm0010 1 Comparison result CMP/GE Rm,Rn If Rn ≥ Rm with signed data, 1 → T 0011nnnnmmmm0011 1 Comparison result CMP/HI Rm,Rn If Rn > Rm with unsigned data, 1 → T 0011nnnnmmmm0110

1 Comparison

CMP/GT Rm,Rn If Rn > Rm with signed data, 1 → T 0011nnnnmmmm0111 CMP/PZ Rn If Rn ≥ 0, 1 → T 0100nnnn00010001 1 Comparison result CMP/PL Rn If Rn > 0, 1 → T 0100nnnn00010101 1 Comparison result CMP/STR Rm,Rn If Rn and Rm have an equivalent byte, 1 → T 0010nnnnmmmm1100 DIV1 Rm,Rn Single-step division (Rn/Rm) 0011nnnnmmmm0100

1 Calculation

DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^ Q → T 0010nnnnmmmm0111 1 Calculation result DIV0U 0 → M/Q/T 0000000000011001 1 0 DMULS.L Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm1101 2 to 5* 

Rev. 3.00 Sep. 27, 2007 Page 40 of 758 REJ09B0243-0300 Instruction Operation Code Execution Cycles T Bit DMULU.L Rm,Rn Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm0101 2 to 5*  DT Rn Rn - 1 → Rn, if Rn = 0, 1 → T, else 0 → T 0100nnnn00010000 1 Comparison result EXTS.B Rm,Rn A byte in Rm is sign- extended → Rn 0110nnnnmmmm1110 1  EXTS.W Rm,Rn A word in Rm is sign- extended → Rn 0110nnnnmmmm1111 1  EXTU.B Rm,Rn A byte in Rm is zero- extended → Rn 0110nnnnmmmm1100 1  EXTU.W Rm,Rn A word in Rm is zero- extended → Rn 0110nnnnmmmm1101 1  MAC.L @Rm+,@Rn+ Signed operation of (Rn) × (Rm) + MAC → MAC, 32 × 32 + 64 → 64 bits 0000nnnnmmmm1111 2 to 5*  MAC.W @Rm+,@Rn+ Signed operation of (Rn) × (Rm) + MAC → MAC, 16 × 16 + 64 → 64 bits 0100nnnnmmmm1111 2 to 4*  MUL.L Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits 0000nnnnmmmm0111 2 to 5*  MULS.W Rm,Rn Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits 0010nnnnmmmm1111 1 to 3*  MULU.W Rm,Rn Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 0010nnnnmmmm1110 1 to 3*  NEG Rm,Rn 0-Rm → Rn 0110nnnnmmmm1011 1  NEGC Rm,Rn 0-Rm-T → Rn, Borrow → T 0110nnnnmmmm1010 1 Borrow SUB Rm,Rn Rn-Rm → Rn 0011nnnnmmmm1000 1  SUBC Rm,Rn Rn-Rm–T → Rn, Borrow → T 0011nnnnmmmm1010 1 Borrow SUBV Rm,Rn Rn-Rm → Rn, Underflow → T 0011nnnnmmmm1011 1 Underflow Note: * Indicates the number of execution cycles for normal operation.

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2.5.4 Logic Operation Instructions

Table 2.13 Logic Operation Instructions Instruction Operation Code Execution Cycles T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 1  AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1  AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) 11001101iiiiiiii 3  NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 1  OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1  OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1  OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR) 11001111iiiiiiii 3  TAS.B @Rn If (Rn) is 0, 1 → T; 1 → MSB of (Rn) 0100nnnn00011011 4 Test result TST Rm,Rn Rn & Rm; if the result is 0, 1 → T 0010nnnnmmmm1000 1 Test result TST #imm,R0 R0 & imm; if the result is 0, 1 → T 11001000iiiiiiii 1 Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; if the result is 0, 1 → T 11001100iiiiiiii 3 Test result XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 1  XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii 1  XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm → (R0 + GBR) 11001110iiiiiiii 3 

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2.5.5 Shift Instructions

Table 2.14 Shift Instructions Instruction Operation Code Execution Cycles T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 1 MSB ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 1  SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 1  SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 1  SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 1  SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 1  SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 1 

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2.5.6 Branch Instructions

Table 2.15 Branch Instructions Instruction Operation Code Execution Cycles T Bit BF label If T = 0, disp × 2 + PC → PC; if T = 1, nop 10001011dddddddd 3/1*  BF/S label Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop 10001111dddddddd 2/1*  BT label If T = 1, disp × 2 + PC → PC; if T = 0, nop 10001001dddddddd 3/1*  BT/S label Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop 10001101dddddddd 2/1*  BRA label Delayed branch, disp × 2 + PC → PC 1010dddddddddddd 2  BRAF Rm Delayed branch, Rm + PC → PC 0000mmmm00100011 2  BSR label Delayed branch, PC → PR, disp × 2 + PC → PC 1011dddddddddddd 2  BSRF Rm Delayed branch, PC → PR, Rm + PC → PC 0000mmmm00000011 2  JMP @Rm Delayed branch, Rm → PC 0100mmmm00101011 2  JSR @Rm Delayed branch, PC → PR, Rm → PC 0100mmmm00001011 2  RTS Delayed branch, PR → PC 0000000000001011 2  Note: * One cycle when the branch is not executed.

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2.5.7 System Cont rol Instructions

Table 2.16 System Control Instructions Instruction Operation Code Execution Cycles T Bit CLRT 0 → T 0000000000001000 1 0 CLRMAC 0 → MACH, MACL 0000000000101000 1  LDC Rm,SR Rm → SR 0100mmmm00001110 1 LSB LDC Rm,GBR Rm → GBR 0100mmmm00011110 1  LDC Rm,VBR Rm → VBR 0100mmmm00101110 1  LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 3 LSB LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 3  LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 3  LDS Rm,MACH Rm → MACH 0100mmmm00001010 1  LDS Rm,MACL Rm → MACL 0100mmmm00011010 1  LDS Rm,PR Rm → PR 0100mmmm00101010 1  LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 1  LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 1  LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1  NOP No operation 0000000000001001 1  RTE Delayed branch, Stack area → PC/SR 0000000000101011 5  SETT 1 → T 0000000000011000 1 1 SLEEP Sleep 0000000000011011 4*  STC SR,Rn SR → Rn 0000nnnn00000010 1  STC GBR,Rn GBR → Rn 0000nnnn00010010 1  STC VBR,Rn VBR → Rn 0000nnnn00100010 1  STC.L SR,@–Rn Rn–4 → Rn, SR → (Rn) 0100nnnn00000011 1  STC.L GBR,@–Rn Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 1  STC.L VBR,@–Rn Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 1 

Rev. 3.00 Sep. 27, 2007 Page 45 of 758 REJ09B0243-0300 Instruction Operation Code Execution Cycles T Bit STS MACH,Rn MACH → Rn 0000nnnn00001010 1  STS MACL,Rn MACL → Rn 0000nnnn00011010 1  STS PR,Rn PR → Rn 0000nnnn00101010 1  STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1  STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1  STS.L PR,@–Rn Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 1  TRAPA #imm PC/SR → Stack area, (imm × 4 + VBR) → PC 11000011iiiiiiii 8  Note: * Number of execution cycles until this LSI enters sleep mode. About the number of execution cycles: The table lists the minimum number of execution cycles. In practice, the number of execution cycles will be increased depending on the conditions such as:

• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used by the instruction immediately after the load instruction.

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2.6 Processing States

The CPU has the five processing states: reset, exception handling, program execution, and power- down. Figure 2.4 shows the CPU state transition. When internal power-on reset by WDT or internal manual reset by WDT occurs. From any state when RES = 0 From any state when RES = 1 and MRES = 0 Power-on reset state Manual reset state RES = 0 Reset stateRES = 1 RES = 1, MRES = 1 Exception handling state Exception processing source occurs Exception processing endsProgram execution state NMI interrupt or IRQ interrupt occurs Sleep mode SSBY bit = 1 and STBYMD bit = 1 for SLEEP instruction SSBY bit = 0 for SLEEP instruction Software standby mode Power-down mode Figure 2.4 Transitions between Processing States

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• Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state.
• Exception handling state This state is a transitional state in which the CPU processing state changes due to a request for exception handling such as a reset or an interrupt. When a reset occurs, the execution start address as the initial value of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table. Then, a branch is made for the start address to execute a program. When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to by SP. The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the address is made to execute a program. Then the processing state enters the program execution state.
• Program execution state The CPU executes programs sequentially.
• Power-down state The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter sleep mode or software standby mode.

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Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 49 of 758 REJ09B0243-0300 Section 3 MCU Operating Modes

3.1 Selection of Operating Modes

This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings; do not set these pins in the other way than the shown combinations. When power is applied to the system, be sure to conduct power-on reset. The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user program mode, which are on-chip programming modes are available. Table 3.1 Selection of Operating Modes Pin Setting Mode No. FWE MD1 Mode Name On-Chip ROM Mode 3 0 1 Single chip mode Active Mode 4* 1 0 Boot mode Active Mode 6* 1 1 User program mode Active Note: * Flash memory programming mode.

Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 50 of 758 REJ09B0243-0300

3.2 Input/Output Pins

Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output Function MD1 Input Designates operating mode through the level applied to this pin FWE Input Enables, by hardware, progr amming/erasing of the on-chip flash memory

3.3 Operating Modes

3.3.1 Mode 3 (Single Chip Mode)

All ports can be used in this mode, however the external address cannot be used.

Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 51 of 758 REJ09B0243-0300

3.4 Address Map

The address map for the operating modes are shown in figures 3.1 to 3.3. Mode 3 Single chip mode On-chip ROM (128 kbytes) On-chip RAM (8 kbytes) Reserved area On-chip peripheral I/O registers H'00000000 H'FFFF9FFF H'FFFFA000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'0001FFFF H'00020000 Figure 3.1 Address Map in SH7125, SH7124 (128 Kbytes Flash Memory Version)

Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 52 of 758 REJ09B0243-0300 H'FFFF9FFF H'FFFFA000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'0000FFFF H'00010000 Mode 3 Single chip mode On-chip ROM (64 kbytes) On-chip RAM (8 kbytes) Reserved area On-chip peripheral I/O registers Figure 3.2 Address Map in SH7125, SH7124 (64 Kbytes Flash Memory Version)

Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 53 of 758 REJ09B0243-0300 H'FFFF9FFF H'FFFFA000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'00007FFF H'00008000 Mode 3 Single chip mode On-chip ROM (32 kbytes) On-chip RAM (8 kbytes) Reserved area On-chip peripheral I/O registers Figure 3.3 Address Map in SH7124 (32 Kbytes Flash Memory Version)

Section 3 MCU Operating Modes Rev. 3.00 Sep. 27, 2007 Page 54 of 758 REJ09B0243-0300

3.5 Initial State in This LSI

In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 19, Power-Down Modes.

3.6 Note on Changing Operating Mode

When changing operating mode while power is applied to this LSI, make sure to do it in the power-on reset state (that is, the low level is applied to the RES pin). Note: * See section 21.3.2, Control Signal Timing. tMDS* MD1 RES Figure 3.4 Reset Input Timing when Changing Operating Mode

Section 4 Clock Pulse Generator (CPG) CPGS301C_000020030900 Rev. 3.00 Sep. 27, 2007 Page 55 of 758 REJ09B0243-0300 Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (I φ), a bus clock (Bφ), a peripheral clock (Pφ), and a clock (MPφ) for the MTU2 module. The CPG also controls power- down modes.

4.1 Features

• Five clocks generated independently An internal clock (Iφ) for the CPU; a peripheral clock (Pφ) for the on-chip peripheral modules; a bus clock (Bφ = CK) for the external bus interface; and a MTU2 clock (MPφ) for the on-chip MTU2 module.
• Frequency change function Frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ) can be changed independently using the divider circuit within the CPG. Frequencies are changed by software using the frequency control register (FRQCR) setting.
• Power-down mode control The clock can be stopped in sleep mode and standby mode and specific modules can be stopped using the module standby function.
• Oscillation stop detection If the clock supplied through the clock input pin stops for any reason, the timer pins can be automatically placed in the high-impedance state.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 57 of 758 REJ09B0243-0300 The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at ×8. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins. Divider: The divider generates clocks with the frequencies to be used by the internal clock (I φ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). The frequencies can be selected from 1/2, 1/4 (initial value), and 1/8 times the frequency output from the PLL circuit. The division ratio should be specified in the frequency control register (FRQCR). Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal oscillator. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency according to the setting in the frequency control register (FRQCR). Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator circuit and other modules in sleep or standby mode. Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control bits for the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output through an external pin. Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register (STBCR) has bits for controlling the power-down modes. For details, see section 19, Power-Down Modes.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 58 of 758 REJ09B0243-0300 Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Clock Operating Module Operating Clock Operating Module Internal clock (Iφ) CPU Peripheral clock (P φ) POE UBC SCI ROM A/D RAM CMT WDT Bus clock (Bφ)  MTU2 clock (MP φ) MTU2

4.2 Input/Output Pins

Table 4.2 shows the CPG pin configuration. Table 4.2 Pin Configuration Pin Name Abbr. I/O Description XTAL Output Connects a crystal resonator. Crystal input/output pins (clock input pins) EXTAL Input Connects a crystal resonator or an external clock.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 59 of 758 REJ09B0243-0300

4.3 Clock Operating Mode

Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Source PLL Circuit Input to Divider EXTAL input or crystal resonator ON ( ×8) ×8 The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10 MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 50 MHz. Maximum operating frequencies: Iφ = 50 MHz, Bφ = 40 MHz, Pφ = 40 MHz, and MPφ = 40 MHz Table 4.4 shows the frequency division ratios that can be specified with FRQCR.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 60 of 758 REJ09B0243-0300 Table 4.4 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio I φ B φ P φ MP φ I φ B φ P φ MP φ Input Clock Iφ B φ P φ MP φ ×8 1/8 1/8 1/8 1/8 1 1 1 1 10 10 10 10 10 1/4 1/8 1/8 1/8 2 1 1 1 10 20 10 10 10 1/4 1/4 1/4 1/4 2 2 2 2 10 20 20 20 20 1/2 1/4 1/4 1/4 4 2 2 2 10 40 20 20 20 1/2 1/2 1/2 1/2 4 4 4 4 10 40 40 40 40 1/4 1/8 1/8 1/8 2 1 1 1 12.5 25 12.5 12.5 12.5 1/4 1/4 1/4 1/4 2 2 2 2 12.5 25 25 25 25 1/2 1/4 1/4 1/4 4 2 2 2 12.5 50 25 25 25 Notes: * Clock frequencies when the input clock frequency is assumed to be the shown value. The internal clock (Iφ) frequency must be 10 to 50 MHz and the peripheral clock (Pφ) frequency must be 10 to 40 MHz. The bus clock (Bφ) frequency must be equal to the peripheral clock (Pφ) frequency. 1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1/2, ×1/4, and ×1/8 for each clock by the setting in the frequency control register. 2. The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. 3. The input to the divider is always the output from the PLL circuit. 4. The internal clock (I φ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 50 MHz (maximum operating frequency). 5. The peripheral clock (P φ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz. 6. When using the MTU2, the MTU2 clock (MP φ) frequency must be equal to or higher than the peripheral clock frequency (Pφ). The MTU2 clock (MPφ) frequency are the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. 7. The frequency of the CK pin is always be equal to the bus clock (B φ) frequency. 8. The bus clock (B φ) frequency must be equal to the peripheral clock (Pφ) frequency.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 61 of 758 REJ09B0243-0300

4.4 Register Descriptions

The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers Table 4.5 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Frequency control register FRQCR R/W H'36DB H'FFFFE800 16 Oscillation stop detection control register OSCCR R/W H'00 H'FFFFE814 8

4.4.1 Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). FRQCR can be accessed only in words. FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT overflow). Before making changes to FRQCR, stop clock supply to each module except the CPU, on-chip ROM, and on-chip-RAM. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0011011011011011 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ---- IFC[2:0] BFC[2:0] PFC[2:0] MPFC[2:0]

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 62 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IFC[2:0] 011 R/W Internal Clock (I φ) Frequency Division Ratio Specify the division ratio of the internal clock (Iφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited 11 to 9 BFC[2:0] 011 R/W Bus Clock (B φ) Frequency Division Ratio Specify the division ratio of the bus clock (Bφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 63 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 8 to 6 PFC[2:0] 011 R/W Peripheral Clock (P φ) Frequency Division Ratio Specify the division ratio of the peripheral clock (Pφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited 5 to 3  011 R/W Reserved These bits are always read as B'011. The write value should always be B'011. 2 to 0 MPFC[2:0] 011 R/W MTU2 Clock (MP φ) Frequency Division Ratio Specify the division ratio of the MTU2 clock (MPφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 64 of 758 REJ09B0243-0300

4.4.2 Oscillation Stop Detection Control Register (OSCCR)

OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRR R / W ----- OSC STOP - OSC ERS Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 OSCSTOP 0 R Oscillation Stop Detection Flag

[Setting conditions]

• When a stop in the clock input is detected during normal operation
• When software standby mode is entered [Clearing conditions]
• By a power-on reset input through the RES pin
• When software standby mode is canceled 1  0 R Reserved This bit is always read as 0. The write value should always be 0.

0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select

Selects whether to output the oscillation stop detection flag signal through the WDTOVF pin. 0: Outputs only the WDT overflow signal through the WDTOVF pin 1: Outputs the WDT overflow signal and the oscillation stop detection flag signal through the WDTOVF pin

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 65 of 758 REJ09B0243-0300

4.5 Changing Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software through the frequency control register (FRQCR). The following describes how to specify the frequencies. 1. In the initial state, IFC2 to IFC0 = H'011 ( ×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to PFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011 (×1/4). 2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM. 3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, and MPFC2 to MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at ×8, the frequencies are determined only be selecting division ratios. When specifying the frequencies, satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) = peripheral clock (Pφ). When using the MTU2 clock, specify the frequencies to satisfy the following condition: internal clock (Iφ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ). 4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11Bφ + 7Pφ. n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/4, or 1/8) cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Note: (1 to 24n) depends on the internal state.

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 66 of 758 REJ09B0243-0300

4.6 Oscillator

Clock pulses can be supplied from a connected crystal resonator or an external clock.

4.6.1 Connecting Crystal Resonator

A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6. Use a crystal resonator that has a resonance frequency of 10 to 12.5 MHz. It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI. EXTAL XTAL Rd CL2 CL1 CL1 = CL2 = 18 to 22 pF (Reference values) Figure 4.2 Connection of Crystal Resonator (Example) Table 4.6 Damping Resistan ce Values (Reference Values) Frequency (MHz) 10 12.5 Rd (Ω) (Reference Values) 0 0 Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.7. XTAL CL EXTAL L Rs Figure 4.3 Crystal Resonator Equivalent Circuit

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 67 of 758 REJ09B0243-0300 Table 4.7 Crystal Resonator Characteristics Frequency (MHz) 10 12.5 Rs Max. (Ω) (Reference Values) 60 50 C0 Max. (pF) (Reference Values) 7 7

4.6.2 External Clock Input Method

Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in software standby mode. During operation, make the external input clock frequency 10 to 12.5 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing software standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL External clock input Open state Figure 4.4 Example of External Clock Connection

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 68 of 758 REJ09B0243-0300

4.7 Function for Detect ing Oscillator Stop

This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 are assigned) are always placed in high-impedance state regardless of the PFC setting. For details, refer to appendix A, Pin States. Even in software standby mode, these pins are always placed in high-impedance state. For details, refer to appendix A, Pin States. These pins enter the normal state after software standby mode is canceled. Under an abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI operations other than the oscillation stop detection function become unpredictable. In this case, even after oscillation is restarted, LSI operations including the above high-current pins become unpredictable. Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and operating voltage).

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 69 of 758 REJ09B0243-0300

4.8 Usage Notes

4.8.1 Note on Crystal Resonator

A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user’s board design. As the oscillator circuit's circuit constant will depend on the resonator and the floating capacitance of the mounting circuit, the value of each external circuit’s component should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.

4.8.2 Notes on Board Design

Measures against radiation noise are taken in this LSI. If further reduction in radiation noise is needed, it is recommended to use a multiple layer board and provide a layer exclusive to the system ground. When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. CL2 Signal A Signal B This LSI CL1 XTAL EXTAL Avoid Figure 4.5 Cautions for Oscillator Circuit Board Design

Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 70 of 758 REJ09B0243-0300 A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. PLLVSS VCL VCC VSS CPB = 0.1 µF* CB = 0.1 µF* (Recommended values are shown.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry around PLL

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 71 of 758 REJ09B0243-0300 Section 5 Exception Handling

5.1 Overview

5.1.1 Types of Exception Handling and Priority

Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority. Table 5.1 Types of Exceptions and Priority Exception Exception Source Priority Reset Power-on reset High Manual reset Interrupt User break (break before instruction execution) Address error CPU address error (instruction fetch) Instruction General illegal instructions (undefined code) Illegal slot instruction (undefined code placed immediately after a delayed branch instruction* or instruction that changes the PC value* Trap instruction (TRAPA instruction) Address error CPU address error (data access) Interrupt User break (break after instruction execution or operand break) NMI IRQ On-chip peripheral modules Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.

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5.1.2 Exception Handling Operations

The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Detection and Start of Exception Handling Exception Timing of Source Detection and Start of Exception Handling Reset Power-on reset Started when the RES pin changes from low to high or when the WDT overflows. Manual reset Started when the MRES pin changes from low to high or when the WDT overflows. Address error Interrupt Detected during the instruction decode stage and started after the execution of the current instruction is completed. Instruction Trap instruction Started by the execution of the TRAPA instruction. General illegal instructions Started when an undefined code placed at other than a delay slot (immediately after a delayed branch instruction) is decoded. Illegal slot instructions Started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the PC value is detected. When exception handling starts, the CPU operates Exception Handling Triggered by Reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC from the address H'00000000 and SP from the address H'00000004 when a power-on reset. PC from the address H'00000008 and SP from the address H'0000000C when a manual reset.). For details, see section 5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program starts from the PC address fetched from the exception handling vector table. Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception handling, bits I3 to I0 are not affected. The start address is then fetched from the exception handling vector table and the program starts from that address.

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5.1.3 Exception Handling Vector Table

Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Vector Numbers and Vector Table Address Offsets Exception Handling Source Vector Number Vector Table Address Offset Power-on reset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 Manual reset PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved for system use) 5 H'00000014 to H'00000017 Illegal slot instruction 6 H'00000018 to H'0000001B (Reserved for system use) 7 H'0000001C to H'0000001F

8 H'00000020 to H'00000023

CPU address error 9 H'00000024 to H'00000027 (Reserved for system use) 10 H'00000028 to H'0000002B Interrupt NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 (Reserved for system use) 13 H'00000034 to H'00000037 : :

31 H'0000007C to H'0000007F

Trap instruction (user vector) 32 H'00000080 to H'00000083 : :

63 H'000000FC to H'000000FF

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 74 of 758 REJ09B0243-0300 Exception Handling Source Vector Number Vector Table Address Offset Interrupt IRQ0 (SH7125) 64 H'00000100 to H'00000103 IRQ1 65 H'00000104 to H'00000107 IRQ2 66 H'00000108 to H'0000010B IRQ3 67 H'0000010C to H'0000010F (Reserved for system use) 68 H'00000110 to H'00000113 : :

71 H'0000011C to H'0000011F

On-chip peripheral module* 72 H'00000120 to H'00000123 : :

255 H'000003FC to H'000003FF

Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) × 4 Address errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3.

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5.2 Resets

5.2.1 Types of Resets

Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset State Internal State Type RES WDT Overflow MRES CPU, INTC On-Chip Peripheral Module POE, PFC, I/O Port Low   Initialized Initialized Initialized Power-on reset High Overflow High Initialized Initialized Initialized High Not overflowed Low Initialized Not initialized Not initialized Manual reset High Overflow High Initialized Not initialized Not initialized

5.2.2 Power-On Reset

Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during power-on reset mode. In the power-on reset state, power-on reset exception handling starts when driving the RES pin high after driving the pin low for the given time. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111).

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 76 of 758 REJ09B0243-0300 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Be certain to always perform power-on reset exception handling when turning the system power on. Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-on reset state. The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog timer (WDT) registers are not initialized by a reset generated by the WDT (these registers are only initialized by a power-on reset from the RES pin). If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When the power-on reset exception handling caused by the WDT is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in the PC and SP, then the program starts.

5.2.3 Manual Reset

When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT when in software standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets.

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 77 of 758 REJ09B0243-0300

5.3 Address Errors

5.3.1 Address Error Sources

Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors CPU Instruction fetched from even address None (normal) Instruction fetch Instruction fetched from odd address Address error occurs Instruction fetched from a space other than on-chip peripheral module space None (normal) Instruction fetched from on-chip peripheral module space Address error occurs Instruction fetched from external memory space in single chip mode Address error occurs Word data accessed from even address None (normal) Data read/write CPU Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Byte or word data accessed in on-chip peripheral module space None (normal) Longword data accessed in 16-bit on-chip peripheral module space None (normal) Longword data accessed in 8-bit on-chip peripheral module space None (normal) Reserved space accessed when in single chip mode Address error occurs

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5.3.2 Address Error Exception Source

When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address of the instruction which caused an address error exception. When the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately before the delay slot. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the generated address error, and the program starts executing from that address. This branch is not a delayed branch.

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 79 of 758 REJ09B0243-0300

5.4 Interrupts

5.4.1 Interrupt Sources

Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller (UBC) 1 IRQ IRQ0 to IRQ3 pins (external input) 4 (SH7125) 3 (SH7124) On-chip peripheral module Multi-function timer pulse unit 2 (MTU2) 28 Watchdog timer (WDT) 1 A/D converter (A/D_0 and A/D_1) 2 Compare match timer (CMT_0 and CMT_1) 2 Serial communication interface (SCI_0, SCI_1, and SCI_2) Port output enable (POE) 2 All interrupt sources are given different vector numbers and vector table address offsets. For details on vector numbers and vector table address offsets, see table 6.3 in section 6, Interrupt Controller (INTC).

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5.4.2 Interrupt Priority

The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRF, see section 6.3.4, Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Table 5.8 Interrupt Priority Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. Can be masked. IRQ 0 to 15 On-chip peripheral module Set with interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM).

5.4.3 Interrupt Exception Handling

When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception handling begins. In interrupt exception handling, the CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. For details on the interrupt exception handling, see section 6.6, Interrupt Operation.

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 81 of 758 REJ09B0243-0300

5.5 Exceptions Triggered by Instructions

5.5.1 Types of Exceptions Triggered by Instructions

Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instruction TRAPA  Illegal slot instructions* Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the PC value Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that changes the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR General illegal instructions* Undefined code anywhere besides in a delay slot Note: * The operation is not guaranteed when und efined instructions other than H'F000 to H'FFFF are decoded.

5.5.2 Trap Instructions

When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start addr ess of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in the TRAPA instruction, program execution branches to that address, and then the program starts. This branch is not a delayed branch.

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5.5.3 Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred. Program execution branches to that address and the program starts. This branch is not a delayed branch.

5.5.4 General Illegal Instructions

When an undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code.

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5.6 Cases when Excep tions are Accepted

When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the exception is accepted. Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions Exception Occurrence Timing Address Error General Illegal Instruction Slot Illegal Instruction Trap Instruction Interrupt Instruction in delay slot ×*  ×*  ×* Immediately after interrupt disabled instruction* [Legend] √: Accepted ×: Not accepted : Does not occur 2. An exception is accepted before the execution of a delayed branch instruction. However, when an address error or a slot illegal instruction exception occurs in the delay slot of the RTE instruction, correct operation is not guaranteed. 3. An exception is accepted after a delayed branch (between instructions in the delay slot and the branch destination). 4. An exception is accepted after the execution of the next instruction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction).

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5.7 Stack States after Exception Handling Ends

The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Stack State Address error (when the instruction that caused an exception is placed in the delay slot) SP Address of delayed branch instruction SR → 32 bits 32 bits Address error (other than above) SP SR → 32 bits 32 bits Address of instruction that caused exception Interrupt SP SR → 32 bits 32 bits Address of instruction after executed instruction Trap instruction SP SR → 32 bits 32 bits Address of instruction after TRAPA instruction

Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 85 of 758 REJ09B0243-0300 Types Stack State Illegal slot instruction SP Address of delayed branch instruction SR → 32 bits 32 bits General illegal instruction SP SR → 32 bits 32 bits Address of general illegal instruction

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5.8 Usage Notes

5.8.1 Value of Stack Pointer (SP)

The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling.

5.8.2 Value of Vector Base Register (VBR)

The VBR value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling.

5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling

When the SP value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. Address errors will also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be passed to the handling routine for address error exception and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. When stacking the SR and PC values, the SP values for both are subtracted by 4, therefore, the SP value is still not a multiple of 4 after the stacking. The address value output during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is undefined.

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5.8.4 Notes on Slot Illegal Instruction Exception Handling

Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2.

• Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions.
• This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal instructions. The supporting status on our software products regarding this note is as follows: Compiler This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions. Real-time OS for µITRON specifications 1. HI7000/4, HI-SH7 This instruction does not exist in the delay slot within the OS. 2. HI7000 This instruction is in part allocated to the delay slot within the OS, which may cause the slot illegal instruction exception handling in this LSI. 3. Others The slot illegal instruction exception handling may be generated in this LSI in a case where the instruction is described in assembler or when the middleware of the object is introduced. Note that a check-up program (checker) to pick up this instruction is available on our website. Download and utilize this checker as needed.

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Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 89 of 758 REJ09B0243-0300 Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU.

6.1 Features

• 16 levels of interrupt priority
• NMI noise canceller function
• Occurrence of interrupt can be reported externally (IRQOUT pin)

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 91 of 758 REJ09B0243-0300

6.2 Input/Output Pins

Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbr. I/O Function Non-maskable interrupt input pin NMI Input Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of notification signal when an interrupt has occurred

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 92 of 758 REJ09B0243-0300

6.3 Register Descriptions

The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 6.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Interrupt control register 0 ICR0 R/W H'x000 H'FFFFE900 8, 16 IRQ control register IRQCR R/W H'0000 H'FFFFE902 8, 16 IRQ status register IRQSR R/W H'Fx00 H'FFFFE904 8, 16 Interrupt priority register A IPRA R/W H'0000 H'FFFFE906 8, 16 Interrupt priority register B IPRB R/W H'0000 H'FFFFE908 8, 16 Interrupt priority register C IPRC R/W H'0000 H'FFFFE980 16 Interrupt priority register D IPRD R/W H'0000 H'FFFFE982 16 Interrupt priority register E IPRE R/W H'0000 H'FFFFE984 16 Interrupt priority register F IPRF R/W H'0000 H'FFFFE986 16 Interrupt priority register H IPRH R/W H'0000 H'FFFFE98A 16 Interrupt priority register I IPRI R/W H'0000 H'FFFFE98C 16 Interrupt priority register J IPRJ R/W H'0000 H'FFFFE98E 16 Interrupt priority register K IPRK R/W H'0000 H'FFFFE990 16 Interrupt priority register L IPRL R/W H'0000 H'FFFFE992 16 Interrupt priority register M IPRM R/W H'0000 H'FFFFE994 16

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 93 of 758 REJ09B0243-0300

6.3.1 Interrupt Control Register 0 (ICR0)

ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 Note: The initial value is 1 when the level on the NMI pin is high, and 0 when the level on the pin is low.* * 000000000000000 RRRRRRR R / W RRRRRRRR Bit Bit Name Initial Value R/W Description

15 NMIL * R NMI Input Level

Indicates the state of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: State of the NMI input is low 1: State of the NMI input is high 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 NMIE 0 R/W NMI Edge Select

0: Interrupt request is detected on the falling edge of the NMI input 1: Interrupt request is detected on the rising edge of the NMI input 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 94 of 758 REJ09B0243-0300

6.3.2 IRQ Control Register (IRQCR)

IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ3. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. IRQ31S IRQ30S R/W R/W IRQ3 Sense Select Set the interrupt request detection mode for pin IRQ3. 00: Interrupt request is detected at the low level of pin IRQ3 01: Interrupt request is detected at the falling edge of pin IRQ3 10: Interrupt request is detected at the rising edge of pin IRQ3 11: Interrupt request is detected at both the falling and rising edges of pin IRQ3 IRQ21S IRQ20S R/W R/W IRQ2 Sense Select Set the interrupt request detection mode for pin IRQ2. 00: Interrupt request is detected at the low level of pin IRQ2 01: Interrupt request is detected at the falling edge of pin IRQ2 10: Interrupt request is detected at the rising edge of pin IRQ2 11: Interrupt request is detected at both the falling and rising edges of pin IRQ2

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 95 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description IRQ11S IRQ10S R/W R/W IRQ1 Sense Select Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1 11: Interrupt request is detected at both the falling and rising edges of pin IRQ1 IRQ01S IRQ00S R/W R/W IRQ0 Sense Select (SH7125) Set the interrupt request detection mode for pin IRQ0. 00: Interrupt request is detected at the low level of pin IRQ0 01: Interrupt request is detected at the falling edge of pin IRQ0 10: Interrupt request is detected at the rising edge of pin IRQ0 11: Interrupt request is detected at both the falling and rising edges of pin IRQ0 Reserved (SH7124) These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 96 of 758 REJ09B0243-0300

6.3.3 IRQ Status register (IRQSR)

IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ3 and the status of interrupt request. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111 **** 00000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W Note: The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low.* - - - - IRQ3L IRQ2L IRQ1L IRQ0L - - - - IRQ3F IRQ2F IRQ1F IRQ0F Bit Bit Name Initial Value R/W Description 15 to 12  All 1 R Reserved These bits are always read as 1. 11 IRQ3L * R Indicates the state of pin IRQ3. 0: State of pin IRQ3 is low 1: State of pin IRQ3 is high 10 IRQ2L * R Indicates the state of pin IRQ2. 0: State of pin IRQ2 is low 1: State of pin IRQ2 is high 9 IRQ1L * R Indicates the state of pin IRQ1. 0: State of pin IRQ1 is low 1: State of pin IRQ1 is high 8 IRQ0L * R Indicates the state of pin IRQ0. 0: State of pin IRQ0 is low 1: State of pin IRQ0 is high 7to 4  All 0  Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 97 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 3 IRQ3F 0 R/W Indicates the status of an IRQ3 interrupt request.

• When level detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low
• When edge detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing conditions]  Writing 0 after reading IRQ3F = 1  Accepting an IRQ3 interrupt 1: An IRQ3 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ3

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 98 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 2 IRQ2F 0 R/W Indicates the status of an IRQ2 interrupt request.

• When level detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low
• When edge detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing conditions]  Writing 0 after reading IRQ2F = 1  Accepting an IRQ2 interrupt 1: An IRQ2 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ2 1 IRQ1F 0 R/W Indicates the status of an IRQ1 interrupt request.
• When level detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing condition] Driving pin IRQ1 high 1: An IRQ1 interrupt has been detected [Setting condition] Driving pin IRQ1 low
• When edge detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing conditions]  Writing 0 after reading IRQ1F = 1  Accepting an IRQ1 interrupt 1: An IRQ1 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ1

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 99 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 0 IRQ0F 0 R/W Indicates the status of an IRQ0 interrupt request.

• When level detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low
• When edge detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing conditions]  Writing 0 after reading IRQ0F = 1  Accepting an IRQ0 interrupt 1: An IRQ0 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ0 Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low.

6.3.4 Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to

IPRM) Interrupt priority registers are twelve 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000). Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IPR[15:12] IPR[11:8] IPR[7:4] IPR[3:0]

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 100 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 15 to 12 IPR[15:12] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 11 to 8 IPR[11:8] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest)

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 101 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 7 to 4 IPR[7:4] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 3 to 0 IPR[3:0] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 102 of 758 REJ09B0243-0300

6.4 Interrupt Sources

6.4.1 External Interrupts

There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Use the IRQ sense select bits (IRQ31S, IRQ30S to IRQ01S, and IRQ00S) in the IRQ control register (IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA). In the case that the low level detection is selected, an interrupt request signal is sent to the INTC while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when the following change on the IRQ pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been detected by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). An IRQ interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag after reading 1. In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of the IRQ3 to IRQ0 interrupts.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 103 of 758 REJ09B0243-0300 IRQCR.IRQn1S IRQCR.IRQn0S IRQSR.IRQnF IRQSR.IRQnL IRQn pins RESIRQn Level detection Edge detection SQ R Selection CPU interrupt request (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) n = 3 to 0 Distribution Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control

6.4.2 On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. Since a different interrupt vector is allocated to each interrupt source, the exception handling routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers C to F and H to M (IPRC to IPRF and IPRH to IPRM). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted.

6.4.3 User Break Interrupt

A user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section 7, User Break Controller (UBC).

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6.5 Interrupt Exception Handling Vector Table

Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets. For interrupt exception handling, the start address of the exception handling routine is fetched from the vector table address in the vector table. For the details on calculation of vector table addresses, see table 5.4 in section 5, Exception Handling. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). However, when interrupt sources whose priority levels are allocated with the same IPR are requested, the interrupt of the smaller vector number has priority. This priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.3.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 105 of 758 REJ09B0243-0300 Table 6.3 Interrupt Exception Handling Vectors and Priorities Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority User break 12 H'00000030  High External pin NMI 11 H'0000002C  IRQ0 (only SH7125) 64 H'00000100 IPRA15 to IPRA12 IRQ1 65 H'00000104 IPRA11 to IPRA8 IRQ2 66 H'00000108 IPRA7 to IPRA4 IRQ3 67 H'0000010C IPRA3 to IPRA0 TGIA_0 88 H'00000160 IPRD15 to IPRD12 TGIB_0 89 H'00000164 TGIC_0 90 H'00000168 TGID_0 91 H'0000016C TCIV_0 92 H'00000170 IPRD11 to IPRD8 TGIE_0 93 H'00000174 MTU2_0 TGIF_0 94 H'00000178 TGIA_1 96 H'00000180 IPRD7 to IPRD4 TGIB_1 97 H'00000184 TCIV_1 100 H'00000190 IPRD3 to IPRD0 MTU2_1 TCIU_1 101 H'00000194 MTU2_2 TGIA_2 104 H'000001A0 IPRE15 to IPRE12 TGIB_2 105 H'000001A4 TCIV_2 108 H'000001B0 IPRE11 to IPRE8 TCIU_2 109 H'000001B4 MTU2_3 TGIA_3 112 H'000001C0 IPRE7 to IPRE4 TGIB_3 113 H'000001C4 TGIC_3 114 H'000001C8 TGID_3 115 H'000001CC TCIV_3 116 H'000001D0 IPRE3 to IPRE0 Low

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 106 of 758 REJ09B0243-0300 Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority MTU2_4 TGIA_4 120 H'000001E0 IPRF15 to IPRF12 High TGIB_4 121 H'000001E4 TGIC_4 122 H'000001E8 TGID_4 123 H'000001EC TCIV_4 124 H'000001F0 IPRF11 to IPRF8 MTU2_5 TGIU_5 128 H'00000200 IPRF7 to IPRF4 TGIV_5 129 H'00000204 TGIW_5 130 H'00000208 POE (MTU2) OEI1 132 H'00000210 IPRF3 to IPRF0 OEI3 133 H'00000214 CMT_0 CMI_0 184 H'000002E0 IPRJ15 to IPRJ12 CMT_1 CMI_1 188 H'000002F0 IPRJ11 to IPRJ8 WDT ITI 196 H'00000310 IPRJ3 to IPRJ0 ADI_0 200 H'00000320 IPRK15 to IPRK12 A/D_0 and A/D_1 ADI_1 201 H'00000324 SCI_0 ERI_0 216 H'00000360 IPRL15 to IPRL12 RXI_0 217 H'00000364 TXI_0 218 H'00000368 TEI_0 219 H'0000036C SCI_1 ERI_1 220 H'00000370 IPRL11 to IPRL8 RXI_1 221 H'00000374 TXI_1 222 H'00000378 TEI_1 223 H'0000037C SCI_2 ERI_2 224 H'00000380 IPRL7 to IPRL4 RXI_2 225 H'00000384 TXI_2 226 H'00000388 TEI_2 227 H'0000038C Low

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 107 of 758 REJ09B0243-0300

6.6 Interrupt Operation

6.6.1 Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority shown in table 6.3. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt contro ller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling. 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR. 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in 5. above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the IRQOUT pin holds low level. 9. The CPU reads the start addr ess of the exception handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. This branch is not a delayed branch.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 108 of 758 REJ09B0243-0300 Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (IRQSR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 109 of 758 REJ09B0243-0300 Program execution state Interrupt? User break? I3 to I0 ≤ level 14? Level 14 interrupt? Level 1 interrupt?I3 to I0 ≤ level 13? I3 to I0 = level 0? No Yes No No No No No No No Yes Yes Yes Yes Yes Yes Yes Save SR to stack IRQOUT = low Save PC to stack Copy interrupt level to I3 to I0 Read exception vector table Branch to exception handling routine No Yes Level 15 interrupt? Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU 1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. 3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (Iφ) and bus (Bφ) clocks. This flowchart shows that the frequency dividing ratios of the internal (Iφ) and bus (Bφ) clocks are the same. NMI? I3 to I0 ≤ level 14? No Yes IRQOUT = high *1*3 *2*3 Figure 6.3 Interrupt Sequence Flowchart

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 110 of 758 REJ09B0243-0300

6.6.2 Stack after Interrupt Exception Handling

Figure 6.4 shows the stack after interrupt exception handling. 32 bits 32 bits PC*1 SR Address 4n – 8 4n – 4 SP*2 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling

6.7 Interrupt Response Time

Table 6.4 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins.

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 111 of 758 REJ09B0243-0300 Table 6.4 Interrupt Response Time Number of Cycles Item NMI IRQ Peripheral Modules Remarks Interrupt priority decision and comparison with mask bits in SR 1 × Icyc + 2 × Pcyc 1 × Icyc + 1 × Pcyc 1 × Icyc + 2 × Pcyc Wait for completion of sequence currently being executed by CPU X ( ≥ 0) X ( ≥ 0) X ( ≥ 0) The longest sequence is for interrupt or address- error exception handling (X = 7 × Icyc + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts 8 × Icyc + m1 + m2 + m3 8 × Icyc + m1 + m2 + m3 8 × Icyc + m1 + m2 + m3 Performs the saving PC and SR, and vector address fetch. Interrupt response time Total: 9 × Icyc + 2 × Pcyc + m1 + m2 + m3 + X 9 × Icyc + 1 × Pcyc + m1 + m2 + m3 + X 9 × Icyc + 2 × Pcyc + m1 + m2 + m3 + X Minimum *: 12 × Icyc + 2 × Pcyc 12 × Icyc + 1 × Pcyc 12 × Icyc + 2 × Pcyc SR, PC, and vector table are all in on-chip RAM. Maximum: 16 × Icyc + 2 × Pcyc + 2 × (m1 + m2 + m3) + m4 16 × Icyc + 1 × Pcyc + 2 (m1 + m2 + m3) + m4 16 × Icyc + 2 × Pcyc + 2 (m1 + m2 + m3) + m4 Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine

Section 6 Interrupt Controller (INTC) Rev. 3.00 Sep. 27, 2007 Page 112 of 758 REJ09B0243-0300

6.8 Usage Note

The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction.

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 113 of 758 REJ09B0243-0300 Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch.

7.1 Features

The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle).

• Address Comparison bits are maskable in 1-bit units. One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected.
• Data 32-bit maskable. One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected.
• Bus cycle Instruction fetch or data access
• Read/write
• Operand size Byte, word, and longword 2. A user-designed user-break condition interrupt exception processing routine can be run. 3. In an instruction fetch cycle, it can be select ed that a user-break is set before or after an instruction is executed. 4. Maximum repeat times for the break condition (only for channel B): 2 – 1 times. 5. Four pairs of branch source/destination buffers.

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7.2 Register Descriptions

The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 7.1 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Break address register A BARA R/W H'00000000 H'FFFFF300 32 Break address mask register A BAMRA R/W H'00000000 H'FFFFF304 32 Break bus cycle register A BBRA R/W H'0000 H'FFFFF308 16 Break data register A BDRA R/W H'00000000 H'FFFFF310 32 Break data mask register A BDMRA R/W H'00000000 H'FFFFF314 32 Break address register B BARB R/W H'00000000 H'FFFFF320 32 Break address mask register B BAMRB R/W H'00000000 H'FFFFF324 32 Break bus cycle register B BBRB R/W H'0000 H'FFFFF328 16 Break data register B BDRB R/W H'00000000 H'FFFFF330 32 Break data mask register B BDMRB R/W H'00000000 H'FFFFF334 32 Break control register BRCR R/W H'00000000 H'FFFFF3C0 32 Branch source register BRSR R H'0xxxxxxx H'FFFFF3D0 32 Branch destination register BRDR R H'0xxxxxxx H'FFFFF3D4 32 Execution times break register BETR R/W H'0000 H'FFFFF3DC 16

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7.2.1 Break Address Register A (BARA)

BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Bit Bit Name Initial Value R/W Description 31 to 0 BAA31 to BAA 0 All 0 R/W Break Address A Store the address on the LAB or IAB specifying break conditions of channel A.

7.2.2 Break Address Mask Register A (BAMRA)

BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 117 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 31 to 0 BAMA31 to BAMA 0 All 0 R/W Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0

7.2.3 Break Bus Cycle Register A (BBRA)

BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel A. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - - - - - CPA[2:0] CDA[1:0] IDA[1:0] RWA[1:0] SZA[1:0] Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CPA[2:0] 000 R/W Bus Master Select A for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel A break condition. However, when the L bus is selected as the bus cycle, the setting of the CPA2 to CPA0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: Setting prohibited

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 118 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 7, 6 CDA[1:0] 00 R/W L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 5, 4 IDA[1:0] 00 R/W Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3, 2 RWA[1:0] 00 R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1, 0 SZA[1:0] 00 R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care.

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7.2.4 Break Data Register A (BDRA)

BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R/W Description 31 to 0 BDA31 to BDA0 All 0 R/W Break Data Bit A Stores data, which specifies a break condition in channel A. If the I bus is selected in BBRA, the break data on IDB is set in BDA31 to BDA0. If the L bus is selected in BBRA, the break data on LDB is set in BDA31 to BDA0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRA as the break data.

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7.2.5 Break Data Mask Register A (BDMRA)

BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 Bit Bit Name Initial Value R/W Description 31 to 0 BDMA31 to BDMA 0 All 0 R/W Break Data Mask A Specifies bits masked in the break data of channel A specified by BDRA (BDA31 to BDA0). 0: Break data BDAn of channel A is included in the break condition 1: Break data BDAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA.

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7.2.6 Break Address Register B (BARB)

BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break condition B. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 Bit Bit Name Initial Value R/W Description 31 to 0 BAB31 to BAB 0 All 0 R/W Break Address B Stores an address, which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0.

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7.2.7 Break Address Mask Register B (BAMRB)

BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 Bit Bit Name Initial Value R/W Description 31 to 0 BAMB31 to BAMB 0 All 0 R/W Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0

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7.2.8 Break Data Register B (BDRB)

BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 Bit Bit Name Initial Value R/W Description 31 to 0 BDB31 to BDB0 All 0 R/W Break Data Bit B Stores data which specifies a break condition in channel If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data.

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7.2.9 Break Data Mask Register B (BDMRB)

BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Bit Bit Name Initial Value R/W Description 31 to 0 BDMB31 to BDMB 0 All 0 R/W Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRB as the break mask data in BDRB.

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7.2.10 Break Bus Cycle Register B (BBRB)

BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - - - - - CPB[2:0] IDB[1:0] CDB[1:0] RWB[1:0] SZB[1:0] Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CPB[2:0] 000 R/W Bus Master Select B for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel B break condition. However, when the L bus is selected as the bus cycle, the setting of the CPB2 to CPB0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: Setting prohibited 7, 6 CDB[1:0] 00 R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 126 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 5, 4 IDB[1:0] 00 R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3, 2 RWB[1:0] 00 R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1, 0 SZB[1:0] 0 R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care.

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7.2.11 Break Control Register (BRCR)

BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channels A and B in comparison conditions. 5. Enable PC trace. 6. Specify whether to request the user break interrupt when channels A and B match with comparison conditions. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRR R / W R R / W R 0000000000000000 R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R R/W R R R/W SCM FCA SCM FCB SCM FDA SCM FDB PCTE PCBA - - DBEA PCBB DBEB - SEQ - - ETBE Bit Bit Name Initial Value R/W Description 31 to 20  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

19 UBIDB 0 R/W User Break Disable B

Enables or disables the user break interrupt request when the channel B break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 128 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 18  0 R Reserved This bit is always read as 0. The write value should always be 0.

17 UBIDA 0 R/W User Break Disable A

Enables or disables the user break interrupt request when the channel A break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 16  0 R Reserved This bit is always read as 0. The write value should always be 0.

15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A

When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches

14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B

When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches

13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A

When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches

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12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B

When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches

11 PCTE 0 R/W PC Trace Enable

0: Disables PC trace 1: Enables PC trace

10 PCBA 0 R/W PC Break Select A

Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 DBEA 0 R/W Data Break Enable A

Selects whether or not the data bus condition is included in the break condition of channel A. 0: No data bus condition is included in the condition of channel A 1: The data bus condition is included in the condition of channel A

6 PCBB 0 R/W PC Break Select B

Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution

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5 DBEB 0 R/W Data Break Enable B

Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 4  0 R Reserved This bit is always read as 0. The write value should always be 0.

3 SEQ 0 R/W Sequence Condition Select

Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 ETBE 0 R/W Number of Execution Times Break Enable

Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is requested when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B

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7.2.12 Execution Times Break Register (BETR)

BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 – 1 times. When a break condition is satisfied, it decreases BETR. A user- break interrupt is requested when the break condition is satisfied after BETR becomes H'0001. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - - - - BET[11:0] Bit Bit Name Initial Value R/W Description 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET[11:0] All 0 R/W Number of Execution Times

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7.2.13 Branch Source Register (BRSR)

BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRSR is read or the setting to enable PC trace is made. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR RRRRRRRRRRRRRRRR SVF - - - BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 Bit Bit Name Initial Value R/W Description

31 SVF 0 R BRSR Valid Flag

Indicates whether the branch source address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 Undefined R Branch Source Address Store bits 27 to 0 of the branch source address.

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7.2.14 Branch Destination Register (BRDR)

BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRDR is read or the setting to enable PC trace is made. Other bits are not initialized by a power-on reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR RRRRRRRRRRRRRRRR DVF - - - BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R/W Description

31 DVF 0 R BRDR Valid Flag

Indicates whether a branch destination address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 Undefined R Branch Destination Address Store bits 27 to 0 of the branch destination address.

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7.3 Operation

7.3.1 Flow of the User Break Operation

The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break a ddress registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRA or BDRB). The masked data is set in the break data mask register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with B'00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. Before using them again, 0 must first be written to them and then reset flags. 4. There may be an occasion when a break condition match occurs both in channels A and B around the same time. In this case, the flags for both conditions matches will be set even though only one user-break interrupt request is issued to the CPU. 5. When selecting the I bus as the break condition, note the following:  The CPU is connected to the I bus. The UBC monitors bus cycles generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the CPB2 to CPB0 bits in BBRB, and compares the condition match.  I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles.  If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the user- break is to be accepted cannot be clearly defined.

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7.3.2 Break on Instruction Fetch Cycle

1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit in the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the condition is specified to be occur after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDRA or BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 7.3.1, Flow of the User Break Operation.

7.3.3 Break on Data Access Cycle

1. If the L bus is specified as a break cond ition for data access break, condition comparison is performed for the address (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 7.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.2.

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 136 of 758 REJ09B0243-0300 Table 7.2 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register (BBRA or BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data mask register (BDMRA or BDMRB). When word or byte is set, bits 31 to 16 of BDRA or BDRB and BDMRA or BDMRB are ignored. 4. If the L bus is selected, a break occurs on en ding execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the break will occur cannot be determined. When this kind of break occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination.

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7.3.4 Sequential Break

1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0 and clear also the condition match flag to 0 in channel A. 2. In sequential break specification, the L or I bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched.

7.3.5 Value of Saved Program Counter

When a break occurs, the address of the instruction from where execution is to be resumed is saved in the stack, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the stack. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However, when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the stack. 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the stack.

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 138 of 758 REJ09B0243-0300 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the stack. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the stack. If the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the stack.

7.3.6 PC Trace

1. Setting PCTE in BRCR to 1 enables PC traces. Wh en branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch.  If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR.  If a branch occurs due to an interrupt or exception, the value saved in stack due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. 3. BRSR and BRDR have four pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid.

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7.3.7 Usage Examples

Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1)

• Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000404, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (after in struction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2)
• Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 140 of 758 REJ09B0243-0300 <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. (Example 1-3)

• Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00027128, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word <Channel B> Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. (Example 1-4)
• Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 141 of 758 REJ09B0243-0300 <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. (Example 1-5)

• Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000500, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) <Channel B> Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword On channel A, a user break occurs after the instruction of address H'00000500 is executed four times and before the fifth time. On channel B, a user break occurs before an instruction of address H'00001000 is executed. (Example 1-6)
• Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00008404, Address mask: H'00000FFF Data: H'00000000, Data mask: H'00000000

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 142 of 758 REJ09B0243-0300 Bus cycle: L bus/instruction fetch (after in struction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. Break Condition Specified for L Bus Data Access Cycle: (Example 2-1)

• Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00123456, Address mask: H'00000000 Data: H'12345678, Da ta mask: H'FFFFFFFF Bus cycle: L bus/data access/read (operand size is not included in the condition) <Channel B> Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 143 of 758 REJ09B0243-0300 Break Condition Specified for I Bus Data Access Cycle: (Example 3-1)

• Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00314154, Address mask: H'00000000 Data: H'12345678, Da ta mask: H'FFFFFFFF Bus cycle: I bus (CPU cycle)/instruction fetc h/read (operand size is not included in the condition) <Channel B> Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus (CPU cycle)/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314154 in the external memory space. On channel B, a user break occurs when byte data H'7x is written in address H'00055555 in the external memory space by the CPU.

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7.4 Usage Notes

1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception with higher priority occurs, the user break is not generated.  Pre-execution break has the highest priority.  When a post-execution break or data access break occurs simultaneously with a re- execution-type exception (including pre-execution break) that has higher priority, the re- execution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended.  When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a break does not occur, the condition match flag is set. 5. Note the following ex ception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the break. Note that the UBC condition match flag is set in this case. 6. Note the following when a break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed.

Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 145 of 758 REJ09B0243-0300 8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction.

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Section 8 Bus State Controller (BSC) Rev. 3.00 Sep. 27, 2007 Page 147 of 758 REJ09B0243-0300 Section 8 Bus State Controller (BSC) The bus state controller (BSC) controls data transmission and reception between the internal buses (L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, on- chip RAM, and on-chip peripheral I/O.

8.1 Features

• On-chip FLASH and RAM interface  32-bit data access per one clock cycle (I φ synchronous)

8.2 Address Map

The address map is listed in table 8.1. Table 8.1 Address Map Size Address Type of Memory

128 Kbytes

64 Kbytes

32 Kbytes

H'00000000 to H'00007FFF 32 Kbytes H'00008000 to H'0000FFFF H'00010000 to H'0001FFFF On-chip FLASH 128 Kbytes Reserved Reserved H'00020000 to H'83FFFFFF Reserved     H'84000000 to H'84007FFF 32 Kbytes H'84008000 to H'8400FFFF H'84010000 to H'8401FFFF On-chip FLASH programming area H'84020000 to H'FFFF9FFF Reserved     H'FFFFA000 to H'FFFFBFFF On-chip RAM 8 Kbytes 8 Kbytes 8 Kbytes 32 H'FFFFC000 to H'FFFFFFFF On-chip peripheral I/O    8/16

8.3 Access to on-chip FLASH and on-chip RAM

Access to the on-chip FLASH for read is synchronized with I φ clock and is executed in one clock cycle. For details on programming and erasing, see section 17, Flash Memory.

Section 8 Bus State Controller (BSC) Rev. 3.00 Sep. 27, 2007 Page 148 of 758 REJ09B0243-0300 Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one clock cycle. For details, see section 18, RAM.

8.4 Access to on-chip Peripheral I/O Register

The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in table 8.2. Table 8.2 Connection Bus Width of on-chip Peripheral Module and the Number of Access Cycles On-chip Peripheral Module INTC UBC MTU2 POE2 WDT SCI ADC CMT PFC, Port Connection Bus Width 16 16 16 16 16 8 16 16 16 Write (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk Number of Access Cycles Read (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk + 2 × Iclk Note: When m = 0 to 3, Bclk:Pclk = 4:1 When n = 0 to 3, lclk:Bclk = 4:1 When m = 0, 1, Bclk:Pclk = 2:1 When n = 0, 1, lclk:Bclk = 2:1 When m = 0, Bclk:Pclk = 1:1 When n = 0, lclk:Bclk = 1:1 This LSI adopts synchronous logic, and data of each bus is input and output in synchronization with the rising edge of the corresponding clock. The L bus access takes one Iclk cycle, I bus access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer to the I bus is a period of 3 Iclk cycles. Figure 8.1 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk = 4:1:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk. Since there are four Iclk cycles in a single Bclk cycle when Iclk:Bclk = 4:1, data can be output onto the L bus in four possible timings within one Bclk cycle. Accordingly, a maximum of four Iclk cycles of period (four Iclk cycles in the example shown in the figure) is required before the rising edge of Bclk, on which data is transferred from the L bus to the I bus. Because of this, data is transferred from the L bus to the I bus in a period of (3 + n) × Iclk (n = 0 to 3) when Iclk:Bclk = 4:1. The relation of the timing of data output to the L bus and the rising edge of Bclk depends on the state of program execution. In the case shown in figure 8.1, where Bclk = Pclk = 1:1, the period required for access by the CPU is (3 + n) × Iclk + 1 × Bclk + 2 × Pclk.

Section 8 Bus State Controller (BSC) Rev. 3.00 Sep. 27, 2007 Page 150 of 758 REJ09B0243-0300 period is required because Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where n = 0 and m = 1, the period required for access by the CPU is 3 × Iclk + 2 × Bclk + 2 × Pclk + 2 × Iclk. Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.3 Timing of Read Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:2:1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TIMMTU1A_020020030800 Rev. 3.00 Sep. 27, 2007 Page 151 of 758 REJ09B0243-0300 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels.

9.1 Features

• Maximum 16 (SH7125) or 12 (SH7124) pulse input/output lines and three pulse input lines
• Selection of eight counter input clocks for each channel (four clocks for channel 5)
• The following operations can be set for channels 0 to 4:  Waveform output at compare match  Input capture function  Counter clear operation  Multiple timer counters (TCNT) can be written to simultaneously  Simultaneous clearing by compare match and input capture is possible  Register simultaneous input/output is possible by synchronous counter operation  A maximum 12-phase PWM output is possible in combination with synchronous operation
• Buffer operation settable for channels 0, 3, and 4
• Phase counting mode settable independently for each of channels 1 and 2
• Cascade connection operation
• Fast access via internal 16-bit bus
• 28 interrupt sources
• Automatic transfer of register data
• A/D converter start trigger can be generated
• Module standby mode can be settable
• A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible.
• AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible.
• Dead time compensation counter available in channel 5
• In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 152 of 758 REJ09B0243-0300 Table 9.1 MTU2 Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock MP φ/1 MPφ/4 MPφ/16 MPφ/64 TCLKA TCLKB TCLKC TCLKD MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/1024 TCLKA TCLKB TCLKC MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MPφ/64 General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRU_5 TGRV_5 TGRW_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0 — — TGRC_3 TGRD_3 TGRC_4 TGRD_4 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A* TIOC1B* TIOC2A* TIOC2B* TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input pins TIC5U TIC5V TIC5W Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare match output Toggle output Input capture function Synchronous operation Complementary PWM mode AC synchronous motor drive mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 153 of 758 REJ09B0243-0300 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Phase counting mode Dead time compensation counter function A/D converter start trigger TGRA_0 compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complemen- tary PWM mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 154 of 758 REJ09B0243-0300 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Interrupt sources 7 sources

• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match 0E
• Compare match 0F
• Overflow 4 sources
• Compare match or input capture 1A*
• Compare match or input capture 1B*
• Overflow
• Underflow 4 sources
• Compare match or input capture 2A*
• Compare match or input capture 2B*
• Overflow
• Underflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Overflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Overflow or underflow 3 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 155 of 758 REJ09B0243-0300 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 A/D converter start request delaying function converter start request at a match between TADCOR A_4 and TCNT_4

• A/D converter start request at a match between TADCOR B_4 and TCNT_4 Interrupt skipping function — — — • Skips TGRA_3 compare match interrupts
• Skips TCIV_4 interrupts [Legend] √: Possible —: Not possible Notes: 1. This pin is supported only by the SH7125. 2. Input capture is supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 157 of 758 REJ09B0243-0300

9.2 Input/Output Pins

Table 9.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input)

0 TIOC0A I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOC0B I/O TGRB_0 input capture input/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture input/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOC1A * I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOC1B * I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOC2A * I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOC2B * I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOC3A I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOC3B I/O TGRB_3 input capture input/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture input/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOC4A I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOC4B I/O TGRB_4 input capture input/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture input/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture input/output compare output/PWM output pin

5 TIC5U Input TGRU_5 input capture input/external pulse input pin

TIC5V Input TGRV_5 input capture input/external pulse input pin TIC5W Input TGRW_5 input capture input/external pulse input pin Note: * Supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 158 of 758 REJ09B0243-0300

9.3 Register Descriptions

The MTU2 has the following registers. For details on register addresses and register states during each process, see section 20, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 9.3 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size Timer control register_3 TCR_3 R/W H'00 H'FFFFC200 8, 16, 32 Timer control register_4 TCR_4 R/W H'00 H'FFFFC201 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFFC202 8, 16 Timer mode register_4 TMDR_4 R/W H'00 H'FFFFC203 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFFC204 8, 16, 32 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFFC205 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFFC206 8, 16 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFFC207 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFFC208 8, 16 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFFC209 8 Timer output master enable register TOER R/W H'C0 H'FFFFC20A 8 Timer gate control register TGCR R/W H'80 H'FFFFC20D 8 Timer output control register 1 TOCR1 R/W H'00 H'FFFFC20E 8, 16 Timer output control register 2 TOCR2 R/W H'00 H'FFFFC20F 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFFC210 16, 32 Timer counter_4 TCNT_4 R/W H'0000 H'FFFFC212 16 Timer cycle data register TCDR R/W H'FFFF H'FFFFC214 16, 32 Timer dead time data register TDDR R/W H'FFFF H'FFFFC216 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFFC218 16, 32 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFFC21A 16 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFFC21C 16, 32 Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFFC21E 16

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 159 of 758 REJ09B0243-0300 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer subcounter TCNTS R H'0000 H'FFFFC220 16, 32 Timer cycle buffer register TCBR R/W H'FFFF H'FFFFC222 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 R/W H'FFFF H'FFFFC226 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFFC228 16, 32 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFFC22A 16 Timer status register_3 TSR_3 R/W H'C0 H'FFFFC22C 8, 16 Timer status register_4 TSR_4 R/W H'C0 H'FFFFC22D 8 Timer interrupt skipping set register TITCR R/W H'00 H'FFFFC230 8, 16 Timer interrupt skipping counter TITCNT R H'00 H'FFFFC231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFFC232 8 Timer dead time enable register TDER R/W H'01 H'FFFFC234 8 Timer output level buffer register TOLBR R/W H'00 H'FFFFC236 8 Timer buffer operation transfer mode register_3 TBTM_3 R/W H'00 H'FFFFC238 8, 16 Timer buffer operation transfer mode register_4 TBTM_4 R/W H'00 H'FFFFC239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFFC240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFFC244 16, 32 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFFC246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFFC248 16, 32 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFFC24A 16

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 160 of 758 REJ09B0243-0300 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer waveform control register TWCR R/W H'00 H'FFFFC260 8 Timer start register TSTR R/W H'00 H'FFFFC280 8, 16 Timer synchronous register TSYR R/W H'00 H'FFFFC281 8 Timer counter synchronous start register TCSYSTR R/W H'00 H'FFFFC282 8 Timer read/write enable register TRWER R/W H'01 H'FFFFC284 8 Timer control register_0 TCR_0 R/W H'00 H'FFFFC300 8, 16, 32 Timer mode register_0 TMDR_0 R/W H'00 H'FFFFC301 8 Timer I/O control register H_0 TIORH_0 R/W H'00 H'FFFFC302 8, 16 Timer I/O control register L_0 TIORL_0 R/W H'00 H'FFFFC303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFFC304 8, 16, 32 Timer status register_0 TSR_0 R/W H'C0 H'FFFFC305 8 Timer counter_0 TCNT_0 R/W H'0000 H'FFFFC306 16 Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFFC308 16, 32 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFFC30A 16 Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFFC30C 16, 32 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFFC30E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFFC320 16, 32 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFFC322 16 Timer interrupt enable register 2_0 TIER2_0 R/W H'00 H'FFFFC324 8, 16 Timer status register 2_0 TSR2_0 R/W H'C0 H'FFFFC325 8 Timer buffer operation transfer mode register_0 TBTM_0 R/W H'00 H'FFFFC326 8 Timer control register_1 TCR_1 R/W H'00 H'FFFFC380 8, 16 Timer mode register_1 TMDR_1 R/W H'00 H'FFFFC381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFFC382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFFC384 8, 16, 32 Timer status register_1 TSR_1 R/W H'C0 H'FFFFC385 8

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 161 of 758 REJ09B0243-0300 Register Name Abbrevia- tion R/W Initial value Address Access Size Timer counter_1 TCNT_1 R/W H'0000 H'FFFFC386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFFC38A 16 Timer input capture control register TICCR R/W H'00 H'FFFFC390 8 Timer control register_2 TCR_2 R/W H'00 H'FFFFC400 8, 16 Timer mode register_2 TMDR_2 R/W H'00 H'FFFFC401 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFFC402 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFFC404 8, 16, 32 Timer status register_2 TSR_2 R/W H'C0 H'FFFFC405 8 Timer counter_2 TCNT_2 R/W H'0000 H'FFFFC406 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFFC408 16, 32 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFFC40A 16 Timer counter U_5 TCNTU_5 R/W H'0000 H'FFFFC480 16, 32 Timer general register U_5 TGRU_5 R/W H'FFFF H'FFFFC482 16 Timer control register U_5 TCRU_5 R/W H'00 H'FFFFC484 8 Timer I/O control register U_5 TIORU_5 R/W H'00 H'FFFFC486 8 Timer counter V_5 TCNTV_5 R/W H'0000 H'FFFFC490 16, 32 Timer general register V_5 TGRV_5 R/W H'FFFF H'FFFFC492 16 Timer control register V_5 TCRV_5 R/W H'00 H'FFFFC494 8 Timer I/O control register V_5 TIORV_5 R/W H'00 H'FFFFC496 8 Timer counter W_5 TCNTW_5 R/W H'0000 H'FFFFC4A0 16, 32 Timer general register W_5 TGRW_5 R/W H'FFFF H'FFFFC4A2 16 Timer control register W_5 TCRW_5 R/W H'00 H'FFFFC4A4 8 Timer I/O control register W_5 TIORW_5 R/W H'00 H'FFFFC4A6 8 Timer status register_5 TSR_5 R/W H'00 H'FFFFC4B0 8 Timer interrupt enable register_5 TIER_5 R/W H'00 H'FFFFC4B2 8 Timer start register_5 TSTR_5 R/W H'00 H'FFFFC4B4 8 Timer compare match clear register TCNTCMPCLR R/W H'00 H'FFFFC4B6 8

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 162 of 758 REJ09B0243-0300

9.3.1 Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W CCLR[2:0] CKEG[1:0] TPSC[2:0] Bit Bit Name Initial Value R/W Description 7 to 5 CCLR[2:0] 000 R/W Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 9.4 and 9.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. MPφ/4 both edges = MPφ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is MPφ/4 or slower. When MPφ/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 9.6 to 9.10 for details. [Legend] x: Don't care

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 163 of 758 REJ09B0243-0300 Table 9.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 0, 3, 4 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture* 1 0 TCNT cleared by TGRD compare match/input capture* channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 9.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 1, 2 0 0 0 TCNT clearing disabled 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 164 of 758 REJ09B0243-0300 Table 9.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 0 0 0 0 Internal clock: counts on MP φ/1

1 Internal clock: counts on MP φ/4

1 0 Internal clock: counts on MP φ/16

1 Internal clock: counts on MP φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Table 9.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 1 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on MP φ/256

1 Counts on TCNT_2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 165 of 758 REJ09B0243-0300 Table 9.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 2 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on MP φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode. Table 9.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 3, 4 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 Internal clock: counts on MP φ/256 1 0 External clock: counts on TCLKA pin input

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 166 of 758 REJ09B0243-0300 Table 9.10 TPSC1 and TPSC0 (Channel 5) Channel Bit 1 TPSC1 Bit 0 TPSC0 5 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0.

9.3.2 Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 - R/W R/W R/W R/W R/W R/W R/W - BFE BFB BFA MD[3:0] Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0. The write value should always be 0.

6 BFE 0 R/W Buffer Operation E

Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. When TGRF is used as a buffer register, TGRF compare match is generated. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 167 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 9.11 for details.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 168 of 758 REJ09B0243-0300 Table 9.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0

1 Setting prohibited

1 PWM mode 2 *

1 0 0 Phase counting mode 1 *

1 Phase counting mode 2 *

1 0 Phase counting mode 3 *

1 Phase counting mode 4 *

1 0 0 0 Reset synchronous PWM mode *

1 Complementary PWM mode 1 (transmit at crest) *

1 0 Complementary PWM mode 2 (transmit at trough) *

1 Complementary PWM mode 2 (transmit at crest and

trough)* [Legend] x: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode and complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 169 of 758 REJ09B0243-0300

9.3.3 Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR is set when the setting of TMDR is in normal operation, PWM mode, and phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOB[3:0] IOA[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: Table 9.12 TIOR_1: Table 9.14 TIOR_2: Table 9.15 TIORH_3: Table 9.16 TIORH_4: Table 9.18 3 to 0 IOA[3:0] 0000 R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: Table 9.20 TIOR_1: Table 9.22 TIOR_2: Table 9.23 TIORH_3: Table 9.24 TIORH_4: Table 9.26

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 170 of 758 REJ09B0243-0300

• TIORL_0, TIORL_3, TIORL_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOD[3:0] IOC[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 9.13 TIORL_3: Table 9.17 TIORL_4: Table 9.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 9.21 TIORL_3: Table 9.25 TIORL_4: Table 9.27
• TIORU_5, TIORV_5, TIORW_5 Bit name: Initial value: R/W: 7654321 0 00000000 R R R R/W R/W R/W R/W R/W - - - IOC[4:0] Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 9.28.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 171 of 758 REJ09B0243-0300 Table 9.12 TIORH_0 (Channel 0) TGRB_0 Function TIOC0B Pin Function

0 Output retained * 0

1 Initial output is 0

0 Initial output is 0

Toggle output at compare match 0 0 Output retained

1 Initial output is 1

0 Initial output is 1

Toggle output at compare match

0 Input capture at rising edge 0

1 Input capture at falling edge

1 x Input capture at both edges 1 x x Input capture register Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 172 of 758 REJ09B0243-0300 Table 9.13 TIORL_0 (Channel 0) TGRD_0 Function TIOC0D Pin Function 0 0 0 0 Output retained * register* Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 x Input capture at both edges 1 x x Input capture register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 173 of 758 REJ09B0243-0300 Table 9.14 TIOR_1 (Channel 1) TGRB_1 Function TIOC1B Pin Function* 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 x Input capture at both edges 1 x x Input capture register Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC1B pin input/output function is supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 174 of 758 REJ09B0243-0300 Table 9.15 TIOR_2 (Channel 2) TGRB_2 Function TIOC2B Pin Function* 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC2B pin input/output function is supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 175 of 758 REJ09B0243-0300 Table 9.16 TIORH_3 (Channel 3) TGRB_3 Function TIOC3B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 176 of 758 REJ09B0243-0300 Table 9.17 TIORL_3 (Channel 3) TGRD_3 Function TIOC3D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge register* Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 177 of 758 REJ09B0243-0300 Table 9.18 TIORH_4 (Channel 4) TGRB_4 Function TIOC4B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 178 of 758 REJ09B0243-0300 Table 9.19 TIORL_4 (Channel 4) TGRD_4 Function TIOC4D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge register* Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 179 of 758 REJ09B0243-0300 Table 9.20 TIORH_0 (Channel 0) TGRA_0 Function TIOC0A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 x Input capture at both edges 1 x x Input capture register Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 180 of 758 REJ09B0243-0300 Table 9.21 TIORL_0 (Channel 0) TGRC_0 Function TIOC0C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 x Input capture at both edges 1 x x Input capture register* Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 181 of 758 REJ09B0243-0300 Table 9.22 TIOR_1 (Channel 1) TGRA_1 Function TIOC1A Pin Function* 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 x Input capture at both edges 1 x x Input capture register Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC1A pin input/output function is supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 182 of 758 REJ09B0243-0300 Table 9.23 TIOR_2 (Channel 2) TGRA_2 Function TIOC2A Pin Function* 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC2A pin input/output function is supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 183 of 758 REJ09B0243-0300 Table 9.24 TIORH_3 (Channel 3) TGRA_3 Function TIOC3A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 184 of 758 REJ09B0243-0300 Table 9.25 TIORL_3 (Channel 3) TGRC_3 Function TIOC3C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge register* Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 185 of 758 REJ09B0243-0300 Table 9.26 TIORH_4 (Channel 4) TGRA_4 Function TIOC4A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 186 of 758 REJ09B0243-0300 Table 9.27 TIORL_4 (Channel 4) TGRC_4 Function TIOC4C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge register* Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 187 of 758 REJ09B0243-0300 Table 9.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function 0 0 0 0 0 Compare match 1 0 0 0 0 Setting prohibited

1 Input capture at rising edge

1 0 Input capture at falling edge

1 Input capture at both edges

1 0 0 0 Setting prohibited

1 Measurement of low pulse width of external input signal

Capture at trough in complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest in complementary PWM mode Capture at crest and trough in complementary PWM mode 1 0 0 Setting prohibited

1 Measurement of high pulse width of external input

Capture at trough in complementary PWM mode 1 0 Measurement of high pulse width of external input signal Capture at crest in complementary PWM mode Input capture register Measurement of high pulse width of external input signal Capture at crest and trough in complementary PWM mode [Legend] x: Don't care

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 188 of 758 REJ09B0243-0300

9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR)

TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- CMP CLR5U CMP CLR5V CMP CLR5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMPCLR5U 0 R/W TCNT Compare Clear 5U

Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture

1 CMPCLR5V 0 R/W TCNT Compare Clear 5V

Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 189 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 CMPCLR5W 0 R/W TCNT Compare Clear 5W

Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture

9.3.5 Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5.

• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 76543210Bit: Initial value: R/W: 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Bit Bit Name Initial Value R/W Description

7 TTGE 0 R/W A/D Converter Start Request Enable

Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 190 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

6 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 191 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 192 of 758 REJ09B0243-0300

• TIER2_0 Bit: Initial value: R/W: 7654321 0 00000000 R/W R R R R R R/W R/W TTGE2 - - - - - TGIEF TGIEE Bit Bit Name Initial Value R/W Description

7 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGIEF 0 R/W TGR Interrupt Enable F

Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled

0 TGIEE 0 R/W TGR Interrupt Enable E

Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 193 of 758 REJ09B0243-0300

• TIER_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W - - - - - TGIE5U TGIE5V TGIE5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TGIE5U 0 R/W TGR Interrupt Enable 5U

Enables or disables interrupt requests (TGIU_5) issued when the CMFU5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled

1 TGIE5V 0 R/W TGR Interrupt Enable 5V

Enables or disables interrupt requests (TGIV_5) issued when the CMFV5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled

0 TGIE5W 0 R/W TGR Interrupt Enable 5W

Enables or disables interrupt requests (TGIW_5) issued when the CMFW5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 194 of 758 REJ09B0243-0300

9.3.6 Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.

• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 7654321 0 11000000 RR R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1. TCFD - TCFU TCFV TGFD TGFC TGFB TGFA Bit Bit Name Initial Value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

5 TCFU 0 R/(W) *

Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Setting condition]

• When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1*

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 195 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

4 TCFV 0 R/(W) *

Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition]

• When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. [Clearing condition]
• When 0 is written to TCFV after reading TCFV =

3 TGFD 0 R/(W) *

Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions]

• When TCNT = TGRD and TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing condition]
• When 0 is written to TGFD after reading TGFD =

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 196 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

2 TGFC 0 R/(W) *

Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions]

• When TCNT = TGRC and TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing condition]
• When 0 is written to TGFC after reading TGFC =

1 TGFB 0 R/(W) *

Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions]

• When TCNT = TGRB and TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing condition]
• When 0 is written to TGFB after reading TGFB =

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 197 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 TGFA 0 R/(W) *

Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions]

• When TCNT = TGRA and TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing condition]
• When 0 is written to TGFA after reading TGFA = Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 198 of 758 REJ09B0243-0300

• TSR2_0 Bit: Initial value: R/W: 7654321 0 11000000 RRRRRR R/(W)*1 R/(W)*1 Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1. - - - - - - TGFF TGFE Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGFF 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Setting condition]

• When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register [Clearing condition]
• When 0 is written to TGFF after reading TGFF =

0 TGFE 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Setting condition]

• When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register [Clearing condition]
• When 0 is written to TGFE after reading TGFE = Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it.

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• TSR_5 Bit: Initial value: R/W: 7654321 0 00000000 RRRRR R/(W)*1 R/(W)*1 R/(W)*1 Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1. - - - - - CMFU5 CMFV5 CMFW5 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMFU5 0 R/(W) *

Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Setting conditions]

• When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register
• When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register U_5 (TIORU_5)* [Clearing condition]
• When 0 is written to CMFU5 after reading CMFU5 = 1

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 200 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

1 CMFV5 0 R/(W) *

Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions]

• When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register
• When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register V_5 (TIORV_5)* [Clearing condition]
• When 0 is written to CMFV5 after reading CMFV5 = 1

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 201 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 CMFW5 0 R/(W) *

Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions]

• When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register
• When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register W_5 (TIORW_5)* [Clearing condition]
• When 0 is written to CMFW5 after reading CMFW5 = Notes: 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. The transfer timing is specified by the IOC bit in the timer I/O control register U_5/V_5/W_5 (TIORU_5, TIORV_5, TIORW_5).

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 202 of 758 REJ09B0243-0300

9.3.7 Timer Buffer Operation Tr ansfer Mode Register (TBTM)

The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- TTSE TTSB TTSA Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TTSE 0 R/W Timing Select E

Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared

1 TTSB 0 R/W Timing Select B

Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 203 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 TTSA 0 R/W Timing Select A

Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel

9.3.8 Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R/W R/W R/W R/W - - - - I2BE I2AE I1BE I1AE Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 I2BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 204 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

2 I2AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions

1 I1BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions

0 I1AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions Note: This function is supported only by the SH7125. In the SH7124, write value should always be H'00.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 205 of 758 REJ09B0243-0300

9.3.9 Timer A/D Converter Start Request Control Register (TADCR)

TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 000000000 0 * 00 * 0* 0* 0* 0* R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Note: Do not set to 1 when complementary PWM mode is not selected.* BF[1:0] - - - - - - UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 9.29. 13 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 UT4AE 0 R/W Up-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation

6 DT4AE 0 * R/W Down-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation

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5 UT4BE 0 R/W Up-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation

4 DT4BE 0 * R/W Down-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation

3 ITA3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

2 ITA4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping

1 ITB3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 207 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 ITB4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 9.29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.* 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.* 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected.

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9.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and

TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4

and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

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9.3.12 Timer Counter (TCNT)

The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.

9.3.13 Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF .

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9.3.14 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

• TSTR Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W CST4 CST3 - - - CST2 CST1 CST0 Bit Bit Name Initial Value R/W Description

7 CST4 0 R/W

6 CST3 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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2 CST2 0 R/W

1 CST1 0 R/W

0 CST0 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation

• TSTR_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W - - - - - CSTU5 CSTV5 CSTW5 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CSTU5 0 R/W Counter Start U5

Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation

1 CSTV5 0 R/W Counter Start V5

Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation

0 CSTW5 0 R/W Counter Start W5

Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 212 of 758 REJ09B0243-0300

9.3.15 Timer Synchronous Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W SYNC4 SYNC3 - - - SYNC2 SYNC1 SYNC0 Bit Bit Name Initial Value R/W Description

7 SYNC4 0 R/W

6 SYNC3 0 R/W

Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 213 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

2 SYNC2 0 R/W

1 SYNC1 0 R/W

0 SYNC0 0 R/W

Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible

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9.3.16 Timer Counter Synchronous Start Register (TCSYSTR)

TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 counters. Bit: Initial value: R/W: 7654321 0 00000000 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RRR Note: Only 1 can be written to set the register.* SCH0 SCH1 SCH2 SCH3 SCH4 - - - Bit Bit Name Initial Value R/W Description

7 SCH0 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition]

• When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1

6 SCH1 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition]

• When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 215 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

5 SCH2 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition]

• When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1

4 SCH3 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition]

• When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1

3 SCH4 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition]

• When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1 2 to 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * Only 1 can be written to set the register.

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9.3.17 Timer Read/Write Enable Register (TRWER)

TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / W Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 RWE 1 R/W Read/Write Enable

Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition]

• When 0 is written to the RWE bit after reading RWE = 1
• Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT_4.

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9.3.18 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of channel 3 and channel 4 prior to setting TIOR of channel 3 and channel 4. Bit: Initial value: R/W: 7654321 0 11000000 R R R/W R/W R/W R/W R/W R/W - - OE4D OE4C OE3D OE4B OE4A OE3B Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1.

5 OE4D 0 R/W Master Enable TIOC4D

This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

4 OE4C 0 R/W Master Enable TIOC4C

This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

3 OE3D 0 R/W Master Enable TIOC3D

This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

2 OE4B 0 R/W Master Enable TIOC4B

This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

1 OE4A 0 R/W Master Enable TIOC4A

This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 218 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 OE3B 0 R/W Master Enable TIOC3B

This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 9.3.19, Timer Output Control Register 1 (TOCR1), and section 9.3.20, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or reset- synchronized PWM mode. When these bits are set to 0, low level is output.

9.3.19 Timer Output Control Register 1 (TOCR1)

TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7654321 0 00000000 R R/W R R R/(W) * R/W R/W R/W Note: This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.* - PSYE - - TOCL TOCS OLSN OLSP Bit Bit Name Initial value R/W Description 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 PSYE 0 R/W PWM Synchronous Output Enable

This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 219 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

3 TOCL 0 R/(W) *

TOC Register Write Protection* This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled

2 TOCS 0 R/W TOC Select

This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected

1 OLSN 0 R/W Output Level Select N *

This bit selects the reverse phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 9.30.

0 OLSP 0 R/W Output Level Select P *

This bit selects the positive phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 9.31. Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be written to the bit. 2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 3. Clearing the TOCS bit to 0 makes this bit setting valid. Table 9.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count

0 High level Low level High level Low level

1 Low level High level Low level High level

Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 220 of 758 REJ09B0243-0300 Table 9.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count

0 High level Low level Low level High level

1 Low level High level High level Low level

Figure 9.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1 and OLSP = 1. TCNT_3 and TCNT_4 values TGRA_3 TGRA_4 TDDR H'0000 Time TCNT_4 TCNT_3 Positive phase output Reverse phase output Active level Compare match output (up count) Initial output Initial output Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 9.2 Complementary PWM Mode Output Level Example

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 221 of 758 REJ09B0243-0300

9.3.20 Timer Output Control Register 2 (TOCR2)

TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 9.32.

5 OLS3N 0 R/W Output Level Select 3N *

This bit selects the output level on TIOC4D in reset- synchronized PWM mode/complementary PWM mode. See table 9.33.

4 OLS3P 0 R/W Output Level Select 3P *

This bit selects the output level on TIOC4B in reset- synchronized PWM mode/complementary PWM mode. See table 9.34.

3 OLS2N 0 R/W Output Level Select 2N *

This bit selects the output level on TIOC4C in reset- synchronized PWM mode/complementary PWM mode. See table 9.35.

2 OLS2P 0 R/W Output Level Select 2P *

This bit selects the output level on TIOC4A in reset- synchronized PWM mode/complementary PWM mode. See table 9.36.

1 OLS1N 0 R/W Output Level Select 1N *

This bit selects the output level on TIOC3D in reset- synchronized PWM mode/complementary PWM mode. See table 9.37.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 222 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

0 OLS1P 0 R/W Output Level Select 1P *

This bit selects the output level on TIOC3B in reset- synchronized PWM mode/complementary PWM mode. See table 9.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 9.32 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode Reset-Synchronized PWM Mode 0 0 Does not transfer data from the buffer register (TOLBR) to TOCR2. Does not transfer data from the buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Table 9.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 223 of 758 REJ09B0243-0300 Table 9.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count Down Count Table 9.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 9.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count Table 9.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 224 of 758 REJ09B0243-0300 Table 9.38 TIOC3B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count Down Count

9.3.21 Timer Output Level Buffer Register (TOLBR)

TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R R R/W R/W R/W R/W R/W R/W - - OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

5 OLS3N 0 R/W Specifies the buffer value to be transferred to the

OLS3N bit in TOCR2.

4 OLS3P 0 R/W Specifies the buffer value to be transferred to the

OLS3P bit in TOCR2.

3 OLS2N 0 R/W Specifies the buffer value to be transferred to the

OLS2N bit in TOCR2.

2 OLS2P 0 R/W Specifies the buffer value to be transferred to the

OLS2P bit in TOCR2.

1 OLS1N 0 R/W Specifies the buffer value to be transferred to the

OLS1N bit in TOCR2.

0 OLS1P 0 R/W Specifies the buffer value to be transferred to the

OLS1P bit in TOCR2.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 225 of 758 REJ09B0243-0300 Figure 9.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS Set TOCR2 Set TOLBR [1] [2] [3] [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Figure 9.3 PWM Output Level Setting Procedure in Buffer Operation

9.3.22 Timer Gate Control Register (TGCR)

TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/reset- synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 10000000 R R/W R/W R/W R/W R/W R/W R/W - BDC N P FB WF VF UF Bit Bit Name Initial value R/W Description 7 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

6 BDC 0 R/W Brushless DC Motor

This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 226 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

5 N 0 R/W Reverse Phase Output (N) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

4 P 0 R/W Positive Phase Output (P) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

3 FB 0 R/W External Feedback Signal Enable

This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings).

2 WF 0 R/W

1 VF 0 R/W

0 UF 0 R/W

Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 9.39.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 227 of 758 REJ09B0243-0300 Table 9.39 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF

1 ON OFF OFF OFF OFF ON

1 OFF ON OFF OFF OFF ON

1 0 0 OFF OFF ON OFF ON OFF

1 ON OFF OFF OFF ON OFF

1 OFF OFF OFF OFF OFF OFF

9.3.23 Timer Subcounter (TCNTS)

TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 228 of 758 REJ09B0243-0300

9.3.24 Timer Dead Time Data Register (TDDR)

TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.

9.3.25 Timer Cycle Data Register (TCDR)

TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 229 of 758 REJ09B0243-0300

9.3.26 Timer Cycle Buffer Register (TCBR)

TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.

9.3.27 Timer Interrupt Skipping Set Register (TITCR)

TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] Bit Bit Name Initial value R/W Description

7 T3AEN 0 R/W T3AEN

Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 9.40.

3 T4VEN 0 R/W T4VEN

Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 230 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 2 to 0 4VCOR[2:0] 000 R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 9.41. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT). Table 9.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 9.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 231 of 758 REJ09B0243-0300

9.3.28 Timer Interrupt Skipping Counter (TITCNT)

TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRRR - 3ACNT[2:0] - 4VCNT[2:0] Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions]

• When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR
• When the T3AEN bit in TITCR is cleared to 0
• When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 — 0 R Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions]
• When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR
• When the T4VEN bit in TITCR is cleared to 0
• When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 232 of 758 REJ09B0243-0300

9.3.29 Timer Buffer Transfer Set Register (TBTER)

TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRR R / W R / W Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 9.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 233 of 758 REJ09B0243-0300 Table 9.42 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer registers to the temporary registers * and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer registers to the temporary registers. 1 0 Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.* 1 1 Setting prohibited Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 9.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 234 of 758 REJ09B0243-0300

9.3.30 Timer Dead Time Enable Register (TDER)

TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / ( W ) Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 TDER 1 R/(W) Dead Time Enable

Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition]

• When 0 is written to TDER after reading TDER = 1 Note: * TDDR must be set to 1 or a larger value.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 235 of 758 REJ09B0243-0300

9.3.31 Timer Waveform Control Register (TWCR)

TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 Note: Do not set to 1 when complementary PWM mode is not selected.* 0* 0000000 R/(W) R R R R R R R/(W) Bit Bit Name Initial Value R/W Description

7 CCE 0 * R/(W) Compare Match Clear Enable

Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition]

• When 1 is written to CCE after reading CCE = 0 6 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 236 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 WRE 0 R/(W) Waveform Retain Enable

Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 9.40. 0: Outputs the initial value specified in TOCR 1: Retains the waveform output immediately before synchronous clearing [Setting condition]

• When 1 is written to WRE after reading WRE = 0 Note: * Do not set to 1 when complementary PWM mode is not selected.

9.3.32 Bus Master Interface

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8- bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 237 of 758 REJ09B0243-0300

9.4 Operation

9.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). Counter Operation: When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of Count Operation Setting Procedure Figure 9.4 shows an example of the count operation setting procedure. Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free-running counter Start count operation <Free-running counter> <Periodic counter> Start count operation [1] [2] [3] [4] [5] [5] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 9.4 Example of Counter Operation Setting Procedure

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 243 of 758 REJ09B0243-0300

9.4.2 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 9.12 shows an example of the synchronous operation setting procedure. No Yes Set synchronous operation <Synchronous presetting> <Counter clearing> <Synchronous clearing> Clearing source generation channel? Select counter clearing source Start count Set synchronous counter clearing Start count [1] [3] [5] [4] [5] [2] Synchronous operation selection [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Set TCNT Synchronous presetting Synchronous clearing Figure 9.12 Example of Synchronous Operation Setting Procedure

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 245 of 758 REJ09B0243-0300

9.4.3 Buffer Operation

Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 9.43 shows the register combinations used in buffer operation. Table 9.43 Register Combinations in Buffer Operation Channel Timer General Re gister Buffer Register

0 TGRA_0 TGRC_0

TGRB_0 TGRD_0 TGRE_0 TGRF_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3

4 TGRA_4 TGRC_4

TGRB_4 TGRD_4

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.14. Buffer register Timer general register TCNTComparator Compare match signal Figure 9.14 Compare Match Buffer Operation

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 249 of 758 REJ09B0243-0300 TCNT_0 value H'0000 TGRA_0 Time TIOCA TGRC_0 H'0520 H'0520 H'0450 H'0450 H'0200 H'0520H'0450H'0200 H'0200 TGRB_0 TGRA_0 Transfer Figure 9.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing

9.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 9.44 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 9.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 250 of 758 REJ09B0243-0300 Table 9.45 shows the TICCR setting and input capture input pins. Table 9.45 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins I2AE bit = 0 (initial value) TIOC1A Input capture from TCNT_1 to TGRA_1 I2AE bit = 1 TIOC1A, TIOC2A I2BE bit = 0 (initial value) TIOC1B Input capture from TCNT_1 to TGRB_1 I2BE bit = 1 TIOC1B, TIOC2B I1AE bit = 0 (initial value) TIOC2A Input capture from TCNT_2 to TGRA_2 I1AE bit = 1 TIOC2A, TIOC1A I1BE bit = 0 (initial value) TIOC2B Input capture from TCNT_2 to TGRB_2 I1BE bit = 1 TIOC2B, TIOC1B Example of Cascaded Operation Setting Procedure: Figure 9.20 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 9.20 Cascaded Operation Setting Procedure Cascaded Operation Example (a): Figure 9.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 252 of 758 REJ09B0243-0300 Cascaded Operation Example (c) in SH7125: Figure 9.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0514 H'0514 H'0513H'0512 H'0513H'0512 H'C256 H'C256 H'FFFF H'6128 H'6128 H'2064 H'2064 H'9192 H'9192 Figure 9.23 Cascaded Operation Example (c) Cascaded Operation Example (d) in SH7125: Figure 9.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 253 of 758 REJ09B0243-0300 TCNT_2 value H'0000 H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0513H'0512 H'0513 H'D000 H'FFFF H'D000 TCNT_0 value Time TGRA_0 Compare match between TCNT_0 and TGRA_0 Figure 9.24 Cascaded Operation Example (d)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 254 of 758 REJ09B0243-0300

9.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.46.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 255 of 758 REJ09B0243-0300 Table 9.46 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TGRB_0 TIOC0A TIOC0B TGRC_0 TIOC0C TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A * 1 TGRB_1 TIOC1A* TIOC1B* TGRA_2 TIOC2A * 2 TGRB_2 TIOC2A* TIOC2B* TGRA_3 Cannot be set TGRB_3 TIOC3A Cannot be set TGRC_3 Cannot be set TGRD_3 TIOC3C Cannot be set TGRA_4 Cannot be set TGRB_4 TIOC4A Cannot be set TGRC_4 Cannot be set TGRD_4 TIOC4C Cannot be set Notes: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. * Supported only by the SH7125.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 259 of 758 REJ09B0243-0300

9.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 9.47 shows the correspondence between external clock pins and channels. Table 9.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 9.29 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 9.29 Example of Phase Counting Mode Setting Procedure

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 264 of 758 REJ09B0243-0300 Phase Counting Mode Application Example: Figure 9.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 265 of 758 REJ09B0243-0300 TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed period capture) TGRA_0 (speed control period) TGRB_1 (position period capture) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 9.34 Phase Counting Mode Application Example

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 266 of 758 REJ09B0243-0300

9.4.7 Reset-Synchronized PWM Mode

In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter. Table 9.52 shows the PWM output pins used. Table 9.53 shows the settings of the registers. Table 9.52 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description

3 TIOC3B PWM output pin 1

TIOC3D PWM output pin 1' (negative-phase waveform of PWM output 1)

4 TIOC4A PWM output pin 2

TIOC4C PWM output pin 2' (negative-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negative-phase waveform of PWM output 3) Table 9.53 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 267 of 758 REJ09B0243-0300 Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 9.35 shows an example of procedure for selecting the reset synchronized PWM mode. Stop counting Select counter clock and counter clear source Set TGR Reset-synchronized PWM mode Brushless DC motor control setting Set TCNT Enable waveform output Set reset-synchronized PWM mode PWM cycle output enabling, PWM output level setting Start count operation Reset-synchronized PWM mode [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. [2] Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X ≤ TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR2, see figure 9.3. [7] Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] PFC setting [9] [10] Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Figure 9.35 Procedure for Selecting Reset-Synchronized PWM Mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 268 of 758 REJ09B0243-0300 Reset-Synchronized PWM Mode Operation: Figure 9.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TGRA_3 TGRB_3 TGRB_4 H'0000 TGRA_4 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Time TCNT_3 and TCNT_4 values Figure 9.36 Reset-Synchronized PWM Mode Operation Example (When TOCR’s OLSN = 1 and OLSP = 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 269 of 758 REJ09B0243-0300

9.4.8 Complementary PWM Mode

In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without non- overlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 9.54 shows the PWM output pins used. Table 9.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 9.54 Output Pins for Complementary PWM Mode Channel Output Pin Description

3 TIOC3A Toggle output synchronized with PWM period (or I/O port)

TIOC3C I/O port * TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 270 of 758 REJ09B0243-0300 Table 9.55 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU

3 TCNT_3 Start of up-count from value set

setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable

4 TCNT_4 Up-count start, initialized to

H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register).

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 271 of 758 REJ09B0243-0300 TGRC_3 TDDR TCNT_3 TGRD_3 TGRD_4TGRC_4 TGRB_3 Temp 1 TGRA_4 Temp 2 TGRB_4 Temp 3 TCNTS TCNT_4 TGRA_3 TCDR TCBR Comparator Comparator Match signal Match signal Output controller Output protection circuit PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE3 External cutoff input External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) TGRA_3 compare- match interrupt TCNT_4 underflow interrupt Figure 9.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 272 of 758 REJ09B0243-0300 Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 9.38. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting TCNT setting Inter-channel synchronization setting TGR setting Enable/disable dead time generation Start count operation [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 9.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting Enable waveform output Start count operation <Complementary PWM mode> [10] PFC setting [12] [13] Figure 9.38 Example of Complementary PWM Mode Setting Procedure

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 273 of 758 REJ09B0243-0300 Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 9.39 illustrates counter operation in complementary PWM mode, and figure 9.40 shows an example of complementary PWM mode operation. 1. Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down- counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Counter value TGRA_3 TCDR TDDR H'0000 TCNT_4 TCNTS TCNT_3 TCNT_3 TCNT_4 TCNTS Time Figure 9.39 Complementary PWM Mode Counter Operation

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 274 of 758 REJ09B0243-0300 2. Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 9.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 9.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 9.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS—and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 275 of 758 REJ09B0243-0300 TGRA_3 TCDR TGRA_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS (Output waveform is active-low) H'6400 H'0080 H'6400 H'6400 H'0080 H'0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 9.40 Example of Complementary PWM Mode Operation

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 276 of 758 REJ09B0243-0300 3. Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 9.56 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 277 of 758 REJ09B0243-0300 4. PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6- phase output. Complementary PWM mode should be cleared before setting or changing output levels. 5. Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. 6. Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 9.41 shows an example of operation without dead time.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 278 of 758 REJ09B0243-0300 TGRA_3=TCDR+1 TCDR TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active-low. Data1 Data2 Data1 Data2 Data1 Data2 Transfer from temporary register to compare register Transfer from temporary register to compare register Initial output Initial output Figure 9.41 Example of Operation without Dead Time

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 279 of 758 REJ09B0243-0300 7. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 9.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TGRA_3 TCNT_3 TCNT_4 Time Figure 9.42 Example of PWM Cycle Updating

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 280 of 758 REJ09B0243-0300 8. Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 9.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 281 of 758 REJ09B0243-0300 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6Temp_R GR Time : Compare register : Buffer register Figure 9.43 Example of Data Update in Complementary PWM Mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 282 of 758 REJ09B0243-0300 9. Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 9.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 9.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Dead time Time Active level Active level TCNT_3 and TCNT_4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 9.44 Example of Initial Output in Complementary PWM Mode (1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 283 of 758 REJ09B0243-0300 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3 and TCNT_4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 9.45 Example of Initial Output in Complementary PWM Mode (2)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 284 of 758 REJ09B0243-0300 10. Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non- overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare- match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 9.46 to 9.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid- line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as shown in figure 9.46. If compare-matches deviate from the a → b → c → d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 9.47, compare- match b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 9.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 289 of 758 REJ09B0243-0300 11. Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 9.49 to 9.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn- off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. 12. Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 9.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare- match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 H'0000 Toggle output TIOC3A pin TCNT_4 TCNT_3 Figure 9.54 Example of Toggle Output Waveform Synchronized with PWM Output

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 291 of 758 REJ09B0243-0300 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 9.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 9.56) immediately after the counters start operation, initial value output is not suppressed. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing. Tb intervalTb interval Tb interval TGRA_3 TGRB_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low Counter start Figure 9.56 Timing for Synchronous Counter Clearing

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 292 of 758 REJ09B0243-0300  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 9.57. Stop count operation Output waveform control at synchronous counter clearing Set TWCR and complementary PWM mode Start count operation Output waveform control at synchronous counter clearing [1] [2] [3] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Figure 9.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 9.58 to 9.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 9.58 to 9.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 9.56, respectively.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 293 of 758 REJ09B0243-0300 TGRA_3 TGRB_3 TCDR TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Synchronous clearing TCNT_3 (MTU2) TCNT_4 (MTU2) Bit WRE = 1 Figure 9.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 9.56; Bit WRE of TWCR in MTU2 is 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 294 of 758 REJ09B0243-0300 Positive phase Negative phase Output waveform is active-low. Synchronous clearing Bit WRE = 1 TCNT_3 (MTU2) TCNT_4 (MTU2) TGRA_3 TGRB_3 TCDR TDDR H'0000 Figure 9.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 9.56; Bit WRE of TWCR in MTU2 is 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 295 of 758 REJ09B0243-0300 Positive phase Negative phase Output waveform is active-low. Synchronous clearing Bit WRE = 1 TCNT_3 (MTU2) TCNT_4 (MTU2) TGRA_3 TGRB_3 TCDR TDDR H'0000 Figure 9.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 9.56; Bit WRE of TWCR is 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 296 of 758 REJ09B0243-0300 Positive phase Negative phase Output waveform is active-low. Synchronous clearingBit WRE = 1 TGRA_3 TGRB_3 TCDR TDDR H'0000 Initial value output is suppressed. TCNT_3 (MTU2) TCNT_4 (MTU2) Figure 9.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 9.56; Bit WRE of TWCR is 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 298 of 758 REJ09B0243-0300 16. Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 9.63 to 9.66 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 9.63 Example of Output Phase Switching by External Input (1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 300 of 758 REJ09B0243-0300 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 9.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) 17. A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 304 of 758 REJ09B0243-0300 Buffer register Temporary register General register TCNT_3 TCNT_4 Data1 Data2 Data* Data2 Data* Data2 (1) (2) (3) Buffer transfer is suppressed Note: * When buffer transfer at the crest is selected. data1 Bit BTE1 in TBTER Bit BTE0 in TBTER (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. [Legend] Figure 9.70 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 305 of 758 REJ09B0243-0300 Buffer register Temporary register Compare register TCNT_3 TCNT_4 Data1 Data2 Data1 Data Data Data Data2 Data1 Data2 Buffer transfer-enabled period TITCR[6:4] TITCNT[6:4] Buffer register Temporary register Compare register TITCR[6:4] TITCNT[6:4] 01 2 0 1 TCNT_3 TCNT_4 Data1 Data1 Data Data Data Data1 Note: * Buffer transfer at the crest is selected. The skipping count is set to two. T3AEN is set to 1. Buffer transfer-enabled period 01 2 0 1 TGIA_3 interrupt occurred TGIA_3 interrupt occurred TGIA_3 interrupt occurred TGIA_3 interrupt occurred Buffer register rewriting timing Buffer register rewriting timing Buffer register rewriting timing (2) When rewriting a buffer register after a carrier cycle passed from occurring TGIA_3 interrupt. (1) When rewriting a buffer register within a carrier cycle after TGIA_3 interrupt occurred. Figure 9.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0)

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 306 of 758 REJ09B0243-0300 Note: * The skipping count is set to three. Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) 00 1230123 01230123 Skipping counter 3ACNT Skipping counter 4VCNT Figure 9.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer- Enabled Period

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 307 of 758 REJ09B0243-0300 Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. 1. Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following:  TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. 2. Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 10, Port Output Enable (POE), for details. 3. Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. See section 4.7, Function for Detecting Oscillator Stop.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 308 of 758 REJ09B0243-0300

9.4.9 A/D Converter Start Request Delaying Function

A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. 1. Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 9.73 shows an example of procedure for specifying the A/D converter start request delaying function. Set A/D converter start request cycle A/D converter start request delaying function

• Set the timing of transfer from cycle set buffer register
• Set linkage with interrupt skipping
• Enable A/D converter start request delaying function A/D converter start request delaying function [1] [2] [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register.
• Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 9.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 310 of 758 REJ09B0243-0300 Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TADCORA_4 TCNT_4 A/D converter start request (TRG4AN) Note: * When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping 00 01 00 01 02 00 01 00 01 02 (UT4AE/DT4AE = 1) Figure 9.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 311 of 758 REJ09B0243-0300 A/D converter start request (TRG4AN) Note: * When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping TADCORA_4 TCNT_4 00 01 00 01 02 00 01 00 01 02 UT4AE = 1 DT4AE = 0 Figure 9.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 312 of 758 REJ09B0243-0300

9.4.10 External Pulse Width Measurement

The pulse widths of up to three external input lines can be measured in channel 5. Example of External Pulse Width Measurement Setting Procedure: Select counter clock External pulse width measurement Select pulse width measuring conditions Start count operation <External pulse width measurement> [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. [1] [2] [3] Figure 9.77 Example of External Pulse Width Measurement Setting Procedure Example of External Pulse Width Measurement: 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 TIC5U TCNT5_U MPφ 0007 000A 000B Figure 9.78 Example of External Pulse Width Measurement (Measuring High Pulse Width)

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9.4.11 Dead Time Compensation

By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Tdelay Upper arm signal Lower arm signal Inverter output detection signal Dead time delay signal Figure 9.79 Delay in Dead Time in Complementary PWM Operation

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9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation

The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 9.82 is an operating example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). Tdead Tdelay Upper arm signal Lower arm signal Inverter output monitor signal Dead time delay signal TGRA_4 3DE7 3E5B 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF3DE7 TCNT[15:0] TGR[15:0] Up-count/down-count signal (udflg) Figure 9.82 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation

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9.5 Interrupt Sources

9.5.1 Interrupt Sou rces and Priorities

There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 9.57 lists the MTU2 interrupt sources.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 317 of 758 REJ09B0243-0300 Table 9.57 MTU2 Interrupts Channel Name Interrupt Source Interrupt Flag Priority

0 TGIA_0 TGRA_0 input capture/compare match TGFA_0 High

TGIB_0 TGRB_0 input capture/compare match TGFB_0 TGIC_0 TGRC_0 input capture/compare match TGFC_0 TGID_0 TGRD_0 input capture/compare match TGFD_0 TCIV_0 TCNT_0 overflow TCFV_0 TGIE_0 TGRE_0 compare match TGFE_0 TGIF_0 TGRF_0 compare match TGFF_0

1 TGIA_1 TGRA_1 input capture/compare match TGFA_1

TGIB_1 TGRB_1 input capture/compare match TGFB_1 TCIV_1 TCNT_1 overflow TCFV_1 TCIU_1 TCNT_1 underflow TCFU_1

2 TGIA_2 TGRA_2 input capture/compare match TGFA_2

TGIB_2 TGRB_2 input capture/compare match TGFB_2 TCIV_2 TCNT_2 overflow TCFV_2 TCIU_2 TCNT_2 underflow TCFU_2

3 TGIA_3 TGRA_3 input capture/compare match TGFA_3

TGIB_3 TGRB_3 input capture/compare match TGFB_3 TGIC_3 TGRC_3 input capture/compare match TGFC_3 TGID_3 TGRD_3 input capture/compare match TGFD_3 TCIV_3 TCNT_3 overflow TCFV_3

4 TGIA_4 TGRA_4 input capture/compare match TGFA_4

TGIB_4 TGRB_4 input capture/compare match TGFB_4 TGIC_4 TGRC_4 input capture/compare match TGFC_4 TGID_4 TGRD_4 input capture/compare match TGFD_4 TCIV_4 TCNT_4 overflow/underflow TCFV_4

5 TGIU_5 TGRU_5 input capture/compare match TGFU_5

TGIV_5 TGRV_5 input capture/compare match TGFV_5 TGIW_5 TGRW_5 input capture/compare match TGFW_5 Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 318 of 758 REJ09B0243-0300 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.

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9.5.2 A/D Converter Activation

The A/D converter can be activated by one of the following three methods in the MTU2. Table 9.58 shows the relationship between interrupt sources and A/D converter start request signals. A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode: The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions.

• When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1
• When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0: The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by A/D Converter Start Request Delaying Function: The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the TAD4AE or TAD4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 9.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 320 of 758 REJ09B0243-0300 Table 9.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 Input capture/compare match TCNT_4 TCNT_4 Trough in complementary PWM mode TRGAN TGRE_0 and TCNT_0 TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 Compare match TRG4BN

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9.6 Operation Timing

9.6.1 Input/Output Timing

TCNT Count Timing: Figures 9.83 and 9.84 show TCNT count timing in internal clock operation, and figure 9.85 shows TCNT count timing in external clock operation (normal mode), and figure 9.86 shows TCNT count timing in external clock operation (phase counting mode). TCNT TCNT input clock Internal clock MPφ Falling edge Rising edge N - 1 N N + 1 Figure 9.83 Count Timing in Internal Clock Operation (Channels 0 to 4) TCNT TCNT input clock Internal clock MPφ Rising edge N - 1 N Figure 9.84 Count Timing in Internal Clock Operation (Channel 5) MPφ TCNT TCNT input clock External clock Falling edge Rising edge N - 1 N N + 1 Figure 9.85 Count Timing in External Clock Operation (Channels 0 to 4)

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9.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figures 9.99 and 9.100 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TGR TCNT TCNT input clock N N N + 1 Compare match signal TGF flag TGI interrupt MPφ Figure 9.99 TGI Interrupt Timing (Compare Match) (Channels 0 to 4) TGR TCNT TCNT input clock N N - 1 N Compare match signal TGF flag TGI interrupt MPφ Figure 9.100 TGI Interrupt Timing (Compare Match) (Channel 5)

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9.7 Usage Notes

9.7.1 Module Standby Mode Setting

MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes.

9.7.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.107 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- enceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 9.107 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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9.7.3 Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

• Channels 0 to 4 f = MPφ (N + 1)
• Channel 5 f = MPφ N Where f: Counter frequency MP φ: MTU2 peripheral clock operating frequency N: TGR set value

9.7.4 Contention between TCNT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.108 shows the timing in this case. Counter clear signal Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N H'0000 MPφ Counter clear signal Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N H'0000 MPφ Figure 9.108 Contention between TCNT Write and Clear Operations

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9.7.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.109 shows the timing in this case. TCNT input clock Write signal Address TCNT address TCNT TCNT write cycle T1 T2 NM TCNT write data MPφ Figure 9.109 Contention between TCNT Write and Increment Operations

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9.7.6 Contention between TG R Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 9.110 shows the timing in this case. Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 NM TGR write data TGR N N + 1 MPφ Figure 9.110 Contention between TGR Write and Compare Match

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9.7.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 9.111 shows the timing in this case. Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 9.111 Contention between Buffer Register Write and Compare Match

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9.7.8 Contention between Buffer Register Write and TCNT Clear

When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 9.112 shows the timing in this case. Address Write signal TCNT clear signal Buffer transfer signal TGR write cycle T1 T2Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 9.112 Contention between Buffer Register Write and TCNT Clear

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9.7.9 Contention between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 9.113 and 9.114 show the timing in this case. Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address MPφ N NM Figure 9.113 Contention between TGR Read and Input Capture (Channels 0 to 4) Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address MPφ M NM Figure 9.114 Contention between TGR Read and Input Capture (Channel 5)

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9.7.10 Contention between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 9.115 and 9.116 show the timing in this case. Input capture signal Write signal Address TCNT TGR write cycle T1 T2 MTGR M TGR address MPφ Figure 9.115 Contention between TGR Write and Input Capture (Channels 0 to 4) Input capture signal Write signal Address TCNT TGR write cycle T1 T2 NTGR M TGR address MPφ TGR write data Figure 9.116 Contention between TGR Write and Input Capture (Channel 5)

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9.7.11 Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.117 shows the timing in this case. Input capture signal Write signal Address TCNT Buffer register write cycle T1 T2 NTGR N M MBuffer register Buffer register address MPφ Figure 9.117 Contention between Buffer Register Write and Input Capture

9.7.12 TCNT_2 Write and Overflow/Underflo w Contention in Cascade Connection

With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 9.118. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 341 of 758 REJ09B0243-0300 T1 T2 H'FFFE H'FFFF N N + 1 H'FFFF M M N P QP M Disabled TCNT_2 write data TCNT_2 address TCNT write cycle Address Write signal TCNT_2 TGRA_2 to TGRB_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D MPφ Figure 9.118 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection

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9.7.13 Counter Value during Complementary PWM Mode Stop

When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 9.119. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TDDR H'0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 9.119 Counter Value during Complementary PWM Mode Stop

9.7.14 Buffer Operation Setting in Complementary PWM Mode

In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register.

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9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 9.120 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD TGRA_3, TGRC_3 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 Buffer transfer with compare match A3TCNT3 Not set Not set Point a Point b Figure 9.120 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode

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9.7.16 Overflow Flags in Reset Synchronous PWM Mode

When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit in TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 9.121 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. TGRA_3 (H'FFFF) H'0000 TCFV_3 TCFV_4 TCNT_3 = TCNT_4 Counter cleared by compare match 3A Not set Not set Figure 9.121 Reset Synchronous PWM Mode Overflow Flag

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9.7.17 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.122 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. Counter clear signal TCNT TCNT input clock H'FFFF H'0000 TGF TCFV Disabled MPφ Figure 9.122 Contention between Overflow and Counter Clearing

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9.7.18 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.123 shows the operation timing when there is contention between TCNT write and overflow. Disabled Write signal Address TCNT address TCNT TCNT write cycle T1 T2 H'FFFF M TCNT write data TCFV flag MPφ Figure 9.123 Contention between TCNT Write and Overflow

9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-

When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset- synchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to reset- synchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode.

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9.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode

When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00.

9.7.21 Interrupts in Module Standby Mode

If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode.

9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection

When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input-capture input as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time.

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9.8 MTU2 Output Pi n Initialization

9.8.1 Operating Modes

The MTU2 has the following six operating modes. Waveform output is possible in all of these modes.

• Normal mode (channels 0 to 4)
• PWM mode 1 (channels 0 to 4)
• PWM mode 2 (channels 0 to 2)
• Phase counting modes 1 to 4 (channels 1 and 2)
• Complementary PWM mode (channels 3 and 4)
• Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section.

9.8.2 Reset Start Operation

The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 349 of 758 REJ09B0243-0300 9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 9.59. Table 9.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 350 of 758 REJ09B0243-0300

9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error

during Operation, etc.

• When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
• In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.
• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2.
• In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.
• In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.
• When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 351 of 758 REJ09B0243-0300 Pin initialization procedures are described below for the numbered combinations in table 9.59. The active level is assumed to be low. Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.124 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.124 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. After a reset, the TMDR setting is for normal mode. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 352 of 758 REJ09B0243-0300 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.125 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 High-Z High-Z Figure 9.125 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.124. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 353 of 758 REJ09B0243-0300 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.126 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.126 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 9.124. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 354 of 758 REJ09B0243-0300 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.127 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.127 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9.124. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 355 of 758 REJ09B0243-0300 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.128 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re- setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.128 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.124. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 356 of 758 REJ09B0243-0300 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.129 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.129 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 9.124. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 357 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 9.130 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 High-Z High-Z Figure 9.130 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set PWM mode 1. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 358 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.131 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (TIOC*B) n = 0 to 15 High-Z High-Z Figure 9.131 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.130. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 359 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.132 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.132 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 9.130. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 360 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.133 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 High-Z High-Z Figure 9.133 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9.130. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 361 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.134 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re- setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z Figure 9.134 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.130. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 362 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.135 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z Figure 9.135 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 9.134. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 363 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 9.136 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.136 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set PWM mode 2. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 364 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.137 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.137 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 9.136. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 365 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.138 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.138 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 9.136. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 366 of 758 REJ09B0243-0300 Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.139 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 High-Z High-Z Figure 9.139 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 9.136. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 367 of 758 REJ09B0243-0300 Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.140 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.140 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set phase counting mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 368 of 758 REJ09B0243-0300 Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.141 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 High-Z High-Z Figure 9.141 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 9.140. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 369 of 758 REJ09B0243-0300 Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.142 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 9.142 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 9.140. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 370 of 758 REJ09B0243-0300 Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.143 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.143 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 9.140. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 371 of 758 REJ09B0243-0300 Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.144 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.144 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 3. Set complementary PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The complementary PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU2 output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 372 of 758 REJ09B0243-0300 Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.145 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z Figure 9.145 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.144. 11. Set PWM mode 1. (MTU2 output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 373 of 758 REJ09B0243-0300 Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.146 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) PFC (MTU2) TSTR (1) Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.146 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 374 of 758 REJ09B0243-0300 Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.147 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.147 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 375 of 758 REJ09B0243-0300 Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.148 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.148 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 376 of 758 REJ09B0243-0300 Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.149 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.149 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 3. Set reset-synchronized PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The reset-synchronized PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) 11. Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 377 of 758 REJ09B0243-0300 Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.150 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z Figure 9.150 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.149. 11. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 378 of 758 REJ09B0243-0300 Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.151 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z Figure 9.151 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.149. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 379 of 758 REJ09B0243-0300 Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.152 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) PFC (MTU2) TSTR (1) Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High-Z High-Z High-Z High-Z High-Z High-Z Figure 9.152 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 9.149. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence.

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 380 of 758 REJ09B0243-0300

Section 10 Port Output Enable (POE) TIMMTU1A_020020030800 Rev. 3.00 Sep. 27, 2007 Page 381 of 758 REJ09B0243-0300 Section 10 Port Output Enable (POE) The port output enable (POE) can be used to place the high-current pins (pins multiplexed with TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2) and the pins for channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in high-impedance state, depending on the change on POE0, POE1, POE3*, and POE8 input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests.

10.1 Features

• Each of the POE0, POE1, POE3*, and POE8 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0, POE1, POE3*, and POE8 pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results. The POE has input level detection circuits, output level comparison circuits, and a high-impedance request/interrupt request generating circuit as shown in figure 10.1, Block Diagram of POE. In addition to control by the POE, high-current pins can be placed in high-impedance state when the oscillator stops or in software standby state. For details, refer to appendix A, Pin States. Note: * The POE3 pin is supported only by the SH7125.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 383 of 758 REJ09B0243-0300

10.2 Input/Output Pins

Table 10.1 Pin Configuration Name Abbreviation I/O Description Port output enable input pins 0, 1, 3 POE0, POE1, POE3* Input Input request signals to place high- current pins for MTU2 in high- impedance state* Port output enable input pin 8 POE8 Input Inputs a request signal to place pins for channel 0 in MTU2 in high- impedance state* Note: * When the POE3 function is selected in the PFC, the pin is pulled up inside the LSI if nothing is input to it. The POE3 pin is supported only by the SH7125. Table 10.2 shows output-level comparisons with pin combinations. Table 10.2 Pin Combinations Pin Combination I/O Description PE9/TIOC3B and PE11/TIOC3D PE12/TIOC4A and PE14/TIOC4C PE13/TIOC4B and PE15/TIOC4D Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level (low level when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2 is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (Pφ). This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and high- impedance control can be selected by POE registers.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 384 of 758 REJ09B0243-0300

10.3 Register Descriptions

The POE has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 10.3 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Input level control/status register 1 ICSR1 R/W H'0000 H'FFFFD000 8, 16, 32 Output level control/status register 1 OCSR1 R/W H'0000 H'FFFFD002 8, 16 Input level control/status register 3 ICSR3 R/W H'0000 H'FFFFD008 8, 16, 32 Software port output enable register SPOER R/W H'00 H'FFFFD00A 8 Port output enable control register 1 POECR1 R/W H'00 H'FFFFD00B 8 Port output enable control register 2 POECR2 R/W H'7700 H'FFFFD00C 8, 16

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 385 of 758 REJ09B0243-0300

10.3.1 Input Level Control/Status Register 1 (ICSR1)

ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 RRR R / W R / W *2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. POE3F - POE1F POE0F - - - PIE1 POE3M[1:0] POE1M[1:0] POE0M[1:0] Bit Bit Name Initial value R/W Description

15 POE3F 0 R/(W) *

(Supported only by the SH7125.) This flag indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions]

• By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1)
• By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin 14  0 R/(W) * Reserved This bit is always read as 0. The write value should always be 0.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 386 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

13 POE1F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions]

• By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1)
• By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin

12 POE0F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE0 pin. [Clearing conditions]

• By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1)
• By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 387 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

8 PIE1 0 R/W Port Interrupt Enable 1

This bit enables/disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W * POE3 mode 1, 0 (Supported only by the SH7125. Write 00 to these bits in the SH7124.) These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 5, 4  All 0 R/W * Reserved These bits are always read as 0. The write value should always be 0. 3, 2 POE1M[1:0] 00 R/W * POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 Pφ/128 clock pulses and all are low level.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 388 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 1, 0 POE0M[1:0] 00 R/W * POE0 mode 1, 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

10.3.2 Output Level Control/Status Register 1 (OCSR1)

OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W RRRRRRRR Bit: Initial value: R/W:R/(W)*1 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W Description

15 OSF1 0 R/(W) *

This flag indicates that any one of the three pairs of MTU2 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition]

• By writing 0 to OSF1 after reading OSF1 = 1 [Setting condition]
• When any one of the three pairs of 2-phase outputs has simultaneously become an active level

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 389 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 14 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 OCE1 0 R/W *

Output Short High-Impedance Enable 1 This bit specifies whether to place the pins in high- impedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 OIE1 0 R/W Output Short Interrupt Enable 1

This bit enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

10.3.3 Input Level Control/Status Register 3 (ICSR3)

ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRR R/(W)*1 RR R / W *2 R / W RRRRRR R / W *2 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. POE8F - - POE8E - - - - -- - - PIE3 - POE8M[1:0]

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 390 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 15 to 13 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

12 POE8F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions]

• By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3)·
• By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at Pf/8, Pf/16, or Pf/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) [Setting condition]
• When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 POE8E 0 R/W *

POE8 High-Impedance Enable This bit specifies whether to place the pins in high- impedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 PIE3 0 R/W Port Interrupt Enable 3

(Supported only by the SH7125. Write 0 to this bit in the SH7124.) This bit enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 391 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 POE8M[1:0] 00 R/W * POE8 mode 1 and 0 These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

10.3.4 Software Port Output Enable Register (SPOER)

SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W CH0HIZ MTU2 CH34HIZ Bit Bit Name Initial value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 — 0 R/W Reserved This bit is always read as 0. The write value should always be 0.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 392 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

1 MTU2CH0HIZ 0 R/W MTU2 Channel 0 Output High-Impedance

This bit specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH0HIZ

0 MTU2CH34HIZ 0 R/W MTU2 Channel 3 and 4 Output High-Impedance

This bit specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH34HIZ

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 393 of 758 REJ09B0243-0300

10.3.5 Port Output Enable Control Register 1 (POECR1)

POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 7654321 0 00000000 RRRR R / W * R/W* R/W* R/W* Note: Can be modified only once after a power-on reset.* ---- MTU2 PE3ZE MTU2 PE2ZE MTU2 PE1ZE MTU2 PE0ZE Bit Bit Name Initial value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 MTU2PE3ZE 0 R/W * MTU2 PE3 High-Impedance Enable

This bit specifies whether to place the PE3/TIOC1D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

2 MTU2PE2ZE 0 R/W * MTU2 PE2 High-Impedance Enable

This bit specifies whether to place the PE2/TIOC1C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

1 MTU2PE1ZE 0 R/W * MTU2 PE1 High-Impedance Enable

This bit specifies whether to place the PE1/TIOC1B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 394 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

0 MTU2PE0ZE 0 R/W * MTU2 PE0 High-Impedance Enable

This bit specifies whether to place the PE0/TIOC1A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Note: * Can be modified only once after a power-on reset.

10.3.6 Port Output Enable Control Register 2 (POECR2)

POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0111011100000000 RR / W * R/W* R/W* RR / W * R/W* R/W* RRRRRRRR --- --- --- Note: Can be modified only once after a power-on reset.* - MTU2 P1CZE MTU2 P2CZE MTU2 P3CZE --- Bit Bit Name Initial value R/W Description 15 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

14 MTU2P1CZE 1 R/W * MTU2 Port 1 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 395 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

13 MTU2P2CZE 1 R/W * MTU2 Port 2 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

12 MTU2P3CZE 1 R/W * MTU2 Port 3 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8  All 1 R/W * Reserved These bits are always read as 1. The write value should always be 1. 7 to 0 — 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * Can be modified only once after a power-on reset.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 396 of 758 REJ09B0243-0300

10.4 Operation

Table 10.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 10.4 Target Pins and Conditions for High-Impedance Control Pins Conditions Detailed Conditions MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) Input level detection, output level comparison, or SPOER setting MTU2P1CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) Input level detection, output level comparison, or SPOER setting MTU2P2CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) Input level detection, output level comparison, or SPOER setting MTU2P3CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 channel 0 pin (PE0/TIOC0A) Input level detection or SPOER setting MTU2PE0ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE1/TIOC0B) Input level detection or SPOER setting MTU2PE1ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE2/TIOC0C) Input level detection or SPOER setting MTU2PE2ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE3/TIOC0D) Input level detection or SPOER setting MTU2PE3ZE ((POE8F • POE8E) + (MTU2CH0HIZ))

10.4.1 Input Level Detection Operation

If the input conditions set by ICSR1 occur on the POE0, POE1, POE3*, and POE8 pins, the high- current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function or MTU2 function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0, POE1, POE3*, and POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 10.2 shows a sample timing after the level changes in input to the POE0, POE1, POE3*, and POE8 pins until the respective pins enter high-impedance state. Note: * This pin is supported only by the SH7125.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 398 of 758 REJ09B0243-0300

10.4.2 Output-Level Compare Operation

Figure 10.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. Pφ PE11/ TIOC3D PE9/ TIOC3B Low level overlapping detected High impedance state Figure 10.4 Output-Level Compare Operation

10.4.3 Release from High-Impedance State

High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 12 to 15 (POE0F to POE3F and POE8F) in ICSR1. However, note that when low- level sampling is selected by bits 0 to 7 in ICSR1, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to the POE pin and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1) in OCSR1. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 internal registers.

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 399 of 758 REJ09B0243-0300

10.5 Interrupts

The POE issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 10.5 shows the interrupt sources and their conditions. Table 10.5 Interrupt Sources and Conditions Name Interrupt Source Interrupt Flag Condition OEI1 Output enable interrupt 1 POE3F, POE1F, POE0F, and OSF1 PIE1 • (POE3F + POE1F + POE0F) + OIE1 • OSF1 OEI3 Output enable interrupt 2 POE8F PIE3 • POE8F

Section 10 Port Output Enable (POE) Rev. 3.00 Sep. 27, 2007 Page 400 of 758 REJ09B0243-0300

10.6 Usage Note

10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer

When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (Pf), after which the function is switched to general input. This also occurs when a power-on reset is issued from the WDT for pins that are being handled as high impedance due to short-circuit detection by the MTU2. Figure 10.5 shows the state of a pin for which the POE input has selected high impedance handling with the timer output selected when a power-on reset is issued from the WDT. Timer outputPin state General input Timer output General input High impedance state Timer output 1Pφ cycle POE input Pφ PFC setting value Power-on reset by WDT Figure 10.5 Pin State when a Power-On Reset is Issued from the Watchdog Timer

Section 11 Watchdog Timer (WDT) WDTS300B_000020030200 Rev. 3.00 Sep. 27, 2007 Page 401 of 758 REJ09B0243-0300 Section 11 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT). This LSI can be reset by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when clearing software standby mode. It can also be used as an interval timer.

11.1 Features

• Can be used to ensure the clock settling time: Use the WDT to revoke software standby mode.
• Can switch between watchdog timer mode and interval timer mode.
• Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
• An interrupt is generated in interval timer mode An interval timer interrupt is generated when the counter overflows.
• Choice of eight counter input clocks Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen.
• Choice of two resets Power-on reset and manual reset are available.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 403 of 758 REJ09B0243-0300

11.2 Input/Output Pin for WDT

Table 11.1 lists the WDT pin configuration. Table 11.1 WDT Pin Configuration Pin Name Abbreviation I/O Description Watchdog timer overflow WDTOVF Output When an overflow occurs in watchdog timer mode, an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 404 of 758 REJ09B0243-0300

11.3 Register Descriptions

The WDT has the following two registers. Refer to section 20, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. Table 11.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFFE810 8, 16 Watchdog timer control/status register WTCSR R/W H'00 H'FFFFE812 8, 16

11.3.1 Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The WTCNT counter is initialized to H'00 only by a power-on reset using the RES pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: WTCNT differs from other registers in that it is more difficult to write to. See section 11.3.3, Notes on Register Access, for details. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 405 of 758 REJ09B0243-0300

11.3.2 Watchdog Timer Control/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the RES pin. When used to count the clock settling time for canceling a software standby, it retains its value after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: WTCSR differs from other registers in that it is more difficult to write to. See section 11.3.3, Notes on Register Access, for details. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TME WT/IT RSTS WOVF IOVF CKS[2:0] Bit Bit Name Initial Value R/W Description

7 TME 0 R/W Timer Enable

Starts and stops timer operation. Clear this bit to 0 when using the WDT to revoke software standby mode 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled

6 WT/IT 0 R/W Timer Mode Select

Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode Note: If WT/IT is modified when the WDT is operating, the up-count may not be performed correctly.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 406 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

5 RSTS 0 R/W Reset Select

Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset

4 WOVF 0 R/W Watchdog Timer Overflow

Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode

3 IOVF 0 R/W Interval Timer Overflow

Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode 2 to 0 CKS[2:0] 000 R/W Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 40 MHz. 000: Pφ (6.4 µs) 001: Pφ /4 (25.6 µs) 010: Pφ /16 (102.4 µs) 011: Pφ /32 (204.8 µs) 100: Pφ /64 (409.6 µs) 101: Pφ /256 (1.64 ms) 110: Pφ /1024 (6.55 ms) 111: Pφ /4096 (26.21 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is operating, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not operating.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 407 of 758 REJ09B0243-0300

11.3.3 Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. 15 8 7 0 H'5A Write dataAddress: H'FFFFE810 WTCNT write 15 8 7 0 H'A5 Write dataAddress: H'FFFFE812 WTCSR write Figure 11.2 Writing to WTCNT and WTCSR

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 408 of 758 REJ09B0243-0300

11.4 Operation

11.4.1 Canceling Software Standbys

The WDT can be used to revoke software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RES pin low until the clock stabilizes.) 1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Transition to software standby mode by ex ecuting a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin. 5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes operation. The WOVF flag in WTCSR is not set when this happens.

11.4.2 Using Watchdog Timer Mode

While operating in watchdog timer mode, the WDT generates an internal reset of the type specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time the counter overflows. 1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0 bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes counting.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 409 of 758 REJ09B0243-0300 WTCNT value H'FF H'00 WDTOVF signal Internal reset signal (power-on reset selected) Overflow occurs H'00 is written to WTCNT WT/IT = 1 TME = 1 H'00 is written to WTCNT Count starts WOVF = 1 WDTOVF is asserted and an internal reset is generated

32 Pφ clock

(manual reset selected)

18 Pφ clock

3 Pφ + one cycle of count clock

Figure 11.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock is Specified to Pφ/32 by CKS2 to CKS0)

11.4.3 Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting.

Section 11 Watchdog Timer (WDT) Rev. 3.00 Sep. 27, 2007 Page 410 of 758 REJ09B0243-0300

11.5 Usage Note

If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT reaches the immediate H'00, but occurs when WTCNT changes from H'FF to H'00 after 257 cycles of count clock. Whereas if WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from H'FF to H'00 after one cycle of count clock.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 411 of 758 REJ09B0243-0300 Section 12 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function).

12.1 Features

• Choice of asynchronous or clock synchronous serial communication mode
• Asynchronous mode (channels 0 to 2 in the SH7125, channels 0 to 2 in the SH7124):  Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are twelve selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Multiprocessor communications  Receive error detection: Parity, overrun, and framing errors  Break detection: Break is detected by reading the RXD pin level directly when a framing error occurs.
• Clock synchronous mode (channels 0 to 2 in the SH7125, channels 0 and 2 in the SH7124):  Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function.  Data length: 8 bits  Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so high- speed continuous data transfer is possible in both transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal clock) or SCK pin (external clock)
• Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 413 of 758 REJ09B0243-0300

12.2 Input/Output Pins

The SCI has the serial pins summarized in table 12.1. Table 12.1 Pin Configuration Channel Pin Name * I/O Function

0 SCK0 I/O SCI0 clock input/output

RXD0 Input SCI0 receive data input TXD0 Output SCI0 transmit data output

1 SCK1 *

I/O SCI1 clock input/output RXD1 Input SCI1 receive data input TXD1 Output SCI1 transmit data output

2 SCK2 I/O SCI2 clock input/output

RXD2 Input SCI2 receive data input TXD2 Output SCI2 transmit data output Notes: 1. Pin names SCK, RXD, and TXD are used in the description for all channels, omitting the channel designation. 2. This pin is supported only by the SH7125. Channel 1 in the SH7124 is only for asynchronous mode.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 414 of 758 REJ09B0243-0300

12.3 Register Descriptions

The SCI has the following registers for each channel. For details on register addresses and register states during each processing, see section 20, List of Registers. Table 12.2 Register Configuration Chan- nel Register Name Abbrevia- tion R/W Initial Value Address Access Size

0 Serial mode register_0 SCSMR_0 R/W H'00 H'FFFFC000 8

Bit rate register_0 SCBRR_0 R/W H'FF H'FFFFC002 8 Serial control register_0 SCSCR_0 R/W H'00 H'FFFFC004 8 Transmit data register_0 SCTDR_0   H'FFFFC006 8 Serial status register_0 SCSSR_0 R/W H'84 H'FFFFC008 8 Receive data register_0 SCRDR_0   H'FFFFC00A 8 Serial direction control register_0 SCSDCR_0 R/W H'F2 H'FFFFC00C 8 Serial port register_0 SCSPTR_0 R/W H'01 H'FFFFC00E 8

1 Serial mode register_1 SCSMR_1 R/W H'00 H'FFFFC080 8

Bit rate register_1 SCBRR_1 R/W H'FF H'FFFFC082 8 Serial control register_1 SCSCR_1 R/W H'00 H'FFFFC084 8 Transmit data register_1 SCTDR_1   H'FFFFC086 8 Serial status register_1 SCSSR_1 R/W H'84 H'FFFFC088 8 Receive data register_1 SCRDR_1   H'FFFFC08A 8 Serial direction control register_1 SCSDCR_1 R/W H'F2 H'FFFFC08C 8 Serial port register_1 SCSPTR_1 R/W H'01 H'FFFFC08E 8

2 Serial mode register_2 SCSMR_2 R/W H'00 H'FFFFC100 8

Bit rate register_2 SCBRR_2 R/W H'FF H'FFFFC102 8 Serial control register_2 SCSCR_2 R/W H'00 H'FFFFC104 8 Transmit data register_2 SCTDR_2   H'FFFFC106 8 Serial status register_2 SCSSR_2 R/W H'84 H'FFFFC108 8 Receive data register_2 SCRDR_2   H'FFFFC10A 8 Serial direction control register_2 SCSDCR_2 R/W H'F2 H'FFFFC10C 8 Serial port register_2 SCSPTR_2 R/W H'01 H'FFFFC10E 8

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 415 of 758 REJ09B0243-0300

12.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. Bit: Initial value: R/W: 7654321 0

12.3.2 Receive Data Register (SCRDR)

SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and completes operation. After that, SCRSR is ready to receive data. Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously. SCRDR is a read-only register and cannot be written to by the CPU. Bit: Initial value: R/W: 7654321 0 RRRRRRRR

12.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, and then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to SCTSR directly. Bit: Initial value: R/W: 7654321 0

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 416 of 758 REJ09B0243-0300

12.3.4 Transmit Data Register (SCTDR)

SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be written or read to by the CPU. Bit: Initial value: R/W: 7654321 0 R/W R/W R/W R/W R/W R/W R/W R/W

12.3.5 Serial Mode Register (SCSMR)

SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W C/A CHR PE O/ E STOP MP CKS[1:0] Bit Bit Name Initial value R/W Description

7 C/ A 0 R/W Communication Mode

Selects whether the SCI operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode (Channel 1 in the SH7124 is not available.)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 417 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

6 CHR 0 R/W Character Length

Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. 0: 8-bit data 1: 7-bit data

5 PE 0 R/W Parity Enable

Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.

4 O/ E 0 R/W Parity mode

Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity 1: Odd parity If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 418 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

3 STOP 0 R/W Stop Bit Length

Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. 0: One stop bit* 1: Two stop bits* When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1 bits are added at the end of each transmitted character.

2 MP 0 R/W Multiprocessor Mode (only in asynchronous mode)

Enables or disables multiprocessor mode. The PE and O/E bit settings are ignored in multiprocessor mode. 0: Multiprocessor mode disabled 1: Multiprocessor mode enabled 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 12.3.10, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: P φ: Peripheral clock

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 419 of 758 REJ09B0243-0300

12.3.6 Serial Control Register (SCSCR)

SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TIE RIE TE RE MPIE TEIE CKE[1:0] Bit Bit Name Initial value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

Enables or disables a transmit-data-empty interrupt (TXI) to be issued when the TDRE flag in the serial status register (SCSSR) is set to 1 after serial transmit data is sent from the transmit data register (SCTDR) to the transmit shift register (SCTSR). TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE = 1 or by clearing the TIE bit to 0. 0: Transmit-data-empty interrupt request (TXI) is disabled 1: Transmit-data-empty interrupt request (TXI) is enabled

6 RIE 0 R/W Receive Interrupt Enable

Enables or disables a receive-data-full interrupt (RXI) and a receive error interrupt (ERI) to be issued when the RDRF flag in SCSSR is set to 1 after the serial data received is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR). RXI can be canceled by clearing the RDRF flag after reading RDRF =1. ERI can be canceled by clearing the FER, PER, or ORER flag to 0 after reading 1 from the flag. Both RXI and ERI can also be canceled by clearing the RIE bit to 0. 0: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 420 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

5 TE 0 R/W Transmit Enable

Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled. Select the transmit format in the serial mode register (SCSMR) before setting TE to 1.

4 RE 0 R/W Receive Enable

Enables or disables the SCI serial receiver. 0: Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR before setting RE to 1.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (only when MP = 1 in

SCSMR in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF, FER, and ORER status flags in SCSSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared to 0 and normal receiving operation is resumed. For details, see section 12.4.4, Multiprocessor Communication Function.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 421 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

2 TEIE 0 R/W Transmit End Interrupt Enable

Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled 1: Transmit end interrupt request (TEI) is enabled 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. When selecting the clock output in clock synchronous mode, set the C/A bit in SCSMR to 1 and then set bits CKE1 and CKE0. For details on clock source selection, see table 12.14 in section 12.4, Operation.

• Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored.) 01: Internal clock, SCK pin used for clock output* 10: External clock, SCK pin used for clock input* 11: External clock, SCK pin used for clock input* Clock synchronous mode 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 422 of 758 REJ09B0243-0300

12.3.7 Serial Status Register (SCSSR)

SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The TEND flag is a read-only bit and cannot be modified. Bit: Initial value: R/W: 7654321 0 10000100 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W TDRE RDRF ORER FER PER TEND MPB MPBT Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* Bit Bit Name Initial value R/W Description

7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether data has been transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR) and SCTDR has become ready to be written with next serial transmit data. 0: Indicates that SCTDR holds valid transmit data [Clearing condition]

• When 0 is written to TDRE after reading TDRE = 1 1: Indicates that SCTDR does not hold valid transmit data [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When data is transferred from SCTDR to SCTSR and data can be written to SCTDR

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 423 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to RDRF after reading RDRF = 1: Indicates that valid received data is stored in SCRDR [Setting condition]
• When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note: SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register (SCSCR) is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the received data will be lost.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 424 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to ORER after reading ORER = 1: Indicates that an overrun error occurred during reception* [Setting condition]
• When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR, and the data received subsequently is lost. Subsequent serial reception cannot be continued while the ORER flag is set to 1.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 425 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

4 FER 0 R/(W) * Framing Error

Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to FER after reading FER = 1 1: Indicates that a framing error occurred during reception [Setting condition]
• When the SCI founds that the stop bit at the end of the received data is 0 after completing reception* Notes: 1. The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the FER flag is set to 1.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 426 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

3 PER 0 R/(W) * Parity Error

Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to PER after reading PER = 1 1: Indicates that a parity error occurred during reception* [Setting condition]
• When the number of 1s in the received data and parity does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the PER flag is set to 1.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 427 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

2 TEND 1 R Transmit End

Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition]

• When 0 is written to TDRE after reading TDRE = 1 1: Indicates that transmission has ended [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When TDRE = 1 during transmission of the last bit of a 1-byte serial transmit character

1 MPB 0 R Multiprocessor Bit

Stores the multiprocessor bit found in the receive data. When the RE bit in SCSCR is cleared to 0, its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Specifies the multiprocessor bit value to be added to the transmit frame. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 428 of 758 REJ09B0243-0300

12.3.8 Serial Port Register (SCSPTR)

SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to SCSPTR. When reading the value on the SCI pins, use the respective port register. For details, see section 16, I/O Ports. Bit: Initial value: R/W: 7654321 0 00000001 R/W - - - R/W R/W - W EIO - - - SPB1IO SPB1DT - SPB0DT Bit Bit Name Initial value R/W Description

7 EIO 0 R/W Error Interrupt Only

Enables or disables RXI interrupts. While the EIO bit is set to 1, the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1. 0: The RIE bit enables or disables RXI and ERI interrupts. While the RIE bit is 1, RXI and ERI interrupts are sent to the INTC. 1: While the RIE bit is 1, only the ERI interrupt is sent to the INTC. 6 to 4  All 0  Reserved These bits are always read as 0. The write value should always be 0.

3 SPB1IO 0 R/W Clock Port Input/Output in Serial Port

Specifies the input/output direction of the SCK pin in the serial port. To output the data specified in the SPB1DT bit through the SCK pin as a port output pin, set the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0. 0: Does not output the SPB1DT bit value through the SCK pin. 1: Outputs the SPB1DT bit value through the SCK pin.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 429 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description

2 SPB1DT 0 R/W Clock Port Data in Serial Port

Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output 1  0  Reserved This bit is always read as 0. The write value should always be 0.

0 SPB0DT 1 W Serial Port Break Data

Controls the TXD pins together with the TE bit in SCSCR. This bit is write-only bit. Undefined value is read. However, the TXD pin function should be selected with the Pin Function Controller (PFC). Setting value of TE bit in SCSCR Setting value of SPB0DT bit TXD pin state 0 0 Low output 0 1 High output (initial state) 1 * Transmit data output in accord with serial core logic. Note: * Don't care

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 430 of 758 REJ09B0243-0300

12.3.9 Serial Direction Control Register (SCSDCR)

The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: Initial value: R/W: 7654321 0 11110010 RRRR R / W RRR ---- D I R --- Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These bits are always read as 1. The write value should always be 1.

3 DIR 0 R/W Data Transfer Direction

Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: SCTDR contents are transmitted in LSB-first order Receive data is stored in SCRDR in LSB-first 1: SCTDR contents are transmitted in MSB-first order Receive data is stored in SCRDR in MSB-first 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1  1 R Reserved This bit is always read as 1. The write value should always be 1. 0  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 431 of 758 REJ09B0243-0300

12.3.10 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. The SCBRR setting is calculated as follows: Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W

• Asynchronous mode: N = × 106 - 164 × 22n-1 × B Pφ
• Clock synchronous mode: N = × 106 - 18 × 22n-1 × B Pφ B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 12.3.)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 432 of 758 REJ09B0243-0300 Table 12.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0

0 P φ 0 0

1 P φ/4 0 1

2 P φ/16 1 0

3 P φ/64 1 1

Note: The bit rate error in asynchronous is given by the following formula: Pφ × 106

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 433 of 758 REJ09B0243-0300 Tables 12.4 to 12.6 show examples of SCBRR settings in asynchronous mode, and tables 12.7 to 12.9 show examples of SCBRR settings in clock synchronous mode. Table 12.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) Pφ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 434 of 758 REJ09B0243-0300 Table 12.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) Pφ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 435 of 758 REJ09B0243-0300 Table 12.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) Pφ (MHz) 34 36 38 40 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 150 -0.05 3 159 -0.12 3 168 -0.19 3 177 -0.25 150 3 110 -0.29 3 116 0.16 3 123 -0.24 3 129 0.16 300 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 600 2 110 -0.29 2 116 0.16 2 123 -0.24 2 129 0.16 1200 1 220 0.16 1 233 0.16 1 246 0.16 2 64 0.16 2400 1 110 -0.29 1 116 0.16 1 123 -0.24 1 129 0.16 4800 0 220 0.16 0 233 0.16 0 246 0.16 1 64 0.16 9600 0 110 -0.29 0 116 0.16 0 123 -0.24 0 129 0.16 14400 0 73 -0.29 0 77 0.16 0 81 0.57 0 86 -0.22 19200 0 54 0.62 0 58 -0.69 0 61 -0.24 0 64 0.16 28800 0 36 -0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 27 -1.18 0 28 1.02 0 30 -0.24 0 32 -1.36

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 436 of 758 REJ09B0243-0300 Table 12.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) P φ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N n N n N n N n N n N 250 3 155 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 3 140 3 155 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 500000 0 4 0 5 0 6 0 7 0 8 0 9 1000000   0 2   0 3   0 4

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 437 of 758 REJ09B0243-0300 Table 12.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) P φ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N n N n N n N n N n N 250 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000   0 5   0 6   0 7

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 438 of 758 REJ09B0243-0300 Table 12.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) P φ (MHz) 34 36 38 40 Bit Rate (bits/s) n N n N n N n N 250 500 1000 3 132 3 140 3 147 3 155 2500 2 212 2 224 2 237 2 249 5000 2 105 2 112 2 118 2 124 10000 1 212 1 224 1 237 1 249 25000 1 84 1 89 1 94 1 99 50000 0 169 0 179 0 189 0 199 100000 0 84 0 89 0 94 0 99 250000 0 33 0 35 0 37 0 39 500000 0 16 0 17 0 18 0 19 1000000   0 8   0 9 [Legend] Blank: No setting possible : Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 439 of 758 REJ09B0243-0300 Table 12.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 12.11 and 12.12 list the maximum rates for external clock input. Table 12.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 1187500 0 0 40 1250000 0 0

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 440 of 758 REJ09B0243-0300 Table 12.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 441 of 758 REJ09B0243-0300 Table 12.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 442 of 758 REJ09B0243-0300

12.4 Operation

12.4.1 Overview

For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 12.13. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 12.14. (1) Asynchronous Mode (Channels 0 to 2 in the SH7125, Channels 0 to 2 in the SH7124)

• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks.
• An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the clock supplied by the on- chip baud rate generator and can output a clock with a frequency 16 times the bit rate.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode (Channels 0 to 2 in the SH7125, Channels 0 and 2 in the SH7124)
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 443 of 758 REJ09B0243-0300 Table 12.13 SCSMR Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit Asynchronous 2 bits 1 x x x Clock synchronous 8-bit Not set None [Legend] x: Don't care Table 12.14 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use the SCK pin.

1 Clock with a frequency 16 times the bit rate

is output. 1 0 External Input a clock with frequency 16 times the bit rate. 1 0 0 Internal Serial clock is output. Clock synchronous 1 0 External Input the serial clock.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 444 of 758 REJ09B0243-0300

12.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 12.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 445 of 758 REJ09B0243-0300 (1) Transmit/Receive Formats Table 12.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 12.15 Serial Transfer Formats (Asynchronous Mode) PE x x x x S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SCSMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit x: Don't care

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 446 of 758 REJ09B0243-0300 (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 12.14). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. (3) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receives data register (SCRDR), which retains their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 447 of 758 REJ09B0243-0300 [4] [5] < Initialization completed> [1] Set the clock selection in SCSCR. [2] Set the data transfer format in SCSMR and SCSDCR. [3] Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [5] Set the TE bit or RE bit in SCSCR to 1. * Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting, and RXD pin is in an idle state for waiting the start bit during receiving. Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR Wait Yes [1] Start initialization Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0* [2] No Set value in SCBRR [3] 1-bit interval elapsed? Set data transfer format in SCSMR, SCSDCR Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 12.3 Sample Flowchart for SCI Initialization

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 449 of 758 REJ09B0243-0300 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. (A format in which neither parity nor multiprocessor bit is output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 450 of 758 REJ09B0243-0300 Figure 12.5 shows an example of the operation for transmission.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

(mark state) Data Parity bit Stop bit TXI interrupt request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request TEI interrupt request Figure 12.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 452 of 758 REJ09B0243-0300 <End> Error processing Parity error processing Yes No Clear ORER, PER, and FER flags in SCSSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER = 1? FER = 1? Break? PER = 1? Clear RE bit in SCSCR to 0 Figure 12.6 Sample Flowchart for Receiving Serial Data (cont)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 453 of 758 REJ09B0243-0300 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. A. Parity check: Th e SCI counts the number of 1s in the received data and checks whether the count matches the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). B. Stop bit check: The SCI checks wh ether the stop bit is 1. If there are two stop bits, only the first is checked. C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be transferred from the receive shift register (SCRSR) to SCRDR. If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in SCRDR. If a receive error is detected, the SCI operates as shown in table 12.16. Note: When a receive error occurs, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0. 4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Table 12.16 Receive Errors and Error Conditions Receive Error Abbreviation Error Condition Data Transfer Overrun error ORER When the next data reception is completed while the RDRF flag in SCSSR is set to 1 The received data is not transferred from SCRSR to SCRDR. Framing error FER When the stop bit is 0 The received data is transferred from SCRSR to SCRDR. Parity error PER When the received data does not match the even or odd parity specified in SCSMR The received data is transferred from SCRSR to SCRDR.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 454 of 758 REJ09B0243-0300 Figure 12.7 shows an example of the operation for reception.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/1 1

Figure 12.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit)

12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)

In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.8 shows the general format in clock synchronous serial communication. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High level except in continuous transfer Figure 12.8 Data Format in Clock Synchronous Communication

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 455 of 758 REJ09B0243-0300 In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source, see table 12.14. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only reception is performed, the synchronous clock continues to be output until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source. If the internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same time as receiving the n characters of data. (3) Transmitting and Receiving Data SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 457 of 758 REJ09B0243-0300 Transmitting Serial Data (Clock Synchronous Mode): Figure 12.10 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission Read TDRE flag in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? Read TEND flag in SCSSR TEND = 1? Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Figure 12.10 Sample Flowchart for Transmitting Serial Data

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 459 of 758 REJ09B0243-0300 Receiving Serial Data (Clock Synchronous Mode): Figure 12.12 shows a sample flowchart for receiving serial data. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching from asynchronous mode to clock synchronous mode, make sure that the ORER, PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not be set and data reception cannot be started. Start of reception Read ORER flag in SCSSR ORER = 1? Read RDRF flag in SCSSR RDRF = 1? Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling [1] Receive error handling: Read the ORER flag in SCSSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [2] SCI status check and receive data read: Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR, and clear the RDRF flag to 0. The transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read the receive data register (SCRDR) and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Figure 12.12 Sample Flowchart for Receiving Serial Data (1)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 460 of 758 REJ09B0243-0300 Error handling Clear ORER flag in SCSSR to 0 End Overrun error handling ORER = 1? Yes No Figure 12.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in orde r from the LSB to the MSB. After receiving the data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the received data in SCRDR. If a receive error is detected, the SCI operates as shown in table 12.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the RDRF flag to 0. 3. After setting RDRF to 1, if the receive-data- full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI).

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 462 of 758 REJ09B0243-0300 Yes No Start of transmission and reception Error processing No Yes ORER = 1? All data received? Read TDRE flag in SCSSR No Yes TDRE = 1? Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 No Yes RDRF = 1? Read ORER flag in SCSSR Read RDRF flag in SCSSR [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [3] SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Clear TE and RE bits in SCSCR to 0 Write transmit data to SCTDR, and clear TDRE flag in SCSSR to 0 End of transmission and reception Figure 12.14 Sample Flowchart for Transmitting/Receiving Serial Data

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 463 of 758 REJ09B0243-0300

12.4.4 Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPB bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCSCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 464 of 758 REJ09B0243-0300 Transmitting station Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial transmission line Serial data ID transmission cycle = receiving station specification Data transmission cycle = Data transmission to receiving station specified by ID (MPB = 1) (MPB = 0) H'01 H'AA [Legend] MPB: Multiprocessor bit Figure 12.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 465 of 758 REJ09B0243-0300

12.4.5 Multiprocessor Serial Data Transmission

Figure 12.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. Note that the MPBT bit must be held 1 until when an ID is transmitted. All other SCI operations are the same as those in asynchronous mode. No <End> [1] Yes Initialization Start transmission Read TDRE flag in SCSSR [2] No Yes No Yes Read TEND flag in SCSSR [3] No Yes [4] Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC TDRE = 1? All data transmitted? TEND = 1? Break output? Clear TDRE flag to 0 [1] SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. After initializing the SCI, when an ID is written to SCTDR register so as to transmit the ID, data is immediately transferred, and then the TDER flag is set to 1. The MPBT bit must be held 1 because the ID is not transmitted from the TXD pin at this time. When the TDRE flag is set to 1 after data following the ID is written to SCTDR, clear the MPBT bit to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Write transmit data to SCTDR and set MPBT bit in SCSSR Figure 12.16 Sample Multiprocessor Serial Transmission Flowchart

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 466 of 758 REJ09B0243-0300

12.4.6 Multiprocessor Serial Data Reception

Figure 12.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.18 shows an example of SCI operation for multiprocessor format reception. MPIE RXD RXD SCRDR value

0 D0 D1 D7 1 1 0 D0 D1 D7 01

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit Data (ID2)Start bit Stop bit Start bit Data (Data2) Stop bit RXI interrupt request (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and SCRDR retains its state ID1 (a) Data does not match station’s ID MPIE SCRDR value (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt processing routine MPIE bit is set to 1 again ID2 (b) Data matches station’s ID Data2ID1 MPIE = 0 MPIE = 0 Figure 12.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 467 of 758 REJ09B0243-0300 Yes <End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCSCR to 0 Error processing (Continued on next page) [5] No Yes FER = 1? or ORER = 1? RDRF = 1? All data received? Set MPIE bit in SCSCR to 1 [2] Read ORER and FER flags in SCSSR Read RDRF flag in SCSSR [3] Read receive data in SCRDR No Yes This station’s ID? Read ORER and FER flags in SCSSR Yes No Read RDRF flag in SCSSR No Yes FER = 1? or ORER = 1? Read receive data in SCRDR RDRF = 1? [1] SCI initialization: Set the RXD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCSCR to 1. [3] SCI status check, ID reception and comparison: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SCSSR and check that the RDRF flag is set to 1, then read the data in SCRDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD pin value. Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (1)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 468 of 758 REJ09B0243-0300 <End> Error processing Yes No Clear ORER and FER flags in SCSSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER = 1 FER = 1 Break? Clear RE bit in SCSCR to 0 [5] Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (2)

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 469 of 758 REJ09B0243-0300

12.5 SCI Interrupt Sources

The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 12.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt request is generated. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that transmission has been completed. Table 12.17 SCI Interrupt Sources Interrupt Source Description ERI Interrupt caused by receive error (ORER, FER, or PER) RXI Interrupt caused by receive data full (RDRF) TXI Interrupt caused by transmit data empty (TDRE) TEI Interrupt caused by transmit end (TENT)

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12.6 Serial Port Register (SCSPTR) and SCI Pins

The relationship between SCSPTR and the SCI pins is shown in figures 12.19 and 12.20. SPTRW: SCSPTR write Note: * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Reset Internal data bus Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* Bit 3 Bit 2 Reset QD R SCKIO SCK C QD R SCKDT SPTRW SPTRW C Figure 12.19 SPB1IO bit, SPB1DT bit, and SCK Pin SPTRW: SCSPTR write Internal data bus Transmit enable signal Bit 0 Reset Serial transmit data TXD QD R SPBDT SPTRW C Figure 12.20 SPB0DT bit and TXD Pin

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12.7 Usage Notes

12.7.1 SCTDR Writing and TDRE Flag

The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that the TDRE flag is set to 1.

12.7.2 Multiple Receive Error Occurrence

If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in table 12.18. When an overrun error occurs, data is not transferred from the receive shift register (SCRSR) to the receive data register (SCRDR) and the received data will be lost. Table 12.18 SCSSR Status Flag Values and Transfer of Received Data SCSSR Status Flags Receive Errors Generated RDRF ORER FER PER Receive Data Transfer from SCRSR to SCRDR Overrun error 1 1 0 0 Not transferred Framing error 0 0 1 0 Transferred Parity error 0 0 0 1 Transferred Overrun error + framing error 1 1 1 0 Not transferred Overrun error + parity error 1 1 0 1 Not transferred Framing error + parity error 0 0 1 1 Transferred Overrun error + framing error + parity error 1 1 1 1 Not transferred

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 472 of 758 REJ09B0243-0300

12.7.3 Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of received data to SCRDR is halted in the break state, the SCI receiver continues to operate.

12.7.4 Sending a Break Signal

The I/O condition and level of the TXD pin are determined by the SPB0DT bit in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin.

12.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 12.21.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 473 of 758 REJ09B0243-0300 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 D0 D1 16 clocks 8 clocks Base clock Receive data (RXD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: D - 0.5 N Where: M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

Section 12 Serial Communication Interface (SCI) Rev. 3.00 Sep. 27, 2007 Page 474 of 758 REJ09B0243-0300

12.7.6 Note on Using External Clock in Clock Synchronous Mode

TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1.

12.7.7 Module Standby Mode Setting

SCI operation can be disabled or enabled using the standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, see section 19, Power-Down Modes.

Section 13 A/D Converter (ADC) ADCMS20C_000020020700 Rev. 3.00 Sep. 27, 2007 Page 475 of 758 REJ09B0243-0300 Section 13 A/D Converter (ADC) This LSI includes a successive approximation type 10-bit A/D converter.

13.1 Features

• 10-bit resolution
• Input channels  8 channels (two independent A/D conversion modules)
• Conversion time: 2.0 µs per channel (preliminary value, operation when P φ = 25 MHz)
• Three operating modes  Single mode: Single-channel A/D conversion  Continuous scan mode: Repetitive A/D conversion on up to four channels  Single-cycle scan mode: Continuous A/D conversion on up to four channels
• Data registers  Conversion results are held in a 16-bit data register for each channel
• Sample-and-hold function
• Three methods for conversion start  Software  Conversion start trigger from multifunction timer pulse unit 2 (MTU2)  External trigger signal
• Interrupt request  An A/D conversion end interrupt request (ADI) can be generated
• Module standby mode can be set

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 477 of 758 REJ09B0243-0300

13.2 Input/Output Pins

Table 13.1 summarizes the input pins used by the A/D converter. This LSI has two A/D conversion modules, each of which can be operated independently. The input channels of A/D modules 0 and 1 are divided into two channel groups. Table 13.1 Pin Configuration Module Type Symbol I/O Function AVCC Input Analog block power supply and reference voltage AVSS Input Analog block ground and reference voltage Common ADTRG Input A/D external trigger input pin * AN0 Input Analog input pin 0 AN1 Input Analog input pin 1 Group 0 AN2 Input Analog input pin 2 A/D module 0 (A/D_0) AN3 Input Analog input pin 3 Group 1 AN4 Input Analog input pin 4 AN5 Input Analog input pin 5 Group 0 AN6 Input Analog input pin 6 Group 1 A/D module 1 (A/D_1) AN7 Input Analog input pin 7 Notes: The connected A/D module differs for each pin. The control registers of each module must be set. * This pin is supported only by the SH7125.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 478 of 758 REJ09B0243-0300

13.3 Register Descriptions

The A/D converter has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 13.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size A/D data register 0 ADDR0 R H'0000 H'FFFFC900 16 A/D data register 1 ADDR1 R H'0000 H'FFFFC902 16 A/D data register 2 ADDR2 R H'0000 H'FFFFC904 16 A/D data register 3 ADDR3 R H'0000 H'FFFFC906 16 A/D control/status register_0 ADCSR_0 R/W H'0000 H'FFFFC910 16 A/D control register_0 ADCR_0 R/W H'0000 H'FFFFC912 16 A/D data register 4 ADDR4 R H'0000 H'FFFFC980 16 A/D data register 5 ADDR5 R H'0000 H'FFFFC982 16 A/D data register 6 ADDR6 R H'0000 H'FFFFC984 16 A/D data register 7 ADDR7 R H'0000 H'FFFFC986 16 A/D control/status register_1 ADCSR_1 R/W H'0000 H'FFFFC990 16 A/D control register_1 ADCR_1 R/W H'0000 H'FFFFC992 16 A/D trigger select register_0 ADTSR_0 R/W H'0000 H'FFFFE890 8, 16

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 479 of 758 REJ09B0243-0300

13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7)

ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is stored in ADDR4.) The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 16 bits wide. When reading from ADDR, access must be performed in words. The initial value of ADDR is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRR RRRRRRRRRRRR 0000000000000000

13.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1)

ADCSR for each module controls A/D conversion operations. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/(W)* R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* ADF ADIE - - TRGE - CONADF STC CKSL[1:0] ADM[1:0] ADCS CH[2:0] Bit Bit Name Initial Value R/W Description

15 ADF 0 R/(W) * A/D End Flag

A status flag that indicates the end of A/D conversion. [Setting conditions]

• When A/D conversion ends in single mode
• When A/D conversion ends on all specified channels in scan mode [Clearing condition]
• When 0 is written after reading ADF = 1

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 480 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

14 ADIE 0 R/W A/D Interrupt Enable

The A/D conversion end interrupt (ADI) request is enabled when 1 is set When changing the operating mode, first clear the ADST bit to 0. 13, 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

11 TRGE 0 R/W Trigger Enable

Enables or disables triggering of A/D conversion by ADTRG and an MTU2 trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled When changing the operating mode, first clear the ADST bit to 0. 10  0 R Reserved This bit is always read as 0. The write value should always be 0.

9 CONADF 0 R/W ADF Control

Controls setting of the ADF bit in 2-channel scan mode. The setting of this bit is valid only when triggering of A/D conversion is enabled (TRGE = 1) in 2-channel scan mode. The setting of this bit is ignored in single mode or 4-channel scan mode. 0: The ADF bit is set when A/D conversion started by the group 0 trigger or group 1 trigger has finished. 1: The ADF bit is set when A/D conversion started by the group 0 trigger and A/D conversion started by the group 1 trigger have both finished. Note that the triggering order has no affect. When changing the operating mode, first clear the ADST bit to 0.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 481 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

8 STC 0 R/W State Control

Sets the A/D conversion time in combination with the CKSL1 and CKSL0 bits. 0: 50 states 1: 64 states When changing the A/D conversion time, first clear the ADST bit to 0. 7, 6 CKSL[1:0] 00 R/W Clock Select 1 and 0 Select the A/D conversion time. 00: Pφ/4 01: Pφ/3 10: Pφ/2 11: Pφ When changing the A/D conversion time, first clear the ADST bit to 0. CKSL[1:0] = B'11 can be set while Pφ ≤ 25 MHz. 5, 4 ADM[1:0] 00 R/W A/D Mode 1 and 0 Select the A/D conversion mode. 00: Single mode 01: 4-channel scan mode 10: Setting prohibited 11: 2-channel scan mode When changing the operating mode, first clear the ADST bit to 0.

3 ADCS 0 R/W A/D Continuous Scan

Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit to 0.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 482 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 2 to 0 CH[2:0] 000 R/W Channel Select 2 to 0 Select analog input channels. See table 13.3. When changing the operating mode, first clear the ADST bit to 0. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1)

ADCR for each module controls A/D conversion. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RR R / W RRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

13 ADST 0 R/W A/D Start

Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode or module standby mode. 12 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 483 of 758 REJ09B0243-0300 Table 13.3 Channel Select List Analog Input Channels Bit 2 Bit 1 Bit 0 Single Mode 4-Channel Scan Mode * CH2 CH1 CH0 A/D_0 A/D_1 A/D_0 A/D_1 0 0 0 AN0 AN4 AN0 AN4

1 AN1 AN5 AN0, AN1 AN4, AN5

1 0 AN2 AN6 AN0 to AN2 AN4 to AN6

1 AN3 AN7 AN0 to AN3 AN4 to AN7

Setting prohibited Setting prohibited Setting prohibited Setting prohibited Analog Input Channels Bit 2 Bit 1 Bit 0 2-Channel Scan Mode * CH2 CH1 CH0 A/D_0 A/D_1 0 0 0 AN0 AN4

1 AN0, AN1 AN4, AN5

1 AN2, AN3 AN6, AN7

Setting prohibited Setting prohibited Notes: * Continuous scan mode or single-scan mode can be selected with the ADCS bit.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 484 of 758 REJ09B0243-0300

13.3.4 A/D Trigger Select Register_0 (ADTSR_0)

The ADTSR_0 enables an A/D conversion started by an external trigger signal. In particular, the four channels in A/D module 0 are divided into two groups (group 0 and group 1) and the A/D trigger can be specified for each group independently in 2-channel scan mode. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TRG11S[3:0] TRG01S[3:0] TRG1S[3:0] TRG0S[3:0] Bit Bit Name Initial Value R/W Description 15 to 12 TRG11S[3:0] 0000 R/W A/D Trigger 1 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 1 when A/D module 1 is in 2- channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 485 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 11 to 8 TRG01S[3:0] 0000 R/W A/D Trigger 0 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 1 when A/D module 0 is in 2- channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 486 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 7 to 4 TRG1S[3:0] 0000 R/W A/D Trigger 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 1 is in single mode, 4-channel scan mode, or 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 487 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 3 to 0 TRG0S[3:0] 0000 R/W A/D Trigger 0 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 0 is in single mode, 4-channel scan mode, or 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. [Legend] x: Don't care

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 488 of 758 REJ09B0243-0300

13.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR.

13.4.1 Single Mode

In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU2, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state.

13.4.2 Continuous Scan Mode

In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels. 1. When the ADST bit in ADCR is set to 1 by software, MTU2, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 489 of 758 REJ09B0243-0300

13.4.3 Single-Cycle Scan Mode

In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (up to four channels). 1. When the ADST bit in ADCR is set to 1 by a software, MTU2, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state.

13.4.4 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing. Table 13.4 shows the A/D conversion time. As indicated in figure 13.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 13.4. In scan mode, the values given in table 13.4 apply to the first conversion time. The values given in table 13.5 apply to the second and subsequent conversions.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 490 of 758 REJ09B0243-0300 Pφ A/D converter A/D conversion A/D conversion start delay time(tD) A/D conversion time (tCONV) Analog input sampling time(tSPL) ADST write timing End of A/D conversion ADF Address Write cycle A/D synchronization time (Up to 6 states) Internal write signal Analog input sampling signal Idle state Sample-and-hold (2 states) Figure 13.2 A/D Conversion Timing

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 491 of 758 REJ09B0243-0300 Table 13.4 A/D Conversion Time (Single Mode) STC = 0 CKSL1 = 0 CKSL1 = 1 CKSL0 = 0 CKSL0 = 1 CKSL0 = 0 CKSL0 = 1 A/D conversion start delay time tD 2  6 2  5 2  4 2  3 Input sampling time t A/D conversion time tCONV 202  206 152  155 102  104 52  53 STC = 1 CKSL1 = 0 CKSL1 = 1 CKSL0 = 0 CKSL0 = 1 CKSL0 = 0 CKSL0 = 1 A/D conversion start delay time t D 2  6 2  5 2  4 2  3 Input sampling time A/D conversion time t CONV 258  262 194  197 130  132 66  67 Note: All values represent the number of states for P φ. Table 13.5 A/D Conversion Time (Scan Mode) Conversion Time Calculation Example STC CKSL1 CKSL0 Conversion Time (State) P φ = 25 MHz P φ = 40 MHz 0 200 (Fixed) 8 µs 5 µs 0 1 150 (Fixed) 6 µs 3.8 µs 0 100 (Fixed) 4 µs 2.5 µs 1 50 (Fixed) 2 µs Setting prohibited 0 256 (Fixed) 10.2 µs 6.4 µs 0 1 192 (Fixed) 7.7 µs 4.8 µs 0 128 (Fixed) 5.1 µs 3.2 µs 1 64 (Fixed) 2.6 µs Setting prohibited

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 492 of 758 REJ09B0243-0300

13.4.5 A/D Converter Activation by MTU2

The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU2. To activate the A/D converter by the MTU2, first set the TRGE bit in the A/D control/status register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR). After this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion request from the interval timer of the MTU2 occurs. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software.

13.4.6 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit in the A/D control/status register (ADCSR) is set to 1 while the TRGS3 to TRGS0 bits in the A/D trigger select register_0 (ADTSR_0) is set to external trigger input, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 13.3 shows the timing. CK ADTRG External trigger signal ADST A/D conversion Figure 13.3 External Trigger Input Timing

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 493 of 758 REJ09B0243-0300 13.4.7 2-Channel Scanning In 2-channel scan mode, since the four channels of analog input are divided into groups 0 and 1, triggers for activation of groups 0 and 1 are independently specifiable. Conversion end interrupts in 2-channel scan mode can be generated either on completion of group 0 or group 1 or on completion of group 0 and group 1. If conversion is to be started by triggers, the different sources for groups 0 and 1 are specified in ADTSR. A request for conversion by group 1 generated during conversion by group 0 is ignored. Figure 13.4 shows an example of operation when TRG4AN of the MTU2 has been specified as the A/D conversion start request by group 0 and TRG4BN of the MTU2 has been specified as the A/D conversion start request by group 1. TADCORA_4 TGRA_3 TADCORB_4 H'0000 TCNT_4 A/D conversion start request CONADF bit in ADCSR = 1 CONADF bit in ADCSR = 0 A/D conversion end (ADF) AN0 conversion AN1 conversion AN2 conversion AN3 conversion Figure 13.4 Example of 2-Channel Scanning

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 494 of 758 REJ09B0243-0300

13.5 Interrupt Sources

The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. Table 13.6 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag ADI0 A/D_0 conversion completed ADF in ADCSR_0 ADI1 A/D_1 conversion completed ADF in ADCSR_1

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 495 of 758 REJ09B0243-0300

13.6 Definitions of A/D Conversion Accuracy

This LSI's A/D conversion accuracy definitions are given below.

• Resolution The number of A/D converter digital output codes
• Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.5).
• Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 13.6).
• Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 13.6).
• Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and full- scale voltage. Does not include offset error, full-scale error, or quantization error (see figure 13.6).
• Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, full- scale error, quantization error, and nonlinearity error.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 496 of 758 REJ09B0243-0300 111 110 101 100 011 010 001 000 1024 1024 1022 1024 1023 1024 FS Quantization error Digital output Ideal A/D conversion characteristic Analog input voltage Figure 13.5 Definitions of A/D Conversion Accuracy

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 497 of 758 REJ09B0243-0300 FS Digital output Ideal A/D conversion characteristic Nonlinearity error Analog input voltageOffset error Actual A/D conversion characteristic Full-scale error Figure 13.6 Definitions of A/D Conversion Accuracy

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 498 of 758 REJ09B0243-0300

13.7 Usage Notes

13.7.1 Module Standby Mode Setting

Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes.

13.7.2 Permissible Signal Source Impedance

This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 kΩ, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 13.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted.

13.7.3 Influences on Absolute Accuracy

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere in the accuracy by the printed circuit digital signals on the mounting board (i.e, acting as antennas).

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 499 of 758 REJ09B0243-0300 20 pF 10 kΩ Cin = 20 pF Sensor output impedance of up to 3 kΩ or up to 1 kΩ This LSI Low-pass filter C to 0.1 µF Sensor input A/D converter equivalent circuit Figure 13.7 Example of Analog Input Circuit

13.7.4 Range of Analog Power Supply and Other Pin Settings

If the conditions below are not met, the reliability of the device may be adversely affected.

• Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ VAN ≤ AVref.
• Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open.

13.7.5 Notes on Board Design

In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board.

Section 13 A/D Converter (ADC) Rev. 3.00 Sep. 27, 2007 Page 500 of 758 REJ09B0243-0300

13.7.6 Notes on Noise Countermeasures

A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown in figure 13.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN7 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. AVcc AN0 to AN7 AVss Rin *2 100 Ω 0.1 µF 0.01 µF10 µF Notes: Values are reference values. 2. R in: Input impedance Figure 13.8 Example of Analog Input Protection Circuit Table 13.7 Analog Pin Specifications Item Min. Max. Unit Condition Analog input capacitance  20 pF  Permissible signal source impedance  3 k Ω Conversion time ≥ 4.0 µs  1 k Ω Conversion time < 4.0 µs

Section 14 Compare Match Timer (CMT) TIMCMT3A_000020030900 Rev. 3.00 Sep. 27, 2007 Page 501 of 758 REJ09B0243-0300 Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals.

14.1 Features

• Selection of four counter input clocks Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently for each channel.
• Interrupt request on compare match
• Module standby mode can be set. Figure 14.1 shows a block diagram of CMT. Control circuit Clock selection CMSTR CMCSR_0 CMCOR_0 CMCNT_0 Channel 0 Channel 1 CMT Pφ/8 CMCSR_1 CMCOR_1 CMCNT_1 Pφ/32 Pφ/128 Pφ/512 Pφ/8 Pφ/32 Pφ/128 Pφ/512 Clock selectionControl circuit Comparator Comparator [Legend] CMSTR: Compare match timer start register CMCSR: Compare match timer control/status register CMCOR: Compare match timer constant register CMCNT: Compare match counter CMI: Compare match interrupt Module bus Bus interface Internal bus CMI0 CMI1 Figure 14.1 Block Diagram of CMT

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 502 of 758 REJ09B0243-0300

14.2 Register Descriptions

The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Note that the channel number is omitted from the register name in this section. Table 14.1 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Compare match timer start register CMSTR R/W H'0000 H'FFFFCE00 8, 16, 32 Compare match timer control/status register_0 CMCSR_0 R/W H'0000 H'FFFFCE02 8, 16 Compare match counter_0 CMCNT_0 R/W H'0000 H'FFFFCE04 8, 16, 32 Compare match constant register_0 CMCOR_0 R/W H'FFFF H'FFFFCE06 8, 16 Compare match timer control/status register_1 CMCSR_1 R/W H'0000 H'FFFFCE08 8, 16, 32 Compare match counter_1 CMCNT_1 R/W H'0000 H'FFFFCE0A 8, 16 Compare match constant register_1 CMCOR_1 R/W H'FFFF H'FFFFCE0C 8, 16, 32

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 503 of 758 REJ09B0243-0300

14.2.1 Compare Match Timer Start Register (CMSTR)

CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRR R / W R / W Bit Bit Name Initial value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 STR1 0 R/W Count Start 1

Specifies whether compare match counter 1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started

0 STR0 0 R/W Count Start 0

Specifies whether compare match counter 0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started

14.2.2 Compare Match Timer Co ntrol/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects the counter input clock. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRR ( R / W ) *1 R/W R R R R R/W R/W Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.1.

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 504 of 758 REJ09B0243-0300 Bit Bit Name Initial value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 CMF 0 R/(W) *

Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition]

• When 0 is written to this bit after reading CMF = 1* [Setting condition] 1: CMCNT and CMCOR values match

6 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF=1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: Pφ/8 01: Pφ/32 10: Pφ/128 11: Pφ/512 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by simply writing 0 to it. In this case, read the bit as 1 once again and write 0 to it.

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 505 of 758 REJ09B0243-0300

14.2.3 Compare Match Counter (CMCNT)

CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. The initial value of CMCNT is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

14.2.4 Compare Match Constant Register (CMCOR)

CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. The initial value of CMCOR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 506 of 758 REJ09B0243-0300

14.3 Operation

14.3.1 Interval Count Operation

When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 14.2 shows the operation of the compare match counter. CMCOR H'0000 CMCNT value Time Counter cleared by compare match with CMCOR Figure 14.2 Counter Operation

14.3.2 CMCNT Count Timing

One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 14.3 shows the timing. Peripheral operating clock (Pφ) Nth clock (N + 1)th clockCount clock CMCNT N N + 1 Figure 14.3 Count Timing

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 507 of 758 REJ09B0243-0300

14.4 Interrupts

14.4.1 CMT Interrupt Sources

The CMT has channels and each of them to which a different vector address is allocated has compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 6, Interrupt Controller (INTC).

14.4.2 Timing of Setting Compare Match Flag

When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 14.4 shows the timing of CMF bit setting. N Peripheral operating clock (Pφ) Counter clock CMCNT CMCOR Compare match signal (N + 1)th clock N Figure 14.4 Timing of CMF Setting

14.4.3 Timing of Clearing Compare Match Flag

The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 508 of 758 REJ09B0243-0300

14.5 Usage Notes

14.5.1 Module Standby Mode Setting

The CMT operation can be disabled or enabled using the standby control register. The initial setting is for CMT operation to be halted. Access to a register is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes.

14.5.2 Conflict between Write and Compare-Match Processes of CMCNT

When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows the timing to clear the CMCNT counter. Peripheral operating clock (Pφ) Address Internal write Counter clear CMCNT T1 T2 N H'0000 CMCSR write cycle CMCNT Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 509 of 758 REJ09B0243-0300

14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the timing to write to CMCNT in words. M (CMCNT write data) CMCNT count-up enable Peripheral operating clock (Pφ) Address Internal write CMCNT T1 T2 N CMCSR write cycle CMCNT Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT

Section 14 Compare Match Timer (CMT) Rev. 3.00 Sep. 27, 2007 Page 510 of 758 REJ09B0243-0300

14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing has priority over the count-up. In this case, the count-up is not performed. The byte data on another side, which is not written to, is also not counted and the previous contents remain. Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT in bytes. M (CMCNT write data) XX CMCNTH CMCNT count-up enable CMCNTH CMCNTL Peripheral operating clock (Pφ) Address Internal write T1 T2 N CMCSR write cycle Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT

14.5.5 Compare Match between CMCNT and CMCOR

Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. If set, the CMF bit in CMCSR is set to 1 and CMCNT is cleared to H'0000.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 511 of 758 REJ09B0243-0300 Section 15 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 15.1 and 15.2 list the multiplexed pins of this LSI. Tables 15.3 and 15.4 list the pin functions in each operating mode. Table 15.1 SH7125 Multiplexed Pins Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Function 5 (Related Module) A PA0 I/O (port) POE0 input (POE) RXD0 input (SCI)   PA1 I/O (port) POE1 input (POE) TXD0 output (SCI)   PA2 I/O (port) IRQ0 input (INTC) SCK0 I/O (SCI)   PA3 I/O (port) IRQ1 input (INTC) RXD1 input (SCI) TRST input (H-UDI)  PA4 I/O (port) IRQ2 input (INTC) TXD1 output (SCI) TMS input (H-UDI)  PA5 I/O (port) IRQ3 input (INTC) SCK1 I/O (SCI)   PA6 I/O (port) TCLKA input (MTU2)    PA7 I/O (port) TCLKB input (MTU2) SCK2 I/O (SCI) TCK input (H-UDI)  PA8 I/O (port) TCLKC input (MTU2) RXD2 input (SCI) TDI input (H-UDI)  PA9 I/O (port) TCLKD input (MTU2) TXD2 output (SCI) POE8 input (POE) TDO output (H-UDI) PA10 I/O (port) RXD0 input (SCI)    PA11 I/O (port) TXD0 output (SCI) ADTRG input (A/D)   PA12 I/O (port) SCK0 I/O (SCI)    PA13 I/O (port) SCK1 I/O (SCI)    PA14 I/O (port) RXD1 input (SCI)    PA15 I/O (port) TXD1 output (SCI)    B PB1 I/O (port) TIC5W input (MTU2)    PB2 I/O (port) IRQ0 input (INTC) POE0 input (POE)   PB3 I/O (port) IRQ1 input (INTC) POE1 input (POE) TIC5V input (MTU2)  PB5 I/O (port) IRQ3 input (INTC) TIC5U input (MTU2)   PB16 I/O (port) POE3 input (POE)   

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 512 of 758 REJ09B0243-0300 Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Function 5 (Related Module) E PE0 I/O (port) TIOC0A I/O (MTU2)    PE1 I/O (port) TIOC0B I/O (MTU2) RXD0 input (SCI)   PE2 I/O (port) TIOC0C I/O (MTU2) TXD0 output (SCI)   PE3 I/O (port) TIOC0D I/O (MTU2) SCK0 I/O (SCI)   PE4 I/O (port) TIOC1A I/O (MTU2) RXD1 input (SCI)   PE5 I/O (port) TIOC1B I/O (MTU2) TXD1 output (SCI)   PE6 I/O (port) TIOC2A I/O (MTU2) SCK1 I/O (SCI)   PE7 I/O (port) TIOC2B I/O (MTU2)    PE8 I/O (port) TIOC3A I/O (MTU2)    PE9 I/O (port) TIOC3B I/O (MTU2)    PE10 I/O (port) TIOC3C I/O (MTU2)    PE11 I/O (port) TIOC3D I/O (MTU2)    PE12 I/O (port) TIOC4A I/O (MTU2)    PE13 I/O (port) TIOC4B I/O (MTU2) MRES input (INTC)   PE14 I/O (port) TIOC4C I/O (MTU2)    PE15 I/O (port) TIOC4D I/O (MTU2) IRQOUT output (INTC)   F PF0 input (port) AN0 input (A/D)    PF1 input (port) AN1 input (A/D)    PF2 input (port) AN2 input (A/D)    PF3 input (port) AN3 input (A/D)    PF4 input (port) AN4 input (A/D)    PF5 input (port) AN5 input (A/D)    PF6 input (port) AN6 input (A/D)    PF7 input (port) AN7 input (A/D)    Note: During A/D conversion, the AN input function is enabled.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 513 of 758 REJ09B0243-0300 Table 15.2 SH7124 Multiplexed Pins Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Function 5 (Related Module) A PA0 I/O (port) POE0 input (POE) RXD0 input (SCI)   PA1 I/O (port) POE1 input (POE) TXD0 output (SCI)   PA3 I/O (port) IRQ1 input (INTC) RXD1 input (SCI) TRST input (H-UDI)  PA4 I/O (port) IRQ2 input (INTC) TXD1 output (SCI) TMS input (H-UDI)  PA6 I/O (port) TCLKA input (MTU2)    PA7 I/O (port) TCLKB input (MTU2) SCK2 I/O (SCI) TCK input (H-UDI)  PA8 I/O (port) TCLKC input (MTU2) RXD2 input (SCI) TDI input (H-UDI)  PA9 I/O (port) TCLKD input (MTU2) TXD2 output (SCI) POE8 input (POE) TDO output (H-UDI) B PB1 I/O (port) TIC5W input (MTU2)    PB3 I/O (port) IRQ1 input (INTC) POE1 input (POE) TIC5V input (MTU2)  PB5 I/O (port) IRQ3 input (INTC) TIC5U input (MTU2)   E PE0 I/O (port) TIOC0A I/O (MTU2)    PE1 I/O (port) TIOC0B I/O (MTU2) RXD0 input (SCI)   PE2 I/O (port) TIOC0C I/O (MTU2) TXD0 output (SCI)   PE3 I/O (port) TIOC0D I/O (MTU2) SCK0 I/O (SCI)   PE8 I/O (port) TIOC3A I/O (MTU2)    PE9 I/O (port) TIOC3B I/O (MTU2)    PE10 I/O (port) TIOC3C I/O (MTU2)    PE11 I/O (port) TIOC3D I/O (MTU2)    PE12 I/O (port) TIOC4A I/O (MTU2)    PE13 I/O (port) TIOC4B I/O (MTU2) MRES input (INTC)   PE14 I/O (port) TIOC4C I/O (MTU2)    PE15 I/O (port) TIOC4D I/O (MTU2) IRQOUT output (INTC)  

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 514 of 758 REJ09B0243-0300 Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Function 5 (Related Module) F PF0 input (port) AN0 input (A/D)    PF1 input (port) AN1 input (A/D)    PF2 input (port) AN2 input (A/D)    PF3 input (port) AN3 input (A/D)    PF4 input (port) AN4 input (A/D)    PF5 input (port) AN5 input (A/D)    PF6 input (port) AN6 input (A/D)    PF7 input (port) AN7 input (A/D)    Note: During A/D conversion, the AN input function is enabled.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 515 of 758 REJ09B0243-0300 Table 15.3 SH7125 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities 4, 22, 35 Vcc Vcc 6, 24, 33 Vss Vss 8, 37 VCL VCL

61 AVcc AVcc

52 AVss AVss

47 PLLVss PLLVss

42 EXTAL EXTAL

41 XTAL XTAL

46 MD1 MD1

45 FWE/( ASEBRKAK/

ASEBRK*) FWE

39 RES RES

40 WDTOVF WDTOVF

44 NMI NMI

43 ASEMD0 ASEMD0

38 PA0 PA0/ POE0/RXD0

36 PA1 PA1/ POE1/TXD0

34 PA2 PA2/IRQ0/SCK0

32 PA3/( TRST*) PA3/IRQ1/RXD1

31 PA4/(TMS *) PA4/IRQ2/TXD1

30 PA5 PA5/IRQ3/SCK1

29 PA6 PA6/TCLKA

28 PA7/(TCK *) PA7/TCLKB/SCK2

27 PA8/(TDI *) PA8/TCLKC/RXD2

26 PA9/(TDO *) PA9/TCLKD/TXD2/ POE8

25 PA10 PA10/RXD0

23 PA11 PA11/TXD0/ ADTRG

21 PA12 PA12/SCK0

20 PA13 PA13/SCK1

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 516 of 758 REJ09B0243-0300 Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities

19 PA14 PA14/RXD1

18 PA15 PA15/TXD1

51 PB1 PB1/TIC5W

50 PB2 PB2/IRQ0/ POE0

49 PB3 PB3/IRQ1/ POE1/TIC5V

48 PB5 PB5/IRQ3/TIC5U

62 POE3 PB16/POE3

17 PE0 PE0/TIOC0A

16 PE1 PE1/TIOC0B/RXD0

15 PE2 PE2/TIOC0C/TXD0

14 PE3 PE3/TIOC0D/SCK0

13 PE4 PE4/TIOC1A/RXD1

12 PE5 PE5/TIOC1B/TXD1

11 PE6 PE6/TIOC2A/SCK1

10 PE7 PE7/TIOC2B

9 PE8 PE8/TIOC3A

5 PE9 PE9/TIOC3B

7 PE10 PE10/TIOC3C

3 PE11 PE11/TIOC3D

2 PE12 PE12/TIOC4A

1 PE13 PE13/TIOC4B/ MRES

64 PE14 PE14/TIOC4C

63 PE15 PE15/TIOC4D/ IRQOUT

60 PF0/AN0 PF0/AN0

59 PF1/AN1 PF1/AN1

58 PF2/AN2 PF2/AN2

57 PF3/AN3 PF3/AN3

56 PF4/AN4 PF4/AN4

55 PF5/AN5 PF5/AN5

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 517 of 758 REJ09B0243-0300 Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities

54 PF6/AN6 PF6/AN6

53 PF7/AN7 PF7/AN7

Note: * Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). Table 15.4 SH7124 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities 4, 17 Vcc Vcc 6, 19 Vss Vss 8, 25 VCL VCL

48 AVcc AVcc

39 AVss AVss

35 PLLVss PLLVss

30 EXTAL EXTAL

29 XTAL XTAL

34 MD1 MD1

33 FWE/( ASEBRKAK/

ASEBRK*) FWE

27 RES RES

28 WDTOVF WDTOVF

32 NMI NMI

31 ASEMD0 ASEMD0

26 PA0 PA0/ POE0/RXD0

24 PA1 PA1/ POE1/TXD0

23 PA3/( TRST*) PA3/IRQ1/RXD1

22 PA4/(TMS *) PA4/IRQ2/TXD1

21 PA6 PA6/TCLKA

20 PA7/(TCK *) PA7/TCLKB/SCK2

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 518 of 758 REJ09B0243-0300 Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities

18 PA8/(TDI *) PA8/TCLKC/RXD2

16 PA9/(TDO *) PA9/TCLKD/TXD2/ POE8

38 PB1 PB1/TIC5W

37 PB3 PB3/IRQ1/ POE1/TIC5V

36 PB5 PB5/IRQ3/TIC5U

15 PE0 PE0/TIOC0A

14 PE1 PE1/TIOC0B/RXD0

13 PE2 PE2/TIOC0C/TXD0

12 PE3 PE3/TIOC0D/SCK0

11 PE8 PE8/TIOC3A

9 PE9 PE9/TIOC3B

10 PE10 PE10/TIOC3C

7 PE11 PE11/TIOC3D

5 PE12 PE12/TIOC4A

3 PE13 PE13/TIOC4B/ MRES

2 PE14 PE14/TIOC4C

1 PE15 PE15/TIOC4D/ IRQOUT

47 PF0/AN0 PF0/AN0

46 PF1/AN1 PF1/AN1

45 PF2/AN2 PF2/AN2

44 PF3/AN3 PF3/AN3

43 PF4/AN4 PF4/AN4

42 PF5/AN5 PF5/AN5

41 PF6/AN6 PF6/AN6

40 PF7/AN7 PF7/AN7

Note: * Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low).

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 519 of 758 REJ09B0243-0300

15.1 Register Descriptions

The PFC has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 15.5 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Port A I/O register L PAIORL R/W H'0000 H'FFFFD106 8, 16 Port A control register L4 PACRL4 R/W H'0000 H’FFFFD110 8, 16, 32 Port A control register L3 PACRL3 R/W H'0000 H’FFFFD112 8, 16 Port A control register L2 PACRL2 R/W H'0000 H’FFFFD114 8, 16, 32 Port A control register L1 PACRL1 R/W H'0000 H’FFFFD116 8, 16 Port B I/O register H PBIORH R/W H'0000 H'FFFFD184 8, 16, 32 Port B I/O register L PBIORL R/W H'0000 H'FFFFD186 8, 16 Port B control register H1 PBCRH1 R/W H'0000 H'FFFFD18E 8, 16 Port B control register L2 PBCRL2 R/W H'0000 H'FFFFD194 8, 16, 32 Port B control register L1 PBCRL1 R/W H'0000 H'FFFFD196 8, 16 Port E I/O register L PEIORL R/W H'0000 H'FFFFD306 8, 16 Port E control register L4 PECRL4 R/W H'0000 H'FFFFD310 8, 16, 32 Port E control register L3 PECRL3 R/W H'0000 H'FFFFD312 8, 16 Port E control register L2 PECRL2 R/W H'0000 H'FFFFD314 8, 16, 32 Port E control register L1 PECRL1 R/W H'0000 H'FFFFD316 8, 16 IRQOUT function control register IFCR R/W H'0000 H'FFFFD322 8, 16

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 520 of 758 REJ09B0243-0300

15.1.1 Port A I/O Register L (PAIORL)

PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0). In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 15 to 10, 5, and 2 of PAIORL are disabled in SH7124. The initial value of PAIORL is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR

15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4)

PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. SH7125:

• Port A Control Register L4 (PACRL4) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PA15 MD2 PA15 MD1 PA15 MD0 - PA14 MD2 PA14 MD1 PA14 MD0 - PA13 MD2 PA13 MD1 PA13 MD0 - PA12 MD2 PA12 MD1 PA12 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 521 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA15MD2 PA15MD1 PA15MD0 R/W R/W R/W PA15 Mode Select the function of the PA15/TXD1 pin. 000: PA15 I/O (port) 110: TXD1 output (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PA14MD2 PA14MD1 PA14MD0 R/W R/W R/W PA14 Mode Select the function of the PA14/RXD1 pin. 000: PA14 I/O (port) 110: RXD1 input (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PA13MD2 PA13MD1 PA13MD0 R/W R/W R/W PA13 Mode Select the function of the PA13/SCK1 pin. 000: PA13 I/O (port) 110: SCK1 I/O (SCI) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PA12MD2 PA12MD1 PA12MD0 R/W R/W R/W PA12 Mode Select the function of the PA12/SCK0 pin. 000: PA12 I/O (port) 110: SCK0 I/O (SCI) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 522 of 758 REJ09B0243-0300

• Port A Control Register L3 (PACRL3) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PA11 MD2 PA11 MD1 PA11 MD0 - PA10 MD2 PA10 MD1 PA10 MD0 - PA9 MD2 PA9 MD1 PA9 MD0 - PA8 MD2 PA8 MD1 PA8 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PA11MD2 PA11MD1 PA11MD0 R/W R/W R/W PA11 Mode Select the function of the PA11/TXD0/ADTRG pin. 000: PA11 I/O (port) 010: ADTRG input (A/D) 110: TXD0 output (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PA10MD2 PA10MD1 PA10MD0 R/W R/W R/W PA10 Mode Select the function of the PA10/RXD0 pin. 000: PA10 I/O (port) 110: RXD0 input (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 523 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA9MD2 PA9MD1 PA9MD0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/TXD2/TDO/POE8 pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDO output. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PA8MD2 PA8MD1 PA8MD0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RXD2/TDI pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDI input. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 524 of 758 REJ09B0243-0300

• Port A Control Register L2 (PACRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PA7 MD2 PA7 MD1 PA7 MD0 - PA6 MD2 PA6 MD1 PA6 MD0 - PA5 MD2 PA5 MD1 PA5 MD0 - PA4 MD2 PA4 MD1 PA4 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PA7MD2 PA7MD1 PA7MD0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/SCK2/TCK pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 110: SCK2 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PA6MD2 PA6MD1 PA6MD0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PA5MD2 PA5MD1 PA5MD0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ3/SCK1 pin. 000: PA5 I/O (port) 001: SCK1 I/O (SCI) 111: IRQ3 input (INTC) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 525 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PA4MD2 PA4MD1 PA4MD0 R/W R/W R/W PA4 Mode Select the function of the PA4/IRQ2/TXD1/TMS pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA4 I/O (port) 001: TXD1 output (SCI) 111: IRQ2 input (INTC) Other than above: Setting prohibited

• Port A Control Register L1 (PACRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PA3 MD2 PA3 MD1 PA3 MD0 - PA2 MD2 PA2 MD1 PA2 MD0 - PA1 MD2 PA1 MD1 PA1 MD0 - PA0 MD2 PA0 MD1 PA0 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PA3MD2 PA3MD1 PA3MD0 R/W R/W R/W PA3 Mode Select the function of the PA3/IRQ1/RXD1/TRST pin. When the E10A is in use (ASEMD0 = low), function is fixed to TRST input. 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 526 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA2MD2 PA2MD1 PA2MD0 R/W R/W R/W PA2 Mode Select the function of the PA2/IRQ0/SCK0 pin. 000: PA2 I/O (port) 001: SCK0 I/O (SCI) 011: IRQ0 input (INTC) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PA1MD2 PA1MD1 PA1MD0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD0 pin. 000: PA1 I/O (port) 001: TXD0 output (SCI) 111: POE1 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PA0MD2 PA0MD1 PA0MD0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD0 pin. 000: PA0 I/O (port) 001: RXD0 input (SCI) 111: POE0 input (POE) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 527 of 758 REJ09B0243-0300 SH7124:

• Port A Control Register L4 (PACRL4) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
• Port A Control Register L3 (PACRL3) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRR R / W R / W R / W R R / W R / W R / W MD2 PA9 MD1 PA9 MD0 - PA8 MD2 PA8 MD1 PA8 MD0 Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PA9MD2 PA9MD1 PA9MD0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/TXD2/TDO/POE8 pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDO output. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 528 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA8MD2 PA8MD1 PA8MD0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RXD2/TDI pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDI input. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) Other than above: Setting prohibited

• Port A Control Register L2 (PACRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R R R R R/W R/W R/W - PA7 MD2 PA7 MD1 PA7 MD0 - PA6 MD2 PA6 MD1 PA6 MD0 ----- PA4 MD2 PA4 MD1 PA4 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PA7MD2 PA7MD1 PA7MD0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/SCK2/TCK pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 110: SCK2 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 529 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA6MD2 PA6MD1 PA6MD0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) Other than above: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PA4MD2 PA4MD1 PA4MD0 R/W R/W R/W PA4 Mode Select the function of the PA4/IRQ2/TXD1/TMS pin. When the E10A is in use (ASEMD0 = low), function is fixed to TMS input. 000: PA4 I/O (port) 001: TXD1 output (SCI) 111: IRQ2 input (INTC) Other than above: Setting prohibited

• Port A Control Register L1 (PACRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R R R R R/W R/W R/W R R/W R/W R/W - PA3 MD2 PA3 MD1 PA3 MD0 ----- PA1 MD2 PA1 MD1 PA1 MD0 - PA0 MD2 PA0 MD1 PA0 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 530 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PA3MD2 PA3MD1 PA3MD0 R/W R/W R/W PA3 Mode Select the function of the PA3/IRQ1/RXD1/TRST pin. When the E10A is in use (ASEMD0 = low), function is fixed to TRST input. 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PA1MD2 PA1MD1 PA1MD0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD0 pin. 000: PA1 I/O (port) 001: TXD0 output (SCI) 111: POE1 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PA0MD2 PA0MD1 PA0MD0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD0 pin. 000: PA0 I/O (port) 001: RXD0 input (SCI) 100: POE0 output (POE) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 531 of 758 REJ09B0243-0300

15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)

PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B as inputs or outputs. Bits PB16IOR, PB5IOR, and PB3IOR to PB1IOR correspond to pins PB16, PB5, and PB3 to PB1, respectively (names of multiplexed pins are here given as port names and pin numbers alone). PBIORL is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB5 and PB3 to PB1), and the SCK pin is functioning as inputs/outputs of SCI. In other states, PBIORL is disabled. PBIORH is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB16). In other states, PBIORH is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set to 1, and an input pin if the bit is cleared to 0. However, bit 2 of PBIORL and bit 0 of PBIORH are disabled in SH7124. Bits 15 to 6, 4, and 0 of PBIORL and bits 15 to 1 of PBIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PBIORL and PBIORH are H'0000, respectively.

• Port B I/O Register H (PBIORH) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRR R / W IOR
• Port B I/O Register L (PBIORL) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R R / W R / W R / W R IOR - PB3 IOR PB2 IOR PB1 IOR -

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 532 of 758 REJ09B0243-0300

15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1)

PBCRL1, PBCRL2, and PBCRH1 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port B. SH7125:

• Port B Control Register H1 (PBCRH1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000001 RRRRRRRRRRRRRRR R / W * Note: After a power-on reset, write can be performed only once.* MD Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 PB16MD 1 R/W * PB16 Mode

Select the function of the PB16/POE3 pin. 0: PB16 I/O (port) 1: POE3 input (POE)

• Port B Control Register L2 (PBCRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRR R / W R / W R / W RRRR MD2 PB5 MD1 PB5 MD0 ---- Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 533 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PB5MD2 PB5MD1 PB5MD0 R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/TIC5U pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

• Port B Control Register L1 (PBCRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R R R - PB3 MD2 PB3 MD1 PB3 MD0 - PB2 MD2 PB2 MD1 PB2 MD0 - PB1 MD2 PB1 MD1 PB1 MD0 ---- Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PB3MD2 PB3MD1 PB3MD0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1/TIC5V pin. 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 534 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PB2MD2 PB2MD1 PB2MD0 R/W R/W R/W PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 001: IRQ0 input (INTC) 010: POE0 input (POE) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PB1MD2 PB1MD1 PB1MD0 R/W R/W R/W PB1 Mode Select the function of the PB1/TIC5W pin. 000: PB1 I/O (port) 011: TIC5W input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. SH7124:

• Port B Control Register H1 (PBCRH1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 535 of 758 REJ09B0243-0300

• Port B Control Register L2 (PBCRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRR R / W R / W R / W RRRR MD2 PB5 MD1 PB5 MD0 ---- Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PB5MD2 PB5MD1 PB5MD0 R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/TIC5U pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.
• Port B Control Register L1 (PBCRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R R R R R/W R/W R/W R R R R - PB3 MD2 PB3 MD1 PB3 MD0 ----- PB1 MD2 PB1 MD1 PB1 MD0 ---- Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 536 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PB3MD2 PB3MD1 PB3MD0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1/TIC5V pin. 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) Other than above: Setting prohibited 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PB1MD2 PB1MD1 PB1MD0 R/W R/W R/W PB1 Mode Select the function of the PB1/TIC5W pin. 000: PB1 I/O (port) 011: TIC5W input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 537 of 758 REJ09B0243-0300

15.1.5 Port E I/O Register L (PEIORL)

PEIORL is a 16-bit readable/writable register that is used to set the pins on port E as inputs or outputs. PE15IOR to PE0IOR correspond to pins PE15 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), and the TIOC pin is functioning as inputs/outputs of MTU2. In other states, PEIORL is disabled. A given pin on port E will be an output pin if the corresponding bit in PEIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 7 to 4 of PEIORL are disabled in SH7124. The initial value of PEIORL is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PE15 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR

15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4)

PECRL1 to PECRL4, are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port E. SH7125:

• Port E Control Register L4 (PECRL4) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R R/W R/W R R/W R/W R/W - PE15 MD2 PE15 MD1 PE15 MD0 - PE14 MD2 PE14 MD1 PE14 MD0 -- PE13 MD1 PE13 MD0 - PE12 MD2 PE12 MD1 PE12 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 538 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PE15MD2 PE15MD1 PE15MD0 R/W R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE14MD2 PE14MD1 PE14MD0 R/W R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PE13MD1 PE13MD0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PE12MD2 PE12MD1 PE12MD0 R/W R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 539 of 758 REJ09B0243-0300

• Port E Control Register L3 (PECRL3) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PE11 MD2 PE11 MD1 PE11 MD0 - PE10 MD2 PE10 MD1 PE10 MD0 - PE9 MD2 PE9 MD1 PE9 MD0 - PE8 MD2 PE8 MD1 PE8 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PE11MD2 PE11MD1 PE11MD0 R/W R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE10MD2 PE10MD1 PE10MD0 R/W R/W R/W PE10 Mode Select the function of the PE10/TIOC3C pin. 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PE9MD2 PE9MD1 PE9MD0 R/W R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 540 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PE8MD2 PE8MD1 PE8MD0 R/W R/W R/W PE8 Mode Select the function of the PE8/TIOC3A pin. 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited

• Port E Control Register L2 (PECRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PE7 MD2 PE7 MD1 PE7 MD0 - PE6 MD2 PE6 MD1 PE6 MD0 - PE5 MD2 PE5 MD1 PE5 MD0 - PE4 MD2 PE4 MD1 PE4 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PE7MD2 PE7MD1 PE7MD0 R/W R/W R/W PE7 Mode Select the function of the PE7/TIOC2B pin. 000: PE7 I/O (port) 001: TIOC2B I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE6MD2 PE6MD1 PE6MD0 R/W R/W R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK1 pin. 000: PE6 I/O (port) 001: TIOC2A I/O (MTU2) 110: SCK1 I/O (SCI) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 541 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PE5MD2 PE5MD1 PE5MD0 R/W R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TXD1 pin. 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 110: TXD1 output (SCI) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PE4MD2 PE4MD1 PE4MD0 R/W R/W R/W PE4 Mode Select the function of the PE4/TIOC1A/RXD1 pin. 000: PE4 I/O (port) 001: TIOC1A I/O (MTU2) 110: RXD1 input (SCI) Other than above: Setting prohibited

• Port E Control Register L1 (PECRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R R/W R/W - PE3 MD2 PE3 MD1 PE3 MD0 - PE2 MD2 PE2 MD1 PE2 MD0 - PE1 MD2 PE1 MD1 PE1 MD0 -- PE0 MD1 PE0 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 542 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description PE3MD2 PE3MD1 PE3MD0 R/W R/W R/W PE3 Mode Select the function of the PE3/TIOC0D/SCK0 pin. 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE2MD2 PE2MD1 PE2MD0 R/W R/W R/W PE2 Mode Select the function of the PE2/TIOC0C/TXD0 pin. 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PE1MD2 PE1MD1 PE1MD0 R/W R/W R/W PE1 Mode Select the function of the PE1/TIOC0B/RXD0 pin. 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PE0MD1 PE0MD0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 543 of 758 REJ09B0243-0300 SH7124:

• Port E Control Register L4 (PECRL4) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R R/W R/W R R/W R/W R/W - PE15 MD2 PE15 MD1 PE15 MD0 - PE14 MD2 PE14 MD1 PE14 MD0 -- PE13 MD1 PE13 MD0 - PE12 MD2 PE12 MD1 PE12 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PE15MD2 PE15MD1 PE15MD0 R/W R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE14MD2 PE14MD1 PE14MD0 R/W R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PE13MD1 PE13MD0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 544 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PE12MD2 PE12MD1 PE12MD0 R/W R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited

• Port E Control Register L3 (PECRL3) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W - PE11 MD2 PE11 MD1 PE11 MD0 - PE10 MD2 PE10 MD1 PE10 MD0 - PE9 MD2 PE9 MD1 PE9 MD0 - PE8 MD2 PE8 MD1 PE8 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PE11MD2 PE11MD1 PE11MD0 R/W R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE10MD2 PE10MD1 PE10MD0 R/W R/W R/W PE10 Mode Select the function of the PE10/TIOC3C pin. 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 545 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PE9MD2 PE9MD1 PE9MD0 R/W R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. PE8MD2 PE8MD1 PE8MD0 R/W R/W R/W PE8 Mode Select the function of the PE8/TIOC3A pin. 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited

• Port E Control Register L2 (PECRL2) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 546 of 758 REJ09B0243-0300

• Port E Control Register L1 (PECRL1) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R R/W R/W - PE3 MD2 PE3 MD1 PE3 MD0 - PE2 MD2 PE2 MD1 PE2 MD0 - PE1 MD2 PE1 MD1 PE1 MD0 -- PE0 MD1 PE0 MD0 Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. PE3MD2 PE3MD1 PE3MD0 R/W R/W R/W PE3 Mode Select the function of the PE3/TIOC0D/SCK0 pin. 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. PE2MD2 PE2MD1 PE2MD0 R/W R/W R/W PE2 Mode Select the function of the PE2/TIOC0C/TXD0 pin. 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. PE1MD2 PE1MD1 PE1MD0 R/W R/W R/W PE1 Mode Select the function of the PE1/TIOC0B/RXD0 pin. 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 547 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. PE0MD1 PE0MD0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited

15.1.7 IRQOUT Function Control Register (IFCR)

IFCR is a 16-bit readable/writable register that is used to control the IRQOUT pin output when it is selected as the multiplexed pin function by port E control register L4 (PECRL4). When PECRL4 selects another function, the IFCR setting does not affect the pin function. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRR R / W R / W MD1 IRQ MD0 Bit Bit Name Initial Value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. IRQMD1 IRQMD0 R/W R/W Port E IRQOUT Pin Function Select Select the IRQOUT pin function when bits 14 to 12 (PE15MD2 to PE15MD0) in PECRL4 are set to B'011. 00: Interrupt request accept signal output Other than above: Always high-level output

Section 15 Pin Function Controller (PFC) Rev. 3.00 Sep. 27, 2007 Page 548 of 758 REJ09B0243-0300

15.2 Usage Notes

1. In this LSI, the same function is availabl e as a multiplexed function on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. If two or more pins are specified for one function, however, there are two cautions shown below.  When the pin function is input Signals input to several pins are formed as one signal through OR or AND logic and the signal is transmitted into the LSI. Therefore, a signal that differs from the input signals may be transmitted to the LSI depending on the input signals in other pins that have the same functions. Table 15.6 shows the transmit forms of input functions allocated to several pins. When using one of the functions shown below in multiple pins, use it with care of signal polarity considering the transmit forms. Table 15.6 Transmit Forms of Input Functions Allocated to Multiple Pins OR Type AND Type SCK0 to SCK2, RXD0 to RXD2, POE0, POE1, POE3*, POE8 IRQ0* to IRQ3 Note: * This pin is supported only by the SH7125. OR type: Signals input to several pins are formed as one signal through OR logic and the signal is transmitted into the LSI. AND type: Signals input to several pins are formed as one signal through AND logic and the signal is transmitted into the LSI.  When the pin function is output Each selected pin can output the same function. 2. When the port input is switched from a low level to the IRQ edge for the pins that are multiplexed with input/output and IRQ, the corresponding edge is detected. 3. Do not set functions other than those specified in tables 15.3 and 15.4. Otherwise, correct operation cannot be guaranteed.

Rev. 3.00 Sep. 27, 2007 Page 549 of 758 REJ09B0243-0300 Section 16 I/O Ports The SH7125 has four ports: A, B, E, and F. Port A is a 16-bit port, port B is a 5-bit port, and port E is a 16-bit port. Port F is an 8-bit input-only port. The SH7124 has four ports: A, B, E, and F. Port A is an 8-bit port, port B is a 3-bit port, and port E is a 12-bit port. Port F is an 8-bit input-only port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data.

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16.1 Port A

Port A in the SH7125 is an input/output port with the 16 pins shown in figure 16.1. PA15 (I/O)/TXD1 (output) PA14 (I/O)/RXD1 (input) PA13 (I/O)/SCK1 (I/O) PA12 (I/O)/SCK0 (I/O) PA11 (I/O)/TXD0 (output)/ADTRG (input) PA10 (I/O)/RXD0 (input) PA9 (I/O)/TCLKD (input)/TXD2 (output)/TDO (output)/POE8 (input) PA8 (I/O)/TCLKC (input)/RXD2 (input)/TDI (input) PA7 (I/O)/TCLKB (input)/SCK2 (I/O)/TCK (input) PA6 (I/O)/TCLKA (input) PA5 (I/O)/IRQ3 (input)/SCK1 (I/O) PA4 (I/O)/IRQ2 (input)/TXD1 (output)/TMS (input) PA3 (I/O)/IRQ1 (input)/RXD1 (input)/TRST (input) PA2 (I/O)/IRQ0 (input)/SCK0 (I/O) PA1 (I/O)/POE1 (input)/TXD0 (output) PA0 (I/O)/POE0 (input)/RXD0 (input) Port A Figure 16.1 Port A (SH7125) Port A in the SH7124 is an input/output port with the eight pins shown in figure 16.2. PA9 (I/O)/TCLKD (input)/TXD2 (output)/TDO (output)/POE8 (input) PA8 (I/O)/TCLKC (input)/RXD2 (input)/TDI (input) PA7 (I/O)/TCLKB (input)/SCK2 (I/O)/TCK (input) PA6 (I/O)/TCLKA (input) PA4 (I/O)/IRQ2 (input)/TXD1 (output)/TMS (input) PA3 (I/O)/IRQ1 (input)/RXD1 (input)/TRST (input) PA1 (I/O)/POE1 (input)/TXD0 (output) PA0 (I/O)/POE0 (input)/RXD0 (input) Port A Figure 16.2 Port A (SH7124)

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16.1.1 Register Descriptions

Port A is a 16-bit input/output port in the SH7125 and an 8-bit input/output port in the SH7124. Port A has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.1 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Port A data register L PADRL R/W H'0000 H'FFFFD102 8, 16 Port A port register L PAPRL R  H'FFFFD11E 8, 16

16.1.2 Port A Data Register L (PADRL)

PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125. Bits PA9DR to PA6DR, PA4DR, PA3DR, PA1DR, and PA0DR correspond to pins PA9 to PA6, PA4, PA3, PA1, and PA0, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 16.2 summarizes port A data register read/write operations.

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• PADRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 DR PA9 DR PA8 DR PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR Bit Bit Name Initial Value R/W Description 15 PA15DR 0 R/W See table 16.2.

14 PA14DR 0 R/W

13 PA13DR 0 R/W

12 PA12DR 0 R/W

11 PA11DR 0 R/W

10 PA10DR 0 R/W

9 PA9DR 0 R/W

8 PA8DR 0 R/W

7 PA7DR 0 R/W

6 PA6DR 0 R/W

5 PA5DR 0 R/W

4 PA4DR 0 R/W

3 PA3DR 0 R/W

2 PA2DR 0 R/W

1 PA1DR 0 R/W

0 PA0DR 0 R/W

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• PADRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRR R / W R / W R / W R / W R R / W R / W R R / W R / W DR PA8 DR PA7 DR PA6 DR - PA4 DR PA3 DR - PA1 DR PA0 DR Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PA9DR 0 R/W See table 16.2.

5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PA4DR 0 R/W See table 16.2. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 PA1DR 0 R/W See table 16.2.

Rev. 3.00 Sep. 27, 2007 Page 554 of 758 REJ09B0243-0300 Table 16.2 Port A Data Register L (PADRL) Read/Write Operations

• PADRL Bits 15 to 0 PAIORH, PAIORL Pin Function Read Write

0 General input Pin state Can write to PADRL, but it has no effect on pin

Pin state Can write to PADRL, but it has no effect on pin state

1 General output PADRL value Value written is output from pin

PADRL value Can write to PADRL, but it has no effect on pin state

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16.1.3 Port A Port Register L (PAPRL)

PAPRL is a 16-bit read-only register that always return the states of the pins regardless of the PFC setting. Bits PA15PR to PA0PR correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125. Bits PA9PR to PA6PR, PA4PR, PA3PR, PA1PR, and PA0PR correspond to pins PA9 to PA6, PA4, PA3, PA1, and PA0, respectively (multiplexed functions omitted here) in the SH7124.

• PAPRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR PA15 PR PA14 PR PA13 PR PA12 PR PA11 PR PA10 PR PA9 PR PA8 PR PA7 PR PA6 PR PA5 PR PA4 PR PA3 PR PA2 PR PA1 PR PA0 PR Bit Bit Name Initial Value R/W Description

15 PA15PR Pin state R

14 PA14PR Pin state R

The pin state is returned regardless of the PFC setting. These bits cannot be modified.

13 PA13PR Pin state R

12 PA12PR Pin state R

11 PA11PR Pin state R

10 PA10PR Pin state R

9 PA9PR Pin state R

8 PA8PR Pin state R

7 PA7PR Pin state R

6 PA6PR Pin state R

5 PA5PR Pin state R

4 PA4PR Pin state R

3 PA3PR Pin state R

2 PA2PR Pin state R

1 PA1PR Pin state R

0 PA0PR Pin state R

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• PAPRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR PR PA8 PR PA7 PR PA6 PR - PA4 PR PA3 PR - PA1 PR PA0 PR Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

The pin state is returned regardless of the PFC setting. These bits cannot be modified. 5  0 R Reserved This bit is always read as 0. The write value should always be 0. The pin state is returned regardless of the PFC setting. These bits cannot be modified. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. The pin state is returned regardless of the PFC setting. These bits cannot be modified.

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16.2 Port B

Port B in the SH7125 is an input/output port with the five pins shown in figure 16.3. PB5 (I/O)/IRQ3 (input)/TIC5U (input) PB1 (I/O)/TIC5W (input) PB3 (I/O)/IRQ1 (input)/POE1 (input)/TIC5V (input) PB2 (I/O)/IRQ0 (input)/POE0 (input) PB16 (I/O)/POE3 (input) Port B Figure 16.3 Port B (SH7125) Port B in the SH7124 is an input/output port with the three pins shown in figure 16.4. PB5 (I/O)/IRQ3 (input)/TIC5U (input) PB1 (I/O)/TIC5W (input) PB3 (I/O)/IRQ1 (input)/POE1 (input)/TIC5V (input) Port B Figure 16.4 Port B (SH7124)

16.2.1 Register Descriptions

Port B is a 5-bit input/output port in the SH7125 and a 3-bit input/output port in the SH7124. Port B has the following register. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.3 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Port B data register H PBDRH R/W H'0000 H'FFFFD180 8, 16, 32 Port B data register L PBDRL R/W H'0000 H'FFFFD182 8, 16 Port B port register H PBPRH R  H'FFFFD19C 8, 16, 32 Port B port register L PBPRL R  H'FFFFD19E 8, 16

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16.2.2 Port B Data Registers H and L (PBDRH and PBDRL)

PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. Bits PB16DR, PB5DR, and PB3DR to PB1DR correspond to pins PB16, PB5, and PB3 to PB1, respectively (multiplexed functions omitted here) in the SH7125. Bits PB5DR, PB3DR, and PB1DR correspond to pins PB5, PB3, and PB1, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PBDRH or PBDRL, that value is output directly from the pin, and if PBDRH or PBDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PBDRH or PBDRL is read, the pin state, not the register value, is returned directly. If a value is written to PBDRH or PBDRL, although that value is written into PBDRH or PBDRL, it does not affect the pin state. Table 16.4 summarizes port B data register read/write operations.

• PBDRH (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRR R / W DR Bit Bit Name Initial Value R/W Description 15 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PB16DR 0 R/W See table 16.4.

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• PBDRH (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15 to 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.
• PBDRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R R / W R / W R / W R DR - PB3 DR PB2 DR PB1 DR - Bit Bit Name Initial Value R/W Description 15 to 6 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PB5DR 0 R/W See table 16.4. 4 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 PB3DR 0 R/W See table 16.4.

2 PB2DR 0 R/W

1 PB1DR 0 R/W

0 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

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• PBDRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R R / W R R / W R DR - PB3 DR - PB1 DR - Bit Bit Name Initial Value R/W Description 15 to 6 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PB5DR 0 R/W See table 16.4. 4 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 PB3DR 0 R/W See table 16.4. 2 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 PB1DR 0 R/W See table 16.4. 0 — 0 R Reserved This bit is always read as 0. The write value should always be 0. Table 16.4 Port B Data Register (PBDR) Read/Write Operations
• PBDRH Bit 0 and PBDRL Bits 5 and 3 to 1 PBIOR Pin Function Read Write

0 General input Pin state Can write to PBDRH and PBDRL, but it has no

Pin state Can write to PBDRH and PBDRL, but it has no effect on pin state

1 General output PBDRH or

Value written is output from pin Other than general output PBDRH or PBDRL value Can write to PBDRH and PBDRL, but it has no effect on pin state

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16.2.3 Port B Port Registers H and L (PBPRH and PBPRL)

PBPRH and PBPRL are 16-bit read-only registers that always return the states of the pins regardless of the PFC setting. Bits PB16PR, PB5PR, and PB3PR to PB1PR correspond to pins PB16, PB5, and PB3 to PB31, respectively (multiplexed functions omitted here) in the SH7125. Bits PB5PR, PB3PR, and PB1PR correspond to pins PB5, PB3, and PB1, respectively (multiplexed functions omitted here) in the SH7124.

• PBPRH (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 000000000000000 * RRRRRRRRRRRRRRRR PR Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PB16PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified.
• PBPRH (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial Value R/W Description 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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• PBPRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000 * 0 *** 0 RRRRRRRRRRRRRRRR PR - PB3 PR PB2 PR PB1 PR - Bit Bit Name Initial Value R/W Description 15 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PB5PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified. 4  0 R Reserved This bit is always read as 0. The write value should always be 0.

3 PB3PR Pin state R

2 PB2PR Pin state R

The pin state is returned regardless of the PFC setting. These bits cannot be modified.

1 PB1PR Pin state R

0  0 R Reserved This bit is always read as 0. The write value should always be 0.

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• PBPRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000 * 0 * 0 * 0 RRRRRRRRRRRRRRRR PR - PB3 PR - PB1 PR - Bit Bit Name Initial Value R/W Description 15 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PB5PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified. 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 PB3PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 PB1PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified. 0  0 R Reserved This bit is always read as 0. The write value should always be 0.

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16.3 Port E

Port E in the SH7125 is an input/output port with the 16 pins shown in figure 16.5. PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) PE10 (I/O)/TIOC3C (I/O) PE9 (I/O)/TIOC3B (I/O) PE8 (I/O)/TIOC3A (I/O) PE7 (I/O)/TIOC2B (I/O) PE6 (I/O)/TIOC2A (I/O)/SCK1 (I/O) PE5 (I/O)/TIOC1B (I/O)/TXD1 (output) PE4 (I/O)/TIOC1A (I/O)/RXD1 (input) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Port E Figure 16.5 Port E (SH7125)

Rev. 3.00 Sep. 27, 2007 Page 565 of 758 REJ09B0243-0300 Port E in the SH7124 is an input/output port with the 12 pins shown in figure 16.6. PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) PE10 (I/O)/TIOC3C (I/O) PE9 (I/O)/TIOC3B (I/O) PE8 (I/O)/TIOC3A (I/O) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Port E Figure 16.6 Port E (SH7124)

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16.3.1 Register Descriptions

Port E is a 16-bit input/output port in the SH7125 and a 12-bit input/output port in the SH7124. Port E has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.5 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Port E data register L PEDRL R/W H'0000 H'FFFFD302 8, 16 Port E port register L PEPRL R  H'FFFFD31E 8, 16

16.3.2 Port E Data Register L (PEDRL)

PEDRL is a 16-bit readable/writable register that stores port E data. Bits PE15DR to PE0DR correspond to pins PE15 to PE0 (multiplexed functions omitted here) in the SH7125. Bits PE15DR to PE8DR and PE3DR to PE0DR correspond to pins PE15 to PE8 and PE3 to PE0, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PEDRL, that value is output directly from the pin, and if PEDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRL, although that value is written into PEDRL, it does not affect the pin state. Table 16.6 summarizes port E data register read/write operations.

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• PEDRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR Bit Bit Name Initial Value R/W Description 15 PE15DR 0 R/W See table 16.6.

14 PE14DR 0 R/W

13 PE13DR 0 R/W

12 PE12DR 0 R/W

11 PE11DR 0 R/W

10 PE10DR 0 R/W

9 PE9DR 0 R/W

8 PE8DR 0 R/W

7 PE7DR 0 R/W

6 PE6DR 0 R/W

5 PE5DR 0 R/W

4 PE4DR 0 R/W

3 PE3DR 0 R/W

2 PE2DR 0 R/W

1 PE1DR 0 R/W

0 PE0DR 0 R/W

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• PEDRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR ---- PE3 DR PE2 DR PE1 DR PE0 DR Bit Bit Name Initial Value R/W Description 15 PE15DR 0 R/W See table 16.6.

7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 PE3DR 0 R/W See table 16.6. Table 16.6 Port E Data Register L (PEDRL) Read/Write Operations

• PEDRL Bits 15 to 0 PEIOR Pin Function Read Write

0 General input Pin state Can write to PEDRL, but it has no effect on pin

Pin state Can write to PEDRL, but it has no effect on pin state

1 General output PEDRL value Value written is output from pin

PEDRL value Can write to PEDRL, but it has no effect on pin state

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16.3.3 Port E Port Register L (PEPRL)

PEPRL is a 16-bit read-only register that always returns the states of the pins regardless of the PFC setting. Bits PE15PR to PE0PR correspond to pins PE15 to PE0 (multiplexed functions omitted here) in the SH7125. Bits PE15PR to PE8PR and PE3PR to PE0PR correspond to pins PE15 to PE8 and PE3 to PE0, respectively (multiplexed functions omitted here) in the SH7124.

• PEPRL (SH7125) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR PE15 PR PE14 PR PE13 PR PE12 PR PE11 PR PE10 PR PE9 PR PE8 PR PE7 PR PE6 PR PE5 PR PE4 PR PE3 PR PE2 PR PE1 PR PE0 PR Bit Bit Name Initial Value R/W Description

15 PE15PR Pin state R

14 PE14PR Pin state R

The pin state is returned regardless of the PFC setting. These bits cannot be modified.

13 PE13PR Pin state R

12 PE12PR Pin state R

11 PE11PR Pin state R

10 PE10PR Pin state R

9 PE9PR Pin state R

8 PE8PR Pin state R

7 PE7PR Pin state R

6 PE6PR Pin state R

5 PE5PR Pin state R

4 PE4PR Pin state R

3 PE3PR Pin state R

2 PE2PR Pin state R

1 PE1PR Pin state R

0 PE0PR Pin state R

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• PEPRL (SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR PE15 PR PE14 PR PE13 PR PE12 PR PE11 PR PE10 PR PE9 PR PE8 PR ---- PE3 PR PE2 PR PE1 PR PE0 PR Bit Bit Name Initial Value R/W Description

The pin state is returned regardless of the PFC setting. These bits cannot be modified. 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. The pin state is returned regardless of the PFC setting. These bits cannot be modified.

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16.4 Port F

Port F in the SH7125 and SH7124 is an input-only port with the eight pins shown in figure 16.7. PF1 (input)/AN1 (input) PF3 (input)/AN3 (input) PF7 (input)/AN7 (input) PF5 (input)/AN5 (input) PF6 (input)/AN6 (input) PF4 (input)/AN4 (input) PF2 (input)/AN2 (input) PF0 (input)/AN0 (input) Port F Figure 16.7 Port F (SH7125, SH7124)

16.4.1 Register Descriptions

Port F is an 8-bit input-only port in the SH7125 and SH7124. Port F has the following register. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.7 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Port F data register L PFDRL R  H'FFFFD382 8, 16

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16.4.2 Port F Data Register L (PFDRL)

The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits PF7DR to PF0DR correspond to pins PF7 to PF0 (multiplexed functions omitted here) in the SH7125 and SH7124. Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read. Table 16.8 summarizes port F data register L read/write operations.

• PFDRL (SH7125, SH7124) Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR 00000000 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 PF7DR Pin state R See table 16.8.

6 PF6DR Pin state R

5 PF5DR Pin state R

4 PF4DR Pin state R

3 PF3DR Pin state R

2 PF2DR Pin state R

1 PF1DR Pin state R

0 PF0DR Pin state R

Table 16.8 Port F Data Register L (PFDRL) Read/Write Operations

• PFDRL Bits 7 to 0 Pin Function Read Write General input Pin state Ignored (no effect on pin state) ANn input 1 Ignored (no effect on pin state)

Rev. 3.00 Sep. 27, 2007 Page 573 of 758 REJ09B0243-0300 Section 17 Flash Memory This LSI has 128-Kbyte, 64-Kbyte, or 32-Kbyte on-chip flash memory. The flash memory has the following features.

17.1 Features

• Capacitance SH71253, SH71243: 128 Kbytes SH71252, SH71242: 64 Kbytes SH71241: 32 Kbytes
• Two on-board programming modes and one off-board programming mode  On-board programming modes Boot Mode : This mode is a program mode that uses an on-chip SCI interface. The user MAT can be programmed. This mode can automatically adjust the bit rate between the host and this LSI. User Program Mode : The user MAT can be programmed by using the optional interface. This mode cannot be used in 32-Kbyte on-chip flash memory version.  Off-board programming mode This mode uses the dedicated socket adapter and PROM programmer. The user MAT can be programmed.
• Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. The user branch is also supported.  User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition.
• Protection modes There are two protection modes. Software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended.

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• Programming/erasing time The flash memory programming time is tP ms (Typ.) in 128-byte simultaneous programming and tP/128 ms per byte. The erasing time is tE s (Typ.) per block.
• Number of programming The number of flash memory programming can be up to NWEC times.
• Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 40 MHz (P φ).

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17.2 Overview

17.2.1 Block Diagram

User MAT: 128 kbytes 64 kbytes 32 kbytesOperating mode Module bus FWE pin Mode pins Internal address bus Internal data bus (32 bits) [Legend] FCCS: Flash code control and status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FTDAR: Flash transfer destination address register Figure 17.1 Block Diagram of Flash Memory

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17.2.2 Operating Mode

When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 17.2. For the setting of each mode pin and the FWE pin, see tables 17.1 to 17.4.

• Flash memory can be read in user mode, but cannot be programmed or erased.
• Flash memory can be read, programmed, or erased on the board only in user program mode and boot mode. Reset state User mode User program mode Boot mode On-board programming mode FWE = 0 FWE = 1 RES = 0 User mode settingRES = 0 User program mode settin g Boot mode sett ing RES = 0 Figure 17.2 Mode Transition of Flash Memory Table 17.1 Relationship between FWE and MD Pins and Operating Modes Pin Reset State User Mode User Program Mode Boot Mode RES 0 1 1 1 FWE 0/1 0 1 1 MD1 0/1 1 1 0

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17.2.3 Mode Comparison

The comparison table of programming and erasing related items about boot mode and user program mode is shown in table 17.2. Table 17.2 Comparison of Programming Modes On-Board Programming Programming/erasing environment Boot Mode User Program Mode * Off-Board Programming Programming/ erasing enable MAT User MAT User MAT User MAT Programming/ erasing control Command method Programming/erasing interface All erasure Possible (Automatic) Possible Possible (Automatic) Block division erasure Possible * Possible Impossible Program data transfer From host via SCI From optional device via RAM Via programmer User branch function Not possible Possible Impossible Reset initiation MAT Embedded program storage MAT User MAT Embedded program storage MAT Transition to user mode Mode setting change and reset FWE setting change  Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Cannot be used in 32-kbyte on-chip flash memory version.

• The user MAT is all erased in boot mode. Then, the user MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state.

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17.2.4 Flash Memory Configuration

This LSI's flash memory is configured by the 128-Kbyte, 64-Kbyte, or 32-Kbyte user MAT. <User MAT> Address H'00000000 Address H'0001FFFF (when the size of the user MAT is 128 kbytes) Address H'0000FFFF (when the size of the user MAT is 64 kbytes) Address H'00007FFF (when the size of the user MAT is 32 kbytes) 128 kbytes, 64 kbytes, or 32 kbytes

• 128KB SH71253 SH71243
• 64KB SH71252 SH71242
• 32KB SH71241 Figure 17.3 Flash Memory Configuration

17.2.5 Block Division

The user MAT is divided into 64 Kbytes (128-kbyte version: one block), 32 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 17.4. The user MAT can be erased in this divided- block units and the erase-block number of EB0 to EB9 is specified when erasing. Address H'00000000 Last address of 128-kbyte version H'0001FFFF 128 kbytes 64 kbytes 32 kbytes 32 kbytes 64 kbytes EB0 EB7 EB8 EB9 4 kbytes × 8 < User MAT > Erase bloc k Last address of 64-kbyte version H'0000FFFF Last address of 32-kbyte version H'00007FFF to Figure 17.4 Block Division of User MAT

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17.2.6 Programming/Erasing Interface

Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode. The overview of the procedure is as follows. For details, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Select on-chip program to be downloaded and set download destination Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) Start user procedure program for programming/erasing. End user procedure program Programming/ erasing completed? No Yes Figure 17.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR.

Rev. 3.00 Sep. 27, 2007 Page 580 of 758 REJ09B0243-0300 (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS) and the flash key code register (FKEY), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the user MAT area, which is in the middle of programming and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the on- chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 17.7.1, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively.

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17.3 Input/Output Pins

Flash memory is controlled by the pins as shown in table 17.3. Table 17.3 Pin Configuration Pin Name Symbol I/O Function Power-on reset RES Input Reset Flash programming enable FWE Input Hardware protection when programming flash memory Mode 1 MD1 Input Sets operating mode of this LSI Transmit data TXD1 (PA4) Output Serial transmit data output (used in boot mode) Receive data RXD1 (PA3) Input Serial receive data input (used in boot mode)

17.4 Register Descriptions

17.4.1 Registers

The registers/parameters, which control flash memory when the on-chip flash memory is valid are shown in table 17.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. The correspondence of operating modes and registers/parameters for use is shown in table 17.5.

Rev. 3.00 Sep. 27, 2007 Page 582 of 758 REJ09B0243-0300 Table 17.4 (1) Register Configuration Register Name Abbreviation* R/W Initial Value Address Access Size Flash code control and status register FCCS R, W * H'00 * H'80* H'FFFFCC00 8 Flash program code select register FPCS R/W H'00 H'FFFFCC01 8 Flash erase code select register FECS R/W H'00 H'FFFFCC02 8 Flash key code register FKEY R/W H'00 H'FFFFCC04 8 Flash transfer destination address register FTDAR R/W H'00 H'FFFFCC06 8 Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value, which can be read is always 0.) 2. The initial value of the FWE bit is 0 when the FWE pin goes low. The initial value of the FWE bit is 1 when the FWE pin goes high. 3. All registers can be accessed only in bytes. Table 17.4 (2) Parameter Configuration Name Abbreviation R/W Initial Value Address Access Size Download pass/fail result DPFR R/W Undefined On-chip RAM * 8, 16, 32 Flash pass/fail result FPFR R/W Undefined R0 of CPU 8, 16, 32 Flash multipurpose address area FMPAR R/W Undefined R5 of CPU 8, 16, 32 Flash multipurpose data destination area FMPDR R/W Undefined R4 of CPU 8, 16, 32 Flash erase block select FEBS R/W Undefined R4 of CPU 8, 16, 32 Flash program and erase frequency control FPEFEQ R/W Undefined R4 of CPU 8, 16, 32 Flash user branch address set parameter FUBRA R/W Undefined R5 of CPU 8, 16, 32 Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.

Rev. 3.00 Sep. 27, 2007 Page 583 of 758 REJ09B0243-0300 Table 17.5 Register/Parameter and Target Mode Download Initiali- zation Program- ming Erasure Read Programming/ erasing interface registers Programming/ erasing interface parameters

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17.4.2 Programming/Erasing Interface Registers

The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit: Initial value: R/W: 7654321 0 1 / 0 0000000 RRRRRRR ( R ) / W FWE - - FLER - - - SCO Bit Bit Name Initial Value R/W Description

7 FWE 1/0 R Flash Programming Enable

Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. 0: When the FWE pin goes low (in hardware protection state) 1: When the FWE pin goes high 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Rev. 3.00 Sep. 27, 2007 Page 585 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

4 FLER 0 R Flash Memory Error

Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 µs, which is longer than normal. 0: Flash memory operates normally Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset 1: Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 17.6.3, Error Protection. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Rev. 3.00 Sep. 27, 2007 Page 586 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 SCO 0 (R)/W Source Program Copy Operation

Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY and this operation must be in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. For interrupts during download, see section 17.7.1, Interrupts during Programming/Erasing. For the download time, see section 17.7.2, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'84000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. The mode in which the FWE pin is high must be used when using the SCO function. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is generated [Setting conditions] When all of the following conditions are satisfied and 1 is written to this bit

• FKEY is written to H'A5
• During execution in the on-chip RAM

Rev. 3.00 Sep. 27, 2007 Page 587 of 758 REJ09B0243-0300 (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRR R / W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 PPVS 0 R/W Program Pulse Single

Selects the programming program. 0: On-chip programming program is not selected [Clearing condition] When transfer is completed 1: On-chip programming program is selected (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRR R / W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Rev. 3.00 Sep. 27, 2007 Page 588 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 EPVB 0 R/W Erase Pulse Verify Block

Selects the erasing program. 0: On-chip erasing program is not selected [Clearing condition] When transfer is completed 1: On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processings cannot be executed if the key code is not written. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W K[7:0] Bit Bit Name Initial Value R/W Description 7 to 0 K[7:0] All 0 R/W Key Code Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) H'5A: Programming/erasing is enabled (A value other than H'5A enables software protection state.) H'00: Initial value

Rev. 3.00 Sep. 27, 2007 Page 589 of 758 REJ09B0243-0300 (5) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFFA000) in on-chip RAM. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TDER TDA[6:0] Bit Bit Name Initial Value R/W Description

7 TDER 0 R/W Transfer Destination Address Setting Error

This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is tested by checking whether the setting of TDA6 to TDA0 is between the range of H'02 to H'04 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'02 to H'04 as well as clearing this bit to 0. 0: Setting of TDA6 to TDA0 is normal 1: Setting of TDER and TDA6 to TDA0 is H'00 to H'01 and H'05 to H'FF and download has been aborted 6 to 0 TDA[6:0] All 0 R/W Transfer Destination Address These bits specify the download start address. A value from H'02 to H'04 can be set to specify the download start address in on-chip RAM in 2-kbyte units. A value H'00, H'01, or H'05 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. H'02: Download start address is set to H'FFFFA000 H'03: Download start address is set to H'FFFFA800 H'04: Download start address is set to H'FFFFB000 H'00, H'01, H'05 to H'7F: Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing.

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17.4.3 Programming/Erasing Interface Parameters

The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters are used in the following four items. 1. Download control 2. Initialization before programming or erasing 3. Programming 4. Erasing These items use different parameters. The correspondence table is shown in table 17.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing.

Rev. 3.00 Sep. 27, 2007 Page 591 of 758 REJ09B0243-0300 Table 17.6 Usable Parameters and Target Modes Name of Parameter Abbrevia- tion Down- load Initiali- zation Pro- gram- ming Erasure R/W Initial Value Allocation Download pass/fail result DPFR √ — — — R/W Undefined On-chip RAM* Flash pass/fail result FPFR — √ √ √ R/W Undefined R0 of CPU Flash programming/ erasing frequency control FPEFEQ — √ — — R/W Undefined R4 of CPU Flash user branch address set FUBRA — √ — — R/W Undefined R5 of CPU Flash multipurpose address area FMPAR — — √ — R/W Undefined R5 of CPU Flash multipurpose data destination area FMPDR — — √ — R/W Undefined R4 of CPU Flash erase block select FEBS — — — √ R/W Undefined R4 of CPU Note: * One byte of start address of download destination specified by FTDAR (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 17.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 17.5.2 (2), Programming Procedure in User Program Mode.

Rev. 3.00 Sep. 27, 2007 Page 592 of 758 REJ09B0243-0300 Bit: Initial value: R/W: 7654321 0 R/W R/W R/W R/W R/W R/W R/W R/W ----- S S F K S F Bit Bit Name Initial Value R/W Description 7 to 3  Undefined R/W Unused Return 0.

2 SS Undefined R/W Source Select Error Detect

The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. 0: Download program can be selected normally 1: Download error occurs (Multi-selection or program which is not mapped is selected)

1 FK Undefined R/W Flash Key Register Error Detect

Returns the check result whether the value of FKEY is set to H'A5. 0: FKEY setting is normal (FKEY = H'A5) 1: FKEY setting is abnormal (FKEY = value other than H'A5)

0 SF Undefined R/W Success/Fail

Returns the result whether download has ended normally or not. 0: Downloading on-chip program has ended normally (no error) 1: Downloading on-chip program has ended abnormally (error occurs)

Rev. 3.00 Sep. 27, 2007 Page 593 of 758 REJ09B0243-0300 (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 21.3.1, Clock Timing. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Rev. 3.00 Sep. 27, 2007 Page 594 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 31 to  Undefined R/W Unused Return 0. 15 to 0 F15 to F0 Undefined R/W Frequency Set Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency, which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows.  The number to three decimal places of 28.882 is rounded and the value is thus 28.88.  The formula that 28.88 × 100 = 2888 is converted to the binary digit and B'0000, B'1011, B'0100, B'1000 (H'0B48) is set to R4. (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24 UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16 UA15 UA14 UA13 UA12 UA11 UA10 UA9 UA8 UA7 UA6 UA5 UA4 UA3 UA2 UA1 UA0

Rev. 3.00 Sep. 27, 2007 Page 595 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 31 to 0 UA31 to UA0 Undefined R/W User Branch Destination Address When the user branch is not required, address 0 (H'84000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-chip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Store general registers R8 to R15. General registers R0 to R7 are available without storing them. Moreover, the programming/erasing interface registers must not be written to in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User Branch Processing Intervals) in section 17.7.2, Other Notes.

Rev. 3.00 Sep. 27, 2007 Page 596 of 758 REJ09B0243-0300 (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 3  Undefined R/W Unused Return 0.

2 BR Undefined R/W User Branch Error Detect

Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded. 0: User branch address setting is normal 1: User branch address setting is abnormal

1 FQ Undefined R/W Frequency Error Detect

Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal Indicates whether initialization is completed normally. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs)

Rev. 3.00 Sep. 27, 2007 Page 597 of 758 REJ09B0243-0300 (3) Programming Execution When flash memory is programmed, the programming destination address and programming data on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MOA31 MOA30 MOA29 MOA28 MOA27 MOA26 MOA25 MOA24 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16 MOA15 MOA14 MOA13 MOA12 MOA11 MOA10 MOA9 MOA8 MOA7 MOA6 MOA5 MOA4 MOA3 MOA2 MOA1 MOA0

Rev. 3.00 Sep. 27, 2007 Page 598 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 31 to 0 MOA31 to MOA0 Undefined R/W MOA31 to MOA0 Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. (3.2) Flash multipurpose data destination area parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16 MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Bit Bit Name Initial Value R/W Description 31 to 0 MOD31 to MOD0 Undefined R/W MOD31 to MOD0 Store the start address of the area which stores the program data for the user MAT. The consecutive 128- byte data is programmed to the user MAT starting from the specified start address.

Rev. 3.00 Sep. 27, 2007 Page 599 of 758 REJ09B0243-0300 (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 7  Undefined R/W Unused Return 0.

6 MD Undefined R/W Programming Mode Related Setting Error Detect

Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 17.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and programming cannot be performed

Rev. 3.00 Sep. 27, 2007 Page 600 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

5 EE Undefined R/W Programming Execution Error Detect

1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed)

4 FK Undefined R/W Flash Key Register Error Detect

Returns the check result of the value of FKEY before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A) 3  Undefined R/W Unused Return 0.

2 WD Undefined R/W Write Data Address Error Detect

When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of write data address is normal 1: Setting of write data address is abnormal

1 WA Undefined R/W Write Address Error Detect

When the following items are specified as the start address of the programming destination, an error occurs.

• The programming destination address is an area other than flash memory
• The specified address is not at the 128-byte boundary (A6 to A0 are not 0) 0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal

Rev. 3.00 Sep. 27, 2007 Page 601 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description Indicates whether the program processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Rev. 3.00 Sep. 27, 2007 Page 602 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 31 to 8  Undefined R/W Unused Return 0. 7 to 0 EBS[7:0] Undefined R/W • 128-kbyte flash memory Set the erase-block number in the range from 0 to 9. 0 corresponds to the EB0 block and 9 corresponds to the EB9 block. An error occurs when a number other than 0 to 9 (H'00 to H'09) is set.

• 64-kbyte flash memory Set the erase-block number in the range from 0 to 8. 0 corresponds to the EB0 block and 8 corresponds to the EB8 block. An error occurs when a number other than 0 to 8 (H'00 to H'08) is set. (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 7  Undefined R/W Unused Return 0.

Rev. 3.00 Sep. 27, 2007 Page 603 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

6 MD Undefined R/W Erasure Mode Related Setting Error Detect

Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 17.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and erasure cannot be performed

5 EE Undefined R/W Erasure Execution Error Detect

1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. 0: Erasure has ended normally 1: Erasure has ended abnormally (erasure result is not guaranteed) Returns the check result of FKEY value before start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A)

3 EB Undefined R/W Erase Block Select Error Detect

Returns the check result whether the specified erase- block number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal

Rev. 3.00 Sep. 27, 2007 Page 604 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description 2, 1  Undefined R/W Unused Return 0. Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs)

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17.5 On-Board Programming Mode

When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has two operating modes: user program mode and boot mode. For details on the pin setting for entering each mode, see table 17.1. For details on the state transition of each mode for flash memory, see figure 17.2.

17.5.1 Boot Mode

Boot mode executes programming/erasing user MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 17.6. For details on the pin setting in boot mode, see table 17.1. Although NMI and other interrupts are ignored in boot mode, do not generate them. Host RXD1 TXD1 Control command, analysis execution software (on-chip) Flash memory On-chip RAMOn-chip SCI1 This LSI Boot programming tool and program data Control command, program data Reply response Figure 17.6 System Configuration in Boot Mode

Rev. 3.00 Sep. 27, 2007 Page 606 of 758 REJ09B0243-0300 (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI- communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 17.7. Boot mode must be initiated in the range of this system clock. Note that the internal clock division ratio of ×1/3 is not supported in boot mode. D0 D1 D2 D3 D4 D5 D6 D7Start bit Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 17.7 Automatic Adjustment Operation of SCI Bit Rate Table 17.7 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate Peripheral Clock (Pφ) Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 20 to 25 MHz 19,200 bps 20 to 25 MHz Note: The internal clock division ratio of ×1/3 is not supported in boot mode.

Rev. 3.00 Sep. 27, 2007 Page 607 of 758 REJ09B0243-0300 (2) State Transition Diagram Figure 17.8 gives an overview of the state transitions after the chip has been started up in boot mode. For details on boot mode, see section 17.8.1, Specifications of the Standard Serial Communications Interface in Boot Mode. 1. Bit-rate matching After the chip has been started up in boot mode, bit-rate matching between the SCI and the host proceeds. 2. Waiting for inquiry and selection commands The chip sends the requested information to the host in response to inquiries regarding the size and configuration of the user MAT, start addresses of the MATs, information on supported devices, etc. 3. Automatic erasure of the entire user MAT After all necessary inquiries and selections have been made and the command for transition to the programming/erasure state is sent by the host, the entire user MAT is automatically erased. 4. Waiting for programming/erasure command  On receiving the programming selection command, the chip waits for data to be programmed. To program data, the host transmits the programming command code followed by the address where programming should start and the data to be programmed. This is repeated as required while the chip is in the programming-selected state. To terminate programming, H'FFFFFFFF should be transmitted as the first address of the area for programming. This makes the chip return to the programming/erasure command waiting state from the programming data waiting state.  On receiving the erasure select command, the chip waits for the block number of a block to be erased. To erase a block, the host transmits the erasure command code followed by the number of the block to be erased. This is repeated as required while the chip is in the erasure-selected state. To terminate erasure, H'FF should be transmitted as the block number. This makes the chip return to the programming/erasure command waiting state from the erasure block number waiting state. Erasure should only be executed when a specific block is to be reprogrammed without executing a reset-start of the chip after the flash memory has been programmed in boot mode. If all desired programming is done in a single operation, such erasure processing is not necessary because all blocks are erased before the chip enters the programming/erasure/other command waiting state.  In addition to the programming and erasure commands, commands for sum checking and blank checking (checking for erasure) of the user MAT, reading data from the user MAT, and acquiring current state information are provided. Note that the command for reading from the user MAT can only read data that has been programmed after automatic erasure of the entire user MAT.

Rev. 3.00 Sep. 27, 2007 Page 608 of 758 REJ09B0243-0300 Start in boot mode (reset in boot mode) Erasure of entire user MAT and user boot MAT Bit rate matching Wait for inquiry/selection command Wait for programming/erasure command Execute processing in response to inquiry/ selection command Execute processing in response to read/ check command Wait for erasure block number Wait for programming data Transmission of programming data by the host Erasure block specification Reception of inquiry/selection command Response to inquiry/selection command Reception of read/check command Response to command Programming complete Reception of programming select command Erasure complete Reception of erasure select command (Bit rate matching) Reception of H'00, …, H'00 Reception of H'55 Figure 17.8 State Transitions in Boot Mode

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17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version)

The user MAT can be programmed/erased in user program mode. Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 17.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 µs. For details on the programming procedure, see the description in section 17.5.2 (2), Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in section 17.5.2 (3), Erasing Procedure in User Program Mode. When programming, program data is prepared FWE = 1 ? Programming/erasing procedure program is transferred to the on-chip RAM and executed Yes No Programming/erasing start Programming/erasing end 1. Inputting high level to the FWE pin sets the FWE bit to 1. 2. Programming/erasing is executed only in the on-chip RAM. 3. After programming/erasing is finished, low level must be input to the FWE pin for protection. Figure 17.9 Programming/Erasing Overview Flow

Rev. 3.00 Sep. 27, 2007 Page 611 of 758 REJ09B0243-0300 (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 17.11. Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download DPFR = 0? Yes No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting + 32 Yes End programming procedure program FPFR = 0? No Initialization error processing Clear FKEY to 0 Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 Yes FPFR = 0? No Clear FKEY and programming error processing Yes Required data programming is completed? No Set FKEY to H'5A Clear FKEY to 0 (2.1) (2.2) (2.4) (2.5) (2.6) (2.7) (2.8) (2.9) (2.10) (2.11) (2.12) (2.13) (2.14) (2.3) DownloadInitialization Programming Start programming procedure program Figure 17.11 Programming Procedure The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (I φ), a bus clock (Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing.

Rev. 3.00 Sep. 27, 2007 Page 612 of 758 REJ09B0243-0300 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is set to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be set to H'84000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied.

• H'A5 is written to FKEY.
• The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be set to H'84000000. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1.
• The user MAT space is switched to the on-chip program storage area.
• After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting to the on-chip RAM address specified by FTDAR.
• The SCO bits in FCCS, FPCS, and FECS are cleared to 0.
• The return value is set to the DPFR parameter.

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• After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. In the download processing, the values of the general registers of the CPU are retained. During the download processing, interrupts must not be generated. For details on the relationship between download and interrupts, see section 17.7.1, Interrupts during Programming/Erasing. Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below.
• Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below.
• If the value of the DPFR parameter is the same as before downloading (e.g. H’FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR.
• If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 21.3.1, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in section 17.4.3 (2.1), Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU).

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• The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in section 17.4.3 (2.2), Flash user branch address setting parameter (FUBRA: general register R5 of CPU). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L #DLTOP+32,R1 ; Set entry address to R1 JSR @R1 ; Call initialization routine NOP
• The general registers other than R0 are saved in the initialization program.
• R0 is a return value of the FPFR parameter.
• Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM.
• Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is checked. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4.
• FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value

Rev. 3.00 Sep. 27, 2007 Page 615 of 758 REJ09B0243-0300 parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80.

• FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call programming routine NOP  The general registers other than R0 are saved in the programming program.  R0 is a return value of the FPFR parameter.  Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is checked. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128- byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 µs.

Rev. 3.00 Sep. 27, 2007 Page 616 of 758 REJ09B0243-0300 (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 17.12. Start erasing procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download DPFR = 0? Yes No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting + 32 Yes End erasing procedure program FPFR = 0 ? No Initialization error processing Clear FKEY to 0 Set FEBS parameter Erasing JSR FTDAR setting + 16 Yes FPFR = 0 ? No Clear FKEY and erasing error processing Yes Required block erasing is completed? No Set FKEY to H'5A Clear FKEY to 0 (3.1) (3.2) (3.3) (3.4) (3.5) (3.6) DownloadInitialization Erasing Figure 17.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (I φ), a bus clock (Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 17.10.

Rev. 3.00 Sep. 27, 2007 Page 617 of 758 REJ09B0243-0300 A single divided block is erased by one erasing processing. For block divisions, see figure 17.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in section 17.5.2 (2), Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call erasing routine NOP  The general registers other than R0 are saved in the erasing program.  R0 is a return value of the FPFR parameter.  Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is checked. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 µs.

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17.6 Protection

There are three kinds of flash memory program/erase protection: hardware, software, and error protection.

17.6.1 Hardware Protection

Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Table 17.8 Hardware Protection Function to be Protected Item FWE-pin protection The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. — √ Reset/standby protection

• A power-on reset (including a power-on reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state.
• Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. √ √

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17.6.2 Software Protection

Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 17.9 Software Protection Function to be Protected Item Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. √ √ Protection by FKEY Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. √ √

17.6.3 Error Protection

Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. The FLER bit is set to 1 in the following conditions:

• When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch)
• When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset.

Rev. 3.00 Sep. 27, 2007 Page 620 of 758 REJ09B0243-0300 Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 µs. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 17.13 shows transitions to and from the error protection state. Reset or standby (Hardware protection)Program mode Erase mode Error protection mode Error protection mode (Software standby) Read disabled Programming/erasing enabled FLER = 0 Read enabled Programming/erasing disabled FLER = 0 Read enabled Programming/erasing disabled FLER = 1 Read disabled Programming/erasing disabled FLER = 1 RES = 0 Error occurred Error occ urred (Softw are stand by) RES = 0 Software standby mode Cancel software standby mode RES = 0 Programming/erasing interface register is in its initial state. Programming/erasing interface register is in its initial state. Figure 17.13 Transitions to and from Error Protection State

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17.7 Usage Notes

17.7.1 Interrupts during Programming/Erasing

(1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a value other than H'84000000, the interrupt vector table is placed in the user MAT on setting H'84000000 to VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 17.14 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. n n+1 n+2 n+3 n+4 Fetch Decoding Execution Execution Execution (a) (b) CPU cycle CPU operation for instruction that sets SCO bit to 1 (a) When the interrupt is accepted at the (n + 1) cycle or before After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle or later The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated. Interrupt acceptance Figure 17.14 Timing of Contention between SCO Download Request and Interrupt Request 2. Generation of interrupt requests during downloading Ensure that interrupts are not generated during downloading that is initiated by the SCO bit.

Rev. 3.00 Sep. 27, 2007 Page 622 of 758 REJ09B0243-0300 (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, the user MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flash- memory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform download of the on-chip program by an SCO request or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 µs to reduce the damage to flash memory.

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17.7.2 Other Notes

1. Download Time of On-Chip Program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum. 2. User Branch Processing Intervals The intervals for executing the user branch processing differ in programming and erasing. The processing phase also differs. Table 17.10 lists the maximum interval for initiating the user branch processing when the CPU clock frequency is 50 MHz. Table 17.10 Initiation Intervals of User Branch Processing Processing Name Maximum Interval Programming Approximately 4 ms Erasing Approximately 25 ms However, when operation is done with CPU clock of 50 MHz, maximum value of the time until first user branch processing is as shown in table 17.11. Table 17.11 Initial User Branch Processing Time Processing Name Max. Programming Approximately 4 ms Erasing Approximately 25 ms 3. State in which Interrupts are ignored In the following modes or period, interrupt requests are ignored; they are not executed and the interrupt sources are not retained.  Boot mode

Rev. 3.00 Sep. 27, 2007 Page 624 of 758 REJ09B0243-0300 4. Compatibility with Progr amming/Erasing Program of Conventional F-ZTAT SH Microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 5. Monitoring Runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required.

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17.8 Supplementary Information

17.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode

The boot program activated in boot mode communicates with the host via the on-chip SCI of the LSI. The specifications of the serial communications interface between the host and the boot program are described below.

• States of the boot program The boot program has three states. 1. Bit-rate matching state In this state, the boot program adjusts the bit rate to match that of the host. When the chip starts up in boot mode, the boot program is activated and enters the bit-rate matching state, in which it receives commands from the host and adjusts the bit rate accordingly. After bit-rate matching is complete, the boot program proceeds to the inquiry-and-selection state. 2. Inquiry-and-selection state In this state, the boot program responds to inquiry commands from the host. The device, clock mode, and bit rate are selected in this state. After making these selections, the boot program enters the programming/erasure state in response to the transition-to-programming/erasure state command. The boot program transfers the erasure program to RAM and executes erasure of the user MAT before it enters the programming/erasure state. 3. Programming/erasure state In this state, programming/erasure are executed. The boot program transfers the program for programming/erasure to RAM in line with the command received from the host and executes programming/erasure. It also performs sum checking and blank checking as directed by the respective commands. Figure 17.15 shows the flow of processing by the boot program.

Rev. 3.00 Sep. 27, 2007 Page 626 of 758 REJ09B0243-0300 Wait for programming/erasure selection Erase user MAT Bit rate matching Wait for inquiry and selection Selection processing Inquiry processing Programming processing Erasure processing Checking processing Programming Erasure Checking Reset Inquiry Enter programming/erasure state Selection Bit rate matching state Inquiry-and-selection state Programming/erasure state Figure 17.15 Flow of Processing by the Boot Program

• Bit-rate matching state In bit-rate matching, the boot program measures the low-level intervals in a signal carrying H'00 data that is transmitted by the host, and calculates the bit rate from this. The bit rate can be changed by the new-bit-rate selection command. On completion of bit-rate matching, the boot program goes to the inquiry and selection state. The sequence of processing in bit-rate matching is shown in figure 17.16.

Rev. 3.00 Sep. 27, 2007 Page 627 of 758 REJ09B0243-0300 Host Boot program H'00 (max. 30 times) H'00 (bit rate matching complete) H'55 H'E6 (response) H'FF (error) Measures the length of one bit Figure 17.16 Sequence of Bit-Rate Matching

• Communications protocol Formats in the communications protocol between the host and boot program after completion of the bit-rate matching are as follows. 1. One-character command or one-character response A command or response consisting of a single character used for an inquiry or the ACK code indicating normal completion. 2. n-character command or n-character response A command or response that requires n bytes of data, which is used as a selection command or response to an inquiry. The length of programming data is treated separately below. 3. Error response Response to a command in case of an error: two bytes, consisting of the error response and error code. 4. 128-byte programming command The command itself does not include data-size information. The data length is known from the response to the command for inquiring about the programming size. 5. Response to a memory reading command This response includes four bytes of size information.

Rev. 3.00 Sep. 27, 2007 Page 628 of 758 REJ09B0243-0300 Command or response Data Data (n bytes)Address Size Checksum Command or response Command Error code Error response Checksum DataData size Response Checksum One-character command or one-character response n-character command or n-character response Error response 128-byte programming command Response to memory read command Figure 17.17 Formats in the Communications Protocol  Command (1 byte): Inquiry, selection, programming, erasure, checking, etc.  Response (1 byte): Response to an inquiry  Size (one or two bytes): The length of data for transfer, excluding the command/response code, size, and checksum.  Data (n bytes): Particular data for the command or response  Checksum (1 byte): Set so that the total sum of byte values from the command code to the checksum and change lower one byte to H'00.  Error response (1 byte): Error response to a command  Error code (1 byte): Indicates the type of error.  Address (4 bytes): Address for programming  Data (n bytes): Data to be programmed. "n" is known from the response to the command used to inquire about the programming size.  Data size (4 bytes): Four-byte field included in the response to a memory reading command.

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• Inquiry-and-Selection State In this state, the boot program returns information on the flash ROM in response to inquiry commands sent from the host, and selects the device, clock mode, and bit rate in response to the respective selection commands. The inquiry and selection commands are listed in table 17.12. Table 17.12 Inquiry and Selection Commands Command Command Name Function H'20 Inquiry on supported devices Requests the device codes and their respective boot program names. H'10 Device selection Selects a device code. H'21 Inquiry on clock modes Requests the number of available clock modes and their respective values. H'11 Clock-mode selection Selects a clock mode. H'22 Inquiry on frequency multipliers Requests the number of clock signals for which frequency multipliers and divisors are selectable, the number of multiplier and divisor settings for the respective clocks, and the values of the multipliers and divisors. H'23 Inquiry on operating frequency Requests the minimum and maximum values for operating frequency of the main clock and peripheral clock. H'25 Inquiry on user MATs Requests the number of user MAT areas along with their start and end addresses. H'26 Inquiry on erasure blocks Requests the number of erasure blocks along with their start and end addresses. H'27 Inquiry on programming size Requests the unit of data for programming. H'3F New bit rate selection Selects a new bit rate. H'40 Transition to programming/erasure state On receiving this command, the boot program erases the user MAT and enters the programming/erasure state. H'4F Inquiry on boot program state Requests information on the current state of boot processing. The selection commands should be sent by the host in this order: device selection (H'10), clock- mode selection (H'11), new bit rate selection (H'3F). These commands are mandatory. If the same selection command is sent two or more times, the command that is sent last is effective.

Rev. 3.00 Sep. 27, 2007 Page 630 of 758 REJ09B0243-0300 All commands in the above table, except for the boot program state inquiry command (H'4F), are valid until the boot program accepts the transition-to-programming/erasure state command (H'40). That is, until the transition command is accepted, the host can continue to send commands listed in the above table until it has made the necessary inquiries and selections. The host can send the boot program state inquiry command (H'4F) even after acceptance of the transition-to- programming/erasure state command (H'40) by the boot program. (1) Inquiry on supported devices In response to the inquiry on supported devices, the boot program returns the device codes of the devices it supports and the product names of their respective boot programs. Command H'20  Command H'20 (1 byte): Inquiry on supported devices Response H'30 Size No. of devices Number of characters Device code Product name S U M  Response H'30 (1 byte): Response to the inquiry on supported devices  Size (1 byte): The length of data for transfer excluding the command code, this field (size), and the checksum. Here, it is the total number of bytes taken up by the number of devices, number of characters, device code, and product name fields.  Number of devices (1 byte): The number of device models supported by the boot program embedded in the microcomputer.  Number of characters (1 byte): The number of characters in the device code and product name fields.  Device code (4 bytes): Device code of a supported device (ASCII encoded)  Product name (n bytes): Product code of the boot program (ASCII encoded)  SUM (1 byte): Checksum This is set so that the total sum of all bytes from the command code to the checksum is H'00.

Rev. 3.00 Sep. 27, 2007 Page 631 of 758 REJ09B0243-0300 (2) Device selection In response to the device selection command, the boot program sets the specified device as the selected device. The boot program will return the information on the selected device in response to subsequent inquiries. Command H'10 Size Device code SUM  Command H'10 (1 byte): Device selection  Size (1 byte): Number of characters in the device code (fixed at 4)  Device code (4 bytes): A device code that was returned in response to an inquiry on supported devices (ASCII encoded)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to device selection This is the ACK code and is returned when the specified device code matches one of the supported devices. Error response H'90 ERROR  Error response H'90 (1 byte): Error response to device selection  ERROR (1 byte): Error code H'11: Sum-check error H'21: Non-matching device code (3) Inquiry on clock modes In response to the inquiry on clock modes, the boot program returns the number of available clock modes. Command H'21  Command H'21 (1 byte): Inquiry on clock modes Response H'31 Size Mode … SUM

Rev. 3.00 Sep. 27, 2007 Page 632 of 758 REJ09B0243-0300  Response H'31 (1 byte): Response to the inquiry on clock modes  Size (1 byte): The total length of the number of modes and mode data fields.  Mode (1 byte): Selectable clock mode (example: H'01 denotes clock mode 1)  SUM (1 byte): Checksum (4) Clock-mode selection In response to the clock-mode selection command, the boot program sets the specified clock mode. The boot program will return the information on the selected clock mode in response to subsequent inquiries. Command H'11 Size Mode SUM  Command H'11 (1 byte): Clock mode selection  Size (1 byte): Number of characters in the clock-mode field (fixed at 1)  Mode (1 byte): A clock mode returned in response to the inquiry on clock modes  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to clock mode selection This is the ACK code and is returned when the specified clock-mode matches one of the available clock modes. Error response H'91 ERROR  Error response H'91 (1 byte): Error response to clock mode selection  ERROR (1 byte): Error code H'11: Sum-check error H'22: Non-matching clock mode

Rev. 3.00 Sep. 27, 2007 Page 633 of 758 REJ09B0243-0300 (5) Inquiry on frequency multipliers In response to the inquiry on frequency multipliers, the boot program returns information on the settable frequency multipliers or divisors. Command H'22  Command H'22 (1 byte): Inquiry on frequency multipliers Response H'32 Size No. of frequency types No. of multipliers Multiplier … S U M  Response H'32 (1 byte): Response to the inquiry on frequency multipliers  Size (1 byte): The total length of the number of frequency types, number of multipliers, and multiplier fields.  Number of frequency types (1 byte): The number of operating clocks for which multipliers can be selected (for example, if frequency multiplier settings can be made for the frequencies of the main and peripheral operating clocks, the value should be H'02).  Number of multipliers (1 byte): The number of multipliers selectable for the operating frequency of the main or peripheral modules  Multiplier (1 byte): Multiplier: Numerical value in the case of frequency multiplication (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2) As many multiplier fields are included as there are multipliers or divisors, and combinations of the number of frequency types are repeated as many times as there are operating clocks.  SUM (1 byte): Checksum

Rev. 3.00 Sep. 27, 2007 Page 634 of 758 REJ09B0243-0300 (6) Inquiry on operating frequency In response to the inquiry on operating frequency, the boot program returns the number of operating frequencies and the maximum and minimum values. Command H'23  Command H'23 (1 byte): Inquiry on operating frequency Response H'33 Size No. of frequency types Operating freq. (min) Operating freq. (max) SUM  Response H'33 (1 byte): Response to the inquiry on operating frequency  Size (1 byte): The total length of the number of frequency types, and maximum and minimum values of operating frequency fields.  Number of frequency types (1 byte): The number of operating clock frequencies required within the device. For example, the value two indicates main and peripheral operating clock frequencies.  Minimum value of operating frequency (2 bytes): The minimum frequency of a frequency- multiplied or -divided clock signal. The value in this field and in the maximum value field is the frequency in MHz to two decimal places, multiplied by 100 (for example, if the frequency is 20.00 MHz, the value multiplied by 100 is 2000, so H'07D0 is returned here).  Maximum value of operating frequency (2 bytes): The maximum frequency of a frequency- multiplied or -divided clock signal. As many pairs of minimum values are included as there are frequency types.  SUM (1 byte): Checksum

Rev. 3.00 Sep. 27, 2007 Page 635 of 758 REJ09B0243-0300 (7) Inquiry on user MATs In response to the inquiry on user MATs, the boot program returns the number of user MAT areas and their addresses. Command H'25  Command H'25 (1 byte): Inquiry on user MAT information Response H'35 Size No. of areas First address of the area Last address of the area S U M  Response H'35 (1 byte): Response to the inquiry on user MATs  Size (1 byte): The total length of the number of areas and first and last address fields.  Number of areas (1 byte): The number of user MAT areas. H'01 is returned if the entire user MAT area is continuous.  First address of the area (4 bytes)  Last address of the area (4 bytes) As many pairs of first and last address field are included as there are areas.  SUM (1 byte): Checksum (8) Inquiry on erasure blocks In response to the inquiry on erasure blocks, the boot program returns the number of erasure blocks in the user MAT and the addresses where each block starts and ends. Command H'26  Command H'26 (1 byte): Inquiry on erasure blocks Response H'36 Size No. of blocks First address of the block Last address of the block SUM

Rev. 3.00 Sep. 27, 2007 Page 636 of 758 REJ09B0243-0300  Response H'36 (1 byte): Response to the inquiry on erasure blocks  Size (2 bytes): The total length of the number of blocks and first and last address fields.  Number of blocks (1 byte): The number of erasure blocks in flash memory  First address of the block (4 bytes)  Last address of the block (4 bytes) As many pairs of first and last address data are included as there are blocks.  SUM (1 byte): Checksum (9) Inquiry on programming size In response to the inquiry on programming size, the boot program returns the size, in bytes, of the unit for programming. Command H'27  Command H'27 (1 byte): Inquiry on programming size Response H'37 Size Programming size SUM  Response H'37 (1 byte): Response to the inquiry on programming size  Size (1 byte): The number of characters in the programming size field (fixed at 2)  Programming size (2 bytes): The size of the unit for programming This is the unit for the reception of data to be programmed.  SUM (1 byte): Checksum (10) New bit rate selection In response to the new-bit-rate selection command, the boot program changes the bit rate setting to the new bit rate and, if the setting was successful, responds to the ACK sent by the host by returning another ACK at the new bit rate. The new-bit-rate selection command should be sent after clock-mode selection. Command H'3F Size Bit rate Input frequency No. of multipliers Multiplier 1 Multiplier 2 S U M

Rev. 3.00 Sep. 27, 2007 Page 637 of 758 REJ09B0243-0300  Command H'3F (1 byte): New bit rate selection  Size (1 byte): The total length of the bit rate, input frequency, number of multipliers, and multiplier fields  Bit rate (2 bytes): New bit rate The bit rate value divided by 100 should be set here (for example, to select 19200 bps, the set H'00C0, which is 192 in decimal notation).  Input frequency (2 bytes): The frequency of the clock signal fed to the boot program This should be the frequency in MHz to the second decimal place, multiplied by 100 (for example, if the frequency is 28.882 MHz, the values is truncated to the second decimal place and multiplied by 100, making 2888; so H'0B48 should be set in this field).  Number of multipliers (1 byte): The number of selectable frequency multipliers and divisors for the device. This is normally 2, which indicates the main operating frequency and the operating frequency of the peripheral modules.  Multiplier 1 (1 byte): Multiplier or divisor for the main operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2)  Multiplier 2 (1 byte): Multiplier or divisor for the peripheral operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to the new-bit-rate selection command This is the ACK code and is returned if the specified bit rate has been selected. Error response H'BF ERROR  Error response H'BF (1 byte): Error response to new bit rate selection  ERROR (1 byte): Error code H'11: Sum-check error H'24: Bit rate selection error (the specified bit rate is not selectable). H'25: Input frequency error (the specified input frequency is not within the range from the minimum to the maximum value).

Rev. 3.00 Sep. 27, 2007 Page 638 of 758 REJ09B0243-0300 H'26: Frequency multiplier error (the specified multiplier does not match an available one). H'27: Operating frequency error (the specified operating frequency is not within the range from the minimum to the maximum value). The received data are checked in the following ways. 1. Input frequency The value of the received input frequency is checked to see if it is within the range of the minimum and maximum values of input frequency for the selected clock mode of the selected device. A value outside the range generates an input frequency error. 2. Multiplier The value of the received multiplier is checked to see if it matches a multiplier or divisor that is available for the selected clock mode of the selected device. A value that does not match an available ratio generates a frequency multiplier error. 3. Operating frequency The operating frequency is calculated from the received input frequency and the frequency multiplier or divisor. The input frequency is the frequency of the clock signal supplied to the LSI, while the operating frequency is the frequency at which the LSI is actually driven. The following formulae are used for this calculation. Operating frequency = input frequency × multiplier, or Operating frequency = input frequency / divisor The calculated operating frequency is checked to see if it is within the range of the minimum and maximum values of the operating frequency for the selected clock mode of the selected device. A value outside the range generates an operating frequency error. 4. Bit rate From the peripheral operating frequency (Pφ) and the bit rate (B), the value (= n) of the clock select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate register (SCBRR) are calculated, after which the error in the bit rate is calculated. This error is checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate selection error. The following formula is use to calculate the error. Pφ × 106

Rev. 3.00 Sep. 27, 2007 Page 639 of 758 REJ09B0243-0300 When the new bit rate is selectable, the boot program returns an ACK code to the host and then makes the register setting to select the new bit rate. The host then sends an ACK code at the new bit rate, and the boot program responds to this with another ACK code, this time at the new bit rate. Acknowledge H'06  Acknowledge H'06 (1 byte): The ACK code sent by the host to acknowledge the new bit rate. Response H'06  Response H'06 (1 byte): The ACK code transferred in response to acknowledgement of the new bit rate The sequence of new bit rate selection is shown in figure 17.18. Host Boot program New bit rate setting H'06 (ACK) H'06 (ACK) at the new bit rate H'06 (ACK) at the new bit rate New bit rate setting Wait for one-bit period at the current bit rate setting Setting the new bit rate Figure 17.18 Sequence of New Bit Rate Selection

Rev. 3.00 Sep. 27, 2007 Page 640 of 758 REJ09B0243-0300 (11) Transition to the programming/erasure state In response to the transition to the programming/erasure state command, the boot program transfers the erasing program and runs it to erase any data in the user MAT. On completion of this erasure, the boot program returns the ACK code and enters the programming/erasure state. Before sending the programming selection command and data for programming, the host must select the device, clock mode, and new bit rate for the LSI by issuing the device selection command, clock-mode selection command, new-bit-rate selection command, and then initiate the transition to the programming/erasure state by sending the corresponding command to the boot program. Command H'40  Command H'40 (1 byte): Transition to programming/erasure state Response H'06  Response H'06 (1 byte): Response to the transition-to-programming/erasure state command This is returned as ACK when erasure of the user MAT has succeeded after transfer of the erasure program. Error response H'C0 H'51  Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure state command  ERROR (1 byte): Error code H'51: Erasure error (Erasure did not succeed because of an error.)

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• Command Error Command errors are generated by undefined commands, commands sent in an incorrect order, and the inability to accept a command. For example, sending the clock-mode selection command before device selection or an inquiry command after the transition-to-programming/erasure state command generates a command error. Error response H'80 H'xx  Error response H'80 (1 byte): Command error  Command H'xx (1 byte): Received command
• Order of Commands In the inquiry-and-selection state, commands should be sent in the following order. 1. Send the inquiry on supported devices command (H'20) to get the list of supported devices. 2. Select a device from the returned device information, and send the device selection command (H'10) to select that device. 3. Send the inquiry on clock mode command (H'21) to get the available clock modes. 4. Select a clock mode from among the returned clock modes, and send the clock-mode selection command (H'11). 5. After selection of the device and clock mode, send the commands to inquire about frequency multipliers (H'22) and operating frequencies (H'23) to get the information required to select a new bit rate. 6. Taking into account the returned information on the frequency multipliers and operating frequencies, send a new-bit-rate selection command (H'3F). 7. After the device and clock mode have been selected, get the information required for programming and erasure of the user MAT by sending the commands to inquire about the user MAT (H'25), erasure block (H'26), and programming size (H'27). 8. After making all necessary inquiries and the new bit rate selection, send the transition-to- programming/erasure state command (H'40) to place the boot program in the programming/erasure state.

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• Programming/Erasure State In this state, the boot program must select the form of programming corresponding to the programming-selection command and then write data in response to 128-byte programming commands, or perform erasure in block units in response to the erasure-selection and block- erasure commands. The programming and erasure commands are listed in table 17.13. Table 17.13 Programming and Erasure Commands Command Command Name Function H'43 Selection of user MAT programming Selects transfer of the program for user MAT programming. H'50 128-byte programming Executes 128-byte programming. H'48 Erasure selection Selects transfer of the erasure program. H'58 Block erasure Executes erasure of the specified block. H'52 Memory read Reads from memory. H'4B Sum checking of user MAT Executes sum checking of the user MAT. H'4D Blank checking of user MAT Executes blank checking of the user MAT. H'4F Inquiry on boot program state Requests information on the state of boot processing.
• Programming Programming is performed by issuing a programming-selection command and the 128-byte programming command. Firstly, the host issues the programming-selection command to select the MAT to be programmed and programming by the method. Next, the host issues a 128-byte programming command. 128 bytes of data for programming by the method selected by the preceding programming selection command are expected to follow the command. To program more than 128 bytes, repeatedly issue 128-byte programming commands. To terminate programming, the host should send another 128-byte programming command with the address H'FFFFFFFF. On completion of programming, the boot program waits for the next programming/erasure selection command. To then program the other MAT, start by sending the programming select command.

Rev. 3.00 Sep. 27, 2007 Page 643 of 758 REJ09B0243-0300 The sequence of programming by programming-selection and 128-byte programming commands is shown in figure 17.19. Host Boot program Programming selection (H'42, H'43) ACK 128-byte programming (address and data) ACK 128-byte programming (H'FFFFFFFF) ACK Transfer the program that performs programming ProgrammingRepeat Figure 17.19 Sequence of Programming (1) Selection of user MAT programming In response to the command for selecting programming of the user MAT, the boot program transfers the corresponding flash-writing program, i.e. the program for writing to the user MAT. Command H'43  Command H'43 (1 byte): Selects programming of the user MAT. Response H'06  Response H'06 (1 byte): Response to selection of user MAT programming This ACK code is returned after transfer of the program that performs writing to the user MAT. Error response H'C3 ERROR  Error response H'C3 (1 byte): Error response to selection of user MAT programming

Rev. 3.00 Sep. 27, 2007 Page 644 of 758 REJ09B0243-0300  ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error) (2) 128-byte programming In response to the 128-byte programming command, the boot program executes the flash-writing program transferred in response to the command to program into the user MAT. Command H'50 Address for programming Data … SUM  Command H'50 (1 byte): 128-byte programming  Address for programming (4 bytes): Address where programming starts Specify an address on a 128-byte boundary. [Example] H'00, H01, H'00, H'00: H'00010000  Programming data (n bytes): Data for programming The length of the programming data is the size returned in response to the programming size inquiry command.  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to 128-byte programming The ACK code is returned on completion of the requested programming. Error response H'D0 ERROR  Error response H'D0 (1 byte): Error response to 128-byte programming  ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address is not within the range for the selected MAT) H'53: Programming error (programming failed because of an error in programming)

Rev. 3.00 Sep. 27, 2007 Page 645 of 758 REJ09B0243-0300 The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when programming 128 bytes of data, the lowest byte of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF. To terminate programming of a given MAT, send a 128-byte programming command with the address field H'FFFFFFFF. This informs the boot program that all data for the selected MAT have been sent; the boot program then waits for the next programming/erasure selection command. Command H'50 Address for programming SUM  Command H'50 (1 byte): 128-byte programming  Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to 128-byte programming This ACK code is returned on completion of the requested programming. Error response H'D0 ERROR  Error response H'D0 (1 byte): Error response to 128-byte programming  ERROR (1 byte): Error code H'11: Sum-check error H'53: Programming error

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• Erasure Erasure is performed by issuing the erasure selection command and then one or more block erasure commands. Firstly, the host sends the erasure selection command to select erasure; after that, it sends a block erasure command to actually erase a specific block. To erase multiple blocks, send further block erasure commands. To terminate erasure, the host should send a block erasure command with the block number H'FF. After this, the boot program waits for the next programming/erasure selection command. The sequence of erasure by the erasure selection command and block erasure command is shown in figure 17.20. ACK Erasure (H'FF) Erasure selection (H'48) Erasure (block number) ACK ACK Erasure Transfer the program that performs erasure Boot programHost Repeat Figure 17.20 Sequence of Erasure

Rev. 3.00 Sep. 27, 2007 Page 647 of 758 REJ09B0243-0300 (1) Select erasure In response to the erasure selection command, the boot program transfers the program that performs erasure, i.e. erases data in the user MAT. Command H'48  Command H'48 (1 byte): Selects erasure. Response H'06  Response H'06 (1 byte): Response to selection of erasure This ACK code is returned after transfer of the program that performs erasure. Error response H'C8 ERROR  Error response H'C8 (1 byte): Error response to selection of erasure  ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error.) (2) Block erasure In response to the block erasure command, the boot program erases the data in a specified block of the user MAT. Command H'58 Size Block number SUM  Command H'58 (1 byte): Erasure of a block  Size (1 byte): The number of characters in the block number field (fixed at 1)  Block number (1 byte): Block number of the block to be erased  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to the block erasure command This ACK code is returned when the block has been erased.

Rev. 3.00 Sep. 27, 2007 Page 648 of 758 REJ09B0243-0300 Error response H'D8 ERROR  Error response H'D8 (1 byte): Error response to the block erasure command  ERROR (1 byte): Error code H'11: Sum-check error H'29: Block number error (the specified block number is incorrect.) H'51: Erasure error (an error occurred during erasure.) On receiving the command with H'FF as the block number, the boot program stops erasure processing and waits for the next programming/erasure selection command. Command H'58 Size Block number SUM  Command H'58 (1 byte): Erasure of a block  Size (1 byte): The number of characters in the block number field (fixed at 1)  Block number (1 byte): H'FF (erasure terminating code)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): ACK code to indicate response to the request for termination of erasure To perform erasure again after having issued the command with the block number specified as H'FF, execute the process from the selection of erasure.

• Memory read In response to the memory read command, the boot program returns the data from the specified address. Command H'52 Size Area First address for reading Amount to read SUM  Command H'52 (1 byte): Memory read  Size (1 byte): The total length of the area, address for reading, and amount to read fields (fixed value of 9)

Rev. 3.00 Sep. 27, 2007 Page 649 of 758 REJ09B0243-0300  Area (1 byte): H'01: User MAT An incorrect area specification will produce an address error.  Address where reading starts (4 bytes)  Amount to read (4 bytes): The amount of data to be read  SUM (1 byte): Checksum Response H'52 Amount to read Data … SUM  Response H'52 (1 byte): Response to the memory read command  Amount to read (4 bytes): The amount to read as specified in the memory read command  Data (n bytes): The specified amount of data read out from the specified address  SUM (1 byte): Checksum Error response H'D2 ERROR  Error response H'D2 (1 byte): Error response to memory read command  ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address specified for reading is beyond the range of the MAT) H'2B: Size error (the specified amount is greater than the size of the MAT, the last address for reading as calculated from the specified address for the start of reading and the amount to read is beyond the MAT area, or "0" was specified as the amount to read)

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• Sum checking of the user MAT In response to the command for sum checking of the user MAT, the boot program adds all bytes of data in the user MAT and returns the result. Command H'4B  Command H'4B (1 byte): Sum checking of the user MAT Response H'5B Size Checksum for the MAT SUM  Response H'5B (1 byte): Response to sum checking of the user MAT  Size (1 byte): The number of characters in the checksum for the MAT (fixed to 4)  Checksum for the MAT (4 bytes): Result of checksum calculation for the user MAT: the total of all data in the MAT, in byte units.  SUM (1 byte): Checksum (for the transmitted data)
• Blank checking of the user MAT In response to the command for blank checking of the user MAT, the boot program checks to see if the whole of the user MAT is blank; the value returned indicates the result. Command H'4D  Command H'4D (1 byte): Blank checking of the user MAT Response H'06  Response H'06 (1 byte): Response to blank checking of the user MAT The ACK code is returned when the whole area is blank (all bytes are H'FF). Error response H'CD H'52  Error response H'CD (1 byte): Error response to blank checking of the user MAT  Error code H'52 (1 byte): Non-erased error

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• Inquiry on boot program state In response to the command for inquiry on the state of the boot program, the boot program returns an indicator of its current state and error information. This inquiry can be made in the inquiry-and- selection state or the programming/erasure state. Command H'4F  Command H'4F (1 byte): Inquiry on boot program state Response H'5F Size STATUS ERROR SUM  Response H'5F (1 byte): Response to the inquiry regarding boot-program state  Size (1 byte): The number of characters in STATUS and ERROR (fixed at 2)  STATUS (1 byte): State of the standard boot program See table 17.14, Status Codes.  ERROR (1 byte): Error state (indicates whether the program is in normal operation or an error has occurred) ERROR = 0: Normal ERROR ≠ 0: Error See table 17.15, Error Codes.  SUM (1 byte): Checksum Table 17.14 Status Codes Code Description H'11 Waiting for device selection H'12 Waiting for clock-mode selection H'13 Waiting for bit-rate selection H'1F Waiting for transition to programming/erasure status (bit-rate selection complete) H'31 Erasing the user MAT H'3F Waiting for programming/erasure selection (erasure complete) H'4F Waiting to receive data for programming (programming complete) H'5F Waiting for erasure block specification (erasure complete)

Rev. 3.00 Sep. 27, 2007 Page 652 of 758 REJ09B0243-0300 Table 17.15 Error Codes Code Description H'00 No error H'11 Sum check error H'21 Non-matching device code error H'22 Non-matching clock mode error H'24 Bit-rate selection failure H'25 Input frequency error H'26 Frequency multiplier error H'27 Operating frequency error H'29 Block number error H'2A Address error H'2B Data length error (size error) H'51 Erasure error H'52 Non-erased error H'53 Programming error H'54 Selection processing error H'80 Command error H'FF Bit-rate matching acknowledge error

17.8.2 Areas for Storage of the Procedural Program and Data for Programming

In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be executed in other areas as long as the following conditions are satisfied. 1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. 3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been decided. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, interrupt vector

Rev. 3.00 Sep. 27, 2007 Page 653 of 758 REJ09B0243-0300 table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. 5. The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip RAM. 6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 µs must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 µs) is needed before the reset signal is released. 7. When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Tables 17.16 and 17.17 show the areas in which the program data can be stored and executed according to the operation type and mode. Table 17.16 Executable MAT Initiated Mode Operation User Program Mode Programming Table 17.17 (1) Erasing Table 17.17 (2)

Rev. 3.00 Sep. 27, 2007 Page 654 of 758 REJ09B0243-0300 Table 17.17 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT User MAT Embedded Program Storage MAT Program data storage area √ X * — — Selecting on-chip program to be downloaded √ √ √ Writing H'A5 to key register √ √ √ Writing 1 to SCO in FCCS (download) √ X √ Key register clearing √ √ √ Deciding download result √ √ √ Download error processing √ √ √ Setting initialization parameters √ √ √ Initialization √ X √ Deciding initialization result √ √ √ Initialization error processing √ √ √ Pro- gram- ming proce- dure Interrupt processing routine √ X √ Writing H'5A to key register √ √ √ Setting programming parameters √ X √ Programming √ X √ Deciding programming result √ X √ Programming error processing √ X √ Key register clearing √ X √ Note: * If the data has been transferred to on-chip RAM in advance, this area can be used.

Rev. 3.00 Sep. 27, 2007 Page 655 of 758 REJ09B0243-0300 Table 17.17 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT User MAT Embedded Program Storage MAT Selecting on-chip program to be downloaded √ √ √ Writing H'A5 to key register √ √ √ Writing 1 to SCO in FCCS (download) √ X √ Key register clearing √ √ √ Deciding download result √ √ √ Download error processing √ √ √ Setting initialization parameters √ √ √ Initialization √ X √ Deciding initialization result √ √ √ Initialization error processing √ √ √ Interrupt processing routine √ X √ Erasing proce- dure Writing H'5A to key register √ √ √ Setting erasure parameters √ X √ Erasure √ X √ Deciding erasure result √ X √ Erasing error processing √ X √ Key register clearing √ X √

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17.9 Off-Board Programming Mode

A PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-Kbyte flash memory on-chip MCU device type (F-ZTAT128DV5).

RAM0200A_010020030800 Rev. 3.00 Sep. 27, 2007 Page 657 of 758 REJ09B0243-0300 Section 18 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (L bus), enabling 8, 16, or 32-bit width access to data in the on-chip RAM. The on-chip RAM is allocated to different addresses according to each product as shown in figure 18.1. The on-chip RAM can be accessed from the CPU (via the L bus). An access from the L bus (CPU) is a 1-cycle access. In addition, the contents of the on-chip RAM are retained in sleep mode or software standby mode, and at a power-on reset or manual reset. The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control register (RAMCR). For details on the RAM control register (RAMCR), refer to section 19.3.7, RAM Control Register (RAMCR). H'FFFFA000 Page 1 8 kbytes SH7125/SH7124 (8 kbytes) H'FFFFBFFF Figure 18.1 On-chip RAM Addresses

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18.1 Usage Notes

18.1.1 Module Standby Mode Setting

RAM can be enabled/disabled by the standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 19, Power-Down Modes.

18.1.2 Address Error

When an address error in write access to the on-chip RAM occurs, the contents of the on-chip RAM may be corrupted.

18.1.3 Initial Values in RAM

After power has been supplied, initial values in RAM remain undefined until RAM is written.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 659 of 758 REJ09B0243-0300 Section 19 Power-Down Modes This LSI supports the following power-down modes: sleep mode, software standby mode, and module standby mode.

19.1 Features

• Supports sleep mode, software standby mode, and module standby mode.

19.1.1 Types of Power-Down Modes

This LSI has the following power-down modes.

• Sleep mode
• Software standby mode
• Module standby mode Table 19.1 shows the methods to make a transition from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 660 of 758 REJ09B0243-0300 Table 19.1 States of Power-Down Modes State Mode Transition Method CPG CPU CPU Register On-Chip Memory On-Chip Peripheral Modules Canceling Procedure Sleep Execute SLEEP instruction with STBY bit in STBCR1 cleared to 0. Runs Halts Held Runs Run • Reset Software standby Execute SLEEP instruction with STBY bit in STBCR1 and STBYMD bit in STBCR6 set to 1. Halts Halts Held Halts (contents retained) Halt • Interrupt by NMI or IRQ

• Power-on reset by the RES pin Module standby Set MSTP bits in STBCR2 to STBCR5 to 1. Runs Runs Held Specified module halts (contents retained) Specified module halts
• Clear MSTP bit to 0
• Power-on reset (for modules whose MSTP bit has an initial value of 0) Note: For details on the states of on-chip peripheral module registers in each mode, refer to section 20.3, Register States in Each Operating Mode. For details on the pin states in each mode, refer to appendix A, Pin States.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 661 of 758 REJ09B0243-0300

19.2 Input/Output Pins

Table 19.2 lists the pins used for the power-down modes. Table 19.2 Pin Configuration Pin Name Abbr. I/O Description Power-on reset RES Input Power-on reset input signal. Power-on reset by low level. Manual reset MRES Input Manual reset input signal. Manual reset by low level.

19.3 Register Descriptions

There are following registers used for the power-down modes. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 19.3 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Standby control register 1 STBCR1 R/W H'00 H'FFFFE802 8 Standby control register 2 STBCR2 R/W H'38 H'FFFFE804 8 Standby control register 3 STBCR3 R/W H'FF H'FFFFE806 8 Standby control register 4 STBCR4 R/W H'FF H'FFFFE808 8 Standby control register 5 STBCR5 R/W H'03 H'FFFFE80A 8 Standby control register 6 STBCR6 R/W H'00 H'FFFFE80C 8 RAM control register RAMCR R/W H'10 H'FFFFE880 8

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 662 of 758 REJ09B0243-0300

19.3.1 Standby Control Register 1 (STBCR1)

STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit: Initial value: R/W: 7654321 0 00000000 R / W RRRRRRR Bit Bit Name Initial Value R/W Description

7 STBY 0 R/W Standby

Specifies transition to software standby mode. 0: Executing SLEEP instruction makes this LSI sleep mode 1: Executing SLEEP instruction makes this LSI software standby mode 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 663 of 758 REJ09B0243-0300

19.3.2 Standby Control Register 2 (STBCR2)

STBCR2 is an 8-bit readable/writable register that controls the RAM operation in power-down mode. Bit: Initial value: R/W: 7654321 0 00111000 R/W R/W R/W R/W R/W R R R MSTP Bit Bit Name Initial Value R/W Description

7 MSTP7 0 R/W Module Stop Bit 7

When this bit is set to 1, the supply of the clock to the RAM is halted. 0: RAM operates 1: Clock supply to RAM halted 6  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 to 3  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 664 of 758 REJ09B0243-0300

19.3.3 Standby Control Register 3 (STBCR3)

STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W -- MSTP MSTP MSTP 11 --- Bit Bit Name Initial Value R/W Description 7, 6  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1.

5 MSTP13 1 R/W Module Stop Bit 13

When this bit is set to 1, the supply of the clock to the SCI_2 is halted. 0: SCI_2 operates 1: Clock supply to SCI_2 halted

4 MSTP12 1 R/W Module Stop Bit 12

When this bit is set to 1, the supply of the clock to the SCI_1 is halted. 0: SCI_1 operates 1: Clock supply to SCI_1 halted

3 MSTP11 1 R/W Module Stop Bit 11

When this bit is set to 1, the supply of the clock to the SCI_0 is halted. 0: SCI_0 operates 1: Clock supply to SCI_0 halted 2 to 0  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 665 of 758 REJ09B0243-0300

19.3.4 Standby Control Register 4 (STBCR4)

STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R R R/W R/W R/W - MSTP MSTP 21 --- MSTP MSTP Bit Bit Name Initial Value R/W Description 7  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

6 MSTP22 1 R/W Module Stop Bit 22

When this bit is set to 1, the supply of the clock to the MTU2 is halted. 0: MTU2 operates 1: Clock supply to MTU2 halted

5 MSTP21 1 R/W Module Stop Bit 21

When this bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT operates 1: Clock supply to CMT halted 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2  1 R/W Reserved This bit is always read as 1. The write value should always be 1.

1 MSTP17 1 R/W Module Stop Bit 17

When this bit is set to 1, the supply of the clock to the A/D_1 is halted. 0: A/D_1 operates 1: Clock supply to A/D_1 halted

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 666 of 758 REJ09B0243-0300 Bit Bit Name Initial Value R/W Description

0 MSTP16 1 R/W Module Stop Bit 16

When this bit is set to 1, the supply of the clock to the A/D_0 is halted. 0: A/D_0 operates 1: Clock supply to A/D_0 halted

19.3.5 Standby Control Register 5 (STBCR5)

STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit: Initial value: R/W: 7654321 0 00000011 RRRRRR R / W R / W Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 MSTP[25:24] 11 R/W Module Stop Bit 25 and 24 When either or both of these bits are set to 1, the supply of the clock to the UBC is halted. 00: UBC operates 01: Setting prohibited 10: Setting prohibited 11: Clock supply to UBC halted

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 667 of 758 REJ09B0243-0300

19.3.6 Standby Control Register 6 (STBCR6)

STBCR6 is an 8-bit readable/writable register that specifies the state of the power-down modes. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R R/W R --HIZ -UBC RST - STBY MD - Bit Bit Name Initial Value R/W Description

7 UBCRST 0 R/W UBC Software Reset

Resetting the PC trace unit of UBC is controlled by software. Clearing this bit to 0 puts the PC trace unit of the UBC module into the power-on reset state. 0: Puts the PC trace unit of UBC into the reset state 1: Releases reset in the PC trace unit of UBC

6 HIZ 0 R/W Port High-Impedance

In software standby mode, this bit selects whether the pin state is retained or changed to high-impedance. 0: In software standby mode, the pin state is retained 1: In software standby mode, the pin state is changed to high-impedance 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 STBYMD 0 R/W Software Standby Mode Select

If this bit is set to 1, executing SLEEP instruction with the STBY bit in STBCR1 is 1 and makes transition to software standby mode. 0: Setting prohibited 1: Makes transition to software standby mode 0  0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 668 of 758 REJ09B0243-0300

19.3.7 RAM Control Register (RAMCR)

RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit: Initial value: R/W: 7654321 0 00010000 RRR R / W RRRR Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

4 RAME 1 R/W RAM Enable

This bit enables/disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip RAM, and writing to the on- chip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write RAMCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read RAMCR should be set next to the instruction to write to RAMCR. If an instruction to access the on-chip RAM is set next to the instruction to write to RAMCR, normal access is not guaranteed. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 669 of 758 REJ09B0243-0300

19.4 Sleep Mode

19.4.1 Transition to Sleep Mode

Executing the SLEEP instruction when the STBY bit in STBCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to operate.

19.4.2 Canceling Sleep Mode

Sleep mode is canceled by a reset. (1) Canceling with Reset Sleep mode is canceled by a power-on reset with the RES pin, a manual reset with the MRES pin, or an internal power-on/manual reset by WDT. Do not cancel sleep mode with an interrupt.

Section 19 Power-Down Modes Rev. 3.00 Sep. 27, 2007 Page 670 of 758 REJ09B0243-0300

19.5 Software Standby Mode

19.5.1 Transition to Software Standby Mode

This LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The contents of the CPU registers and the data of the on-chip RAM remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. For details on the states of on- chip peripheral module registers in software standby mode, refer to section 20.3, Register States in Each Operating Mode. For details on the pin states in software standby mode, refer to appendix A, Pin States. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT. 2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY bit in STBCR1 and th e STBYMD bit in STBCR6 to 1, execute the SLEEP instruction. 4. Software standby mode is entered and the clocks within this LSI are halted.

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19.5.2 Canceling Software Standby Mode

Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. (1) Canceling with Interrupt The WDT can be used for hot starts. When an NMI or IRQ interrupt (edge detection) is detected, the clock will be supplied to the entire LSI and software standby mode will be canceled after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception handling is then executed. When the priority level of an IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing software standby mode from being canceled. When falling-edge detection is selected for the NMI pin, drive the NMI pin high before making a transition to software standby mode. When rising-edge detection is selected for the NMI pin, drive the NMI pin low before making a transition to software standby mode. Similarly, when falling-edge detection is selected for the IRQ pin, drive the IRQ pin high before making a transition to software standby mode. When rising-edge detection is selected for the IRQ pin, drive the IRQ pin low before making a transition to software standby mode. (2) Canceling with Power-on Reset Software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin low until the clock oscillation settles. (3) Canceling with Manual Reset Note that software standby mode cannot be canceled with a manual reset in this LSI.

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19.6 Module Standby Mode

19.6.1 Transition to Module Standby Mode

Setting the MSTP bits in the standby control registers (STBCR2 to STBCR5) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode. Do not access registers of an on-chip peripheral module, which has been set to enter module standby mode. For details on the states of on-chip peripheral module registers in module standby mode, refer to section 20.3, Register States in Each Operating Mode.

19.6.2 Canceling Module Standby Function

The module standby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR5 to 0. The module standby function can be canceled by a power-on reset for modules whose MSTP bit has an initial value of 0.

19.7 Usage Note

19.7.1 Current Consumption while Waiting for Oscillation to be Stabilized

The current consumption while waiting for oscillation to be stabilized is higher than that while oscillation is stabilized.

19.7.2 Executing the SLEEP Instruction

Apply either of the following measures before executing the SLEEP instruction to initiate the transition to sleep mode or software standby mode. Measure A: Stop the generation of interrupts from on-chip peripheral modules, IRQ interrupts, and the NMI interrupt before executing the SLEEP instruction. Measure B: Change the value in FRQCR to the initial value, H’36DB, and then dummy-read FRQCR twice before executing the SLEEP instruction.

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 673 of 758 REJ09B0243-0300 Section 20 List of Registers This section gives information on internal I/O registers. The contents of this section are as follows: 1. Register Address Table (in the order from a lower address)

• Registers are listed in the order from lower allocated addresses.
• As for reserved addresses, the register name column is indicated with . Do not access reserved addresses.
• As for 16- or 32-bit address, the MSB addresses are shown.
• The list is classified according to module names.
• The numbers of access cycles are given. 2. Register Bit Table
• Bit configurations are shown in the order of the register address table.
• As for reserved bits, the bit name column is indicated with .
• As for the blank column of the bit names, the whole register is allocated to the counter or data.
• As for 16- or 32-bit registers, bits are indicated from the MSB. 3. Register State in Each Operating Mode
• Register states are listed in the order of the register address table.
• Register states in the basic operating mode are shown. As for modules including their specific states such as reset, see the sections of those modules.

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 674 of 758 REJ09B0243-0300

20.1 Register Address Table (In the Order from Lower Addresses)

Access sizes are indicated with the number of bits. Access states are indicated with the number of specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or 32-bit access (L). Note: Access to undefined or reserved addresse s is prohibited. Correct operation cannot be guaranteed if these addresses are accessed. Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Serial mode register_0 SCSMR_0 8 H'FFFFC000 SCI 8 P φ reference Bit rate register_0 SCBRR_0 8 H'FFFFC002 (Channel 0) 8 B: 2 Serial control register_0 SCSCR_0 8 H'FFFFC004 8 Transmit data register_0 SCTDR_0 8 H'FFFFC006 8 Serial status register_0 SCSSR_0 8 H'FFFFC008 8 Receive data register_0 SCRDR_0 8 H'FFFFC00A 8 Serial direction control register_0 SCSDCR_0 8 H'FFFFC00C 8 Serial port register_0 SCSPTR_0 8 H'FFFFC00E 8 Serial mode register_1 SCSMR_1 8 H'FFFFC080 SCI 8 P φ reference Bit rate register_1 SCBRR_1 8 H'FFFFC082 (Channel 1) 8 B: 2 Serial control register_1 SCSCR_1 8 H'FFFFC084 8 Transmit data register_1 SCTDR_1 8 H'FFFFC086 8 Serial status register_1 SCSSR_1 8 H'FFFFC088 8 Receive data register_1 SCRDR_1 8 H'FFFFC08A 8 Serial direction control register_1 SCSDCR_1 8 H'FFFFC08C 8 Serial port register_1 SCSPTR_1 8 H'FFFFC08E 8 Serial mode register_2 SCSMR_2 8 H'FFFFC100 SCI 8 P φ reference Bit rate register_2 SCBRR_2 8 H'FFFFC102 (Channel 2) 8 B: 2 Serial control register_2 SCSCR_2 8 H'FFFFC104 8 Transmit data register_2 SCTDR_2 8 H'FFFFC106 8 Serial status register_2 SCSSR_2 8 H'FFFFC108 8 Receive data register_2 SCRDR_2 8 H'FFFFC10A 8 Serial direction control register_2 SCSDCR_2 8 H'FFFFC10C 8 Serial port register_2 SCSPTR_2 8 H'FFFFC10E 8

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 675 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Timer control register_3 TCR_3 8 H'FFFFC200 MTU2 8, 16, 32 MP φ reference Timer control register_4 TCR_4 8 H'FFFFC201 8 B: 2, W: 2, L: 4 Timer mode register_3 TMDR_3 8 H'FFFFC202 8, 16 Timer mode register_4 TMDR_4 8 H'FFFFC203 8 Timer I/O control register H_3 TIORH_3 8 H'FFFFC204 8, 16, 32 Timer I/O control register L_3 TIORL_3 8 H'FFFFC205 8 Timer I/O control register H_4 TIORH_4 8 H'FFFFC206 8, 16 Timer I/O control register L_4 TIORL_4 8 H'FFFFC207 8 Timer interrupt enable register_3 TIER_3 8 H'FFFFC208 8, 16 Timer interrupt enable register_4 TIER_4 8 H'FFFFC209 8 Timer output master enable register TOER 8 H'FFFFC20A 8 Timer gate control register TGCR 8 H'FFFFC20D 8 Timer output control register 1 TOCR1 8 H'FFFFC20E 8, 16 Timer output control register 2 TOCR2 8 H'FFFFC20F 8 Timer counter_3 TCNT_3 16 H'FFFFC210 16, 32 Timer counter_4 TCNT_4 16 H'FFFFC212 16 Timer cycle data register TCDR 16 H'FFFFC214 16, 32 Timer dead time data register TDDR 16 H'FFFFC216 16 Timer general register A_3 TGRA_3 16 H'FFFFC218 16, 32 Timer general register B_3 TGRB_3 16 H'FFFFC21A 16 Timer general register A_4 TGRA_4 16 H'FFFFC21C 16, 32 Timer general register B_4 TGRB_4 16 H'FFFFC21E 16 Timer sub-counter TCNTS 16 H'FFFFC220 16, 32 Timer cycle buffer register TCBR 16 H'FFFFC222 16 Timer general register C_3 TGRC_3 16 H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 16 H'FFFFC226 16 Timer general register C_4 TGRC_4 16 H'FFFFC228 16, 32 Timer general register D_4 TGRD_4 16 H'FFFFC22A 16 Timer status register_3 TSR_3 8 H'FFFFC22C 8, 16 Timer status register_4 TSR_4 8 H'FFFFC22D 8 Timer interrupt skipping set register TITCR 8 H'FFFFC230 8, 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 676 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Timer interrupt skipping counter TITCNT 8 H'FFFFC231 MTU2 8 MP φ reference Timer buffer transfer set register TBTER 8 H'FFFFC232 8 B: 2, W: 2, L: 4 Timer dead time enable register TDER 8 H'FFFFC234 8 Timer output level buffer register TOLBR 8 H'FFFFC236 8 Timer buffer operation transfer mode register_3 TBTM_3 8 H'FFFFC238 8, 16 Timer buffer operation transfer mode register_4 TBTM_4 8 H'FFFFC239 8 Timer A/D converter start request control register TADCR 16 H'FFFFC240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 16 H'FFFFC244 16, 32 Timer A/D converter start request cycle set register B_4 TADCORB_4 16 H'FFFFC246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 16 H'FFFFC248 16, 32 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 16 H'FFFFC24A 16 Timer waveform control register TWCR 8 H'FFFFC260 8 Timer start register TSTR 8 H'FFFFC280 8, 16 Timer synchronous register TSYR 8 H'FFFFC281 Timer counter synchronous start register TCSYSTR 8 H'FFFFC282 8 Timer read/write enable register TRWER 8 H'FFFFC284 8 Timer control register_0 TCR_0 8 H'FFFFC300 8, 16, 32 Timer mode register_0 TMDR_0 8 H'FFFFC301 8 Timer I/O control register H_0 TIORH_0 8 H'FFFFC302 8, 16 Timer I/O control register L_0 TIORL_0 8 H'FFFFC303 8 Timer interrupt enable register_0 TIER_0 8 H'FFFFC304 8, 16, 32 Timer status register_0 TSR_0 8 H'FFFFC305 8 Timer counter_0 TCNT_0 16 H'FFFFC306 16 Timer general register A_0 TGRA_0 16 H'FFFFC308 16, 32 Timer general register B_0 TGRB_0 16 H'FFFFC30A 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 677 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Timer general register C_0 TGRC_0 16 H'FFFFC30C MTU2 16, 32 MP φ reference Timer general register D_0 TGRD_0 16 H'FFFFC30E 16 B: 2, W: 2, L: 4 Timer general register E_0 TGRE_0 16 H'FFFFC320 16, 32 Timer general register F_0 TGRF_0 16 H'FFFFC322 16 Timer interrupt enable register 2_0 TIER2_0 8 H'FFFFC324 8, 16 Timer status register 2_0 TSR2_0 8 H'FFFFC325 8 Timer buffer operation transfer mode register_0 TBTM_0 8 H'FFFFC326 8 Timer control register_1 TCR_1 8 H'FFFFC380 8, 16 Timer mode register_1 TMDR_1 8 H'FFFFC381 8 Timer I/O control register_1 TIOR_1 8 H'FFFFC382 8 Timer interrupt enable register_1 TIER_1 8 H'FFFFC384 8, 16, 32 Timer status register_1 TSR_1 8 H'FFFFC385 8 Timer counter_1 TCNT_1 16 H'FFFFC386 16 Timer general register A_1 TGRA_1 16 H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 16 H'FFFFC38A 16 Timer input capture control register TICCR 8 H'FFFFC390 8 Timer control register_2 TCR_2 8 H'FFFFC400 8, 16 Timer mode register_2 TMDR_2 8 H'FFFFC401 8 Timer I/O control register_2 TIOR_2 8 H'FFFFC402 8 Timer interrupt enable register_2 TIER_2 8 H'FFFFC404 8, 16, 32 Timer status register_2 TSR_2 8 H'FFFFC405 8 Timer counter_2 TCNT_2 16 H'FFFFC406 16 Timer general register A_2 TGRA_2 16 H'FFFFC408 16, 32 Timer general register B_2 TGRB_2 16 H'FFFFC40A 16 Timer counter U_5 TCNTU_5 16 H'FFFFC480 16, 32 Timer general register U_5 TGRU_5 16 H'FFFFC482 16 Timer control register U_5 TCRU_5 8 H'FFFFC484 8 Timer I/O control register U_5 TIORU_5 8 H'FFFFC486 8 Timer counter V_5 TCNTV_5 16 H'FFFFC490 16, 32 Timer general register V_5 TGRV_5 16 H'FFFFC492 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 678 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Timer control register V_5 TCRV_5 8 H'FFFFC494 MTU2 8 MP φ reference Timer I/O control register V_5 TIORV_5 8 H'FFFFC496 8 B: 2, W: 2, L: 4 Timer counter W_5 TCNTW_5 16 H'FFFFC4A0 16, 32 Timer general register W_5 TGRW_5 16 H'FFFFC4A2 16 Timer control register W_5 TCRW_5 8 H'FFFFC4A4 8 Timer I/O control register W_5 TIORW_5 8 H'FFFFC4A6 8 Timer status register_5 TSR_5 8 H'FFFFC4B0 8 Timer interrupt enable register_5 TIER_5 8 H'FFFFC4B2 8 Timer start register_5 TSTR_5 8 H'FFFFC4B4 8 Timer compare match clear register TCNTCMPCLR 8 H'FFFFC4B6 8 A/D data register 0 ADDR0 16 H'FFFFC900 A/D 16 P φ reference A/D data register 1 ADDR1 16 H'FFFFC902 (Channel 0) 16 B: 2, W: 2 A/D data register 2 ADDR2 16 H'FFFFC904 16 A/D data register 3 ADDR3 16 H'FFFFC906 16 A/D control/status register_0 ADCSR_0 16 H'FFFFC910 16 A/D control register_0 ADCR_0 16 H'FFFFC912 16 A/D data register 4 ADDR4 16 H'FFFFC980 A/D 16 P φ reference A/D data register 5 ADDR5 16 H'FFFFC982 (Channel 1) 16 B: 2, W: 2 A/D data register 6 ADDR6 16 H'FFFFC984 16 A/D data register 7 ADDR7 16 H'FFFFC986 16 A/D control/status register_1 ADCSR_1 16 H'FFFFC990 16 A/D control register_1 ADCR_1 16 H'FFFFC992 16 Flash code control/status register FCCS 8 H'FFFFCC00 FLASH 8 P φ reference Flash program code select register FPCS 8 H'FFFFCC01 8 B: 5 Flash erase code select register FECS 8 H'FFFFCC02 8 Flash key code register FKEY 8 H'FFFFCC04 8 Flash transfer destination address register FTDAR 8 H'FFFFCC06 8

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 679 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Compare match timer start register CMSTR 16 H'FFFFCE00 CMT 8, 16, 32 P φ reference Compare match timer control/status register_0 CMCSR_0 16 H'FFFFCE02 8, 16 B: 2, W: 2, L: 4 Compare match counter_0 CMCNT_0 16 H'FFFFCE04 8, 16, 32 Compare match constant register_0 CMCOR_0 16 H'FFFFCE06 8, 16 Compare match timer control/status register_1 CMCSR_1 16 H'FFFFCE08 8, 16, 32 Compare match counter_1 CMCNT_1 16 H'FFFFCE0A 8, 16 Compare match constant register_1 CMCOR_1 16 H'FFFFCE0C 8, 16, 32 Input level control/status register 1 ICSR1 16 H'FFFFD000 POE 8, 16, 32 P φ reference Output level control/status register 1 OCSR1 16 H'FFFFD002 8, 16 B: 2, W: 2, L: 4 Input level control/status register 3 ICSR3 16 H'FFFFD008 8, 16 Software port output enable register SPOER 8 H'FFFFD00A 8 Port output enable control register 1 POECR1 8 H'FFFFD00B 8 Port output enable control register 2 POECR2 16 H'FFFFD00C 8, 16 Port A data register L PADRL 16 H'FFFFD102 I/O 8, 16 Port A I/O register L PAIORL 16 H'FFFFD106 PFC 8, 16 Pφ reference B: 2, W: 2, L: 4 Port A control register L4 PACRL4 16 H’FFFFD110 8, 16, 32 Port A control register L3 PACRL3 16 H’FFFFD112 8, 16 Port A control register L2 PACRL2 16 H’FFFFD114 8, 16, 32 Port A control register L1 PACRL1 16 H’FFFFD116 8, 16 Port A port register L PAPR L 16 H'FFFFD11E I/O 8, 16 Port B data register H PBDRH 16 H’FFFFD180 8, 16, 32 Port B data register L PBDRL 16 H’FFFFD182 8, 16 Port B I/O register H PBIORH 16 H'FFFFD184 PFC 8, 16, 32 Port B I/O register L PBIORL 16 H'FFFFD186 8, 16 Port B control register H1 PBCRH1 16 H'FFFFD18E 8, 16 Port B control register L2 PBCRL2 16 H'FFFFD194 8, 16, 32 Port B control register L1 PBCRL1 16 H'FFFFD196 8, 16 Port B port register H PBPRH 16 H'FFFFD19C I/O 8, 16, 32 Port B port register L PBPRL 16 H'FFFFD19E 8, 16 Port E data register L PEDRL 16 H'FFFFD302 8, 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 680 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Port E I/O register L PEIORL 16 H'FFFFD306 PFC 8, 16 P φ reference Port E control register L4 PECRL4 16 H'FFFFD310 8, 16, 32 B: 2, W: 2, L: 4 Port E control register L3 PECRL3 16 H'FFFFD312 8, 16 Port E control register L2 PECRL2 16 H'FFFFD314 8, 16, 32 Port E control register L1 PECRL1 16 H'FFFFD316 8, 16 Port E port register L PEPR L 16 H'FFFFD31E I/O 8, 16 IRQOUT function control register IFCR 16 H'FFFFD322 PFC 8, 16 Port F data register L PFDRL 16 H'FFFFD382 I/O 8, 16 Frequency control register FRQCR 16 H'FFFFE800 CPG 16 P φ reference W: 2 Standby control register 1 STBCR1 8 H'FFFFE802 8 P φ reference Standby control register 2 STBCR2 8 H'FFFFE804 Power-down modes 8 B: 2 Standby control register 3 STBCR3 8 H'FFFFE806 8 Standby control register 4 STBCR4 8 H'FFFFE808 8 Standby control register 5 STBCR5 8 H'FFFFE80A 8 Standby control register 6 STBCR6 8 H'FFFFE80C 8 Watchdog timer counter WTCNT 8 H'FFFFE810 8 * , 16* Watchdog timer control/status register WTCSR 8 H'FFFFE812 WDT *1: Read *2: Write , 16* Pφ reference B: 2* , W: 2* Oscillation stop detection control register OSCCR 8 H'FFFFE814 CPG 8 P φ reference B: 2 RAM control register RAMCR 8 H'FFFFE880 Power-down modes

8 P φ reference

B: 2 A/D trigger select register_0 ADTSR_0 16 H'FFFFE890 A/D 8, 16 P φ reference B: 2, W: 2 Interrupt control register 0 ICR0 16 H'FFFFE900 INTC 8, 16 P φ reference IRQ control register IRQCR 16 H'FFFFE902 8, 16 B: 2, W: 2 IRQ status register IRQSR 16 H'FFFFE904 8, 16 Interrupt priority register A IPRA 16 H'FFFFE906 8, 16 Interrupt priority register B IPRB 16 H'FFFFE908 8, 16 Interrupt priority register C IPRC 16 H'FFFFE980 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 681 of 758 REJ09B0243-0300 Register Name Abbreviation Number of Bits Address Module Access Size Number of Access States Interrupt priority register D IPRD 16 H'FFFFE982 INTC 16 P φ reference Interrupt priority register E IPRE 16 H'FFFFE984 16 B: 2, W: 2 Interrupt priority register F IPRF 16 H'FFFFE986 16 Interrupt priority register H IPRH 16 H'FFFFE98A 16 Interrupt priority register I IPRI 16 H'FFFFE98C 16 Interrupt priority register J IPRJ 16 H'FFFFE98E 16 Interrupt priority register K IPRK 16 H'FFFFE990 16 Interrupt priority register L IPRL 16 H'FFFFE992 16 Interrupt priority register M IPRM 16 H'FFFFE994 16 Break address register A BARA 32 H'FFFFF300 UBC 32 B φ reference Break address mask register A BAMRA 32 H'FFFFF304 32 B: 2, W: 2, L: 2 Break bus cycle register A BBRA 16 H'FFFFF308 16 Break data register A BDRA 32 H'FFFFF310 32 Break data mask register A BDMRA 32 H'FFFFF314 32 Break address register B BARB 32 H'FFFFF320 32 Break address mask register B BAMRB 32 H'FFFFF324 32 Break bus cycle register B BBRB 16 H'FFFFF328 16 Break data register B BDRB 32 H'FFFFF330 32 Break data mask register B BDMRB 32 H'FFFFF334 32 Break control register BRCR 32 H'FFFFF3C0 32 Branch source register BRSR 32 H'FFFFF3D0 32 Branch destination register BRDR 32 H'FFFFF3D4 32 Execution times break register BETR 16 H'FFFFF3DC 16

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 682 of 758 REJ09B0243-0300

20.2 Register Bit List

Addresses and bit names of each on-chip peripheral module are shown below. As for 16-bit or 32-bit registers, they are shown in two or four rows. Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module SCSMR_0 C/ A CHR PE O/ E STOP MP CKS[1:0] S C B R R _ 0 SCSCR_0 TIE RIE TE RE MPIE TEIE CKE[1:0] S C T D R _ 0 SCSSR_0 TDRE RDRF ORER FER PER TEND MPB MPBT SCI (Channel 0) SCRDR_0 SCSPTR_0 EIO    SPB1IO SPB1DT SPB0IO SPB0DT SCSMR_1 C/ A CHR PE O/ E STOP MP CKS[1:0] S C B R R _ 1 SCSCR_1 TIE RIE TE RE MPIE TEIE CKE[1:0] S C T D R _ 1 SCSSR_1 TDRE RDRF ORER FER PER TEND MPB MPBT SCI (Channel 1) SCRDR_1 SCSPTR_1 EIO    SPB1IO SPB1DT SPB0IO SPB0DT SCSMR_2 C/ A CHR PE O/ E STOP MP CKS[1:0] S C B R R _ 2 SCSCR_2 TIE RIE TE RE MPIE TEIE CKE[1:0] S C T D R _ 2 SCSSR_2 TDRE RDRF ORER FER PER TEND MPB MPBT SCI (Channel 2) SCRDR_2 SCSPTR_2 EIO    SPB1IO SPB1DT SPB0IO SPB0DT

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 683 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TCR_3 CCLR[2:0] CKEG[1:0] TPSC[2:0] TCR_4 CCLR[2:0] CKEG[1:0] TPSC[2:0] TMDR_3   BFB BFA MD[3:0] TMDR_4   BFB BFA MD[3:0] MTU2 TIORH_3 IOB[3:0] IOA[3:0] TIORL_3 IOD[3:0] IOC[3:0] TIORH_4 IOB[3:0] IOA[3:0] TIORL_4 IOD[3:0] IOC[3:0] TIER_3 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TIER_4 TTGE TTGE2  TCIEV TGIED TGIEC TGIEB TGIEA TOER   OE4D OE4C OE3D OE4B OE4A OE3B TGCR  BDC N P FB WF VF UF TOCR1  PSYE   TOCL TOCS OLSN OLSP TOCR2 BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 684 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module M T U 2 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD   TCFV TGFD TGFC TGFB TGFA TSR_4 TCFD   TCFV TGFD TGFC TGFB TGFA TITCR T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] TITCNT  3ACNT[2:0]  4VCNT[2:0] TOLBR   OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 685 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TSTR CST4 CST3    CST2 CST1 CST0 TSYR SYNC4 SYNC3    SYNC2 SYNC1 SYNC0 TCSYSTR SCH0 SCH1 SCH2 SCH3 SCH4    MTU2 TCR_0 CCLR[2:0] CKEG[1:0] TPSC[2:0] TMDR_0  BFE BFB BFA MD[3:0] TIORH_0 IOB[3:0] IOA[3:0] TIORL_0 IOD[3:0] IOC[3:0] TIER_0 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TSR_0    TCFV TGFD TGFC TGFB TGFA TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TTGE2      TGIEF TGIEE TBTM_0      TTSE TTSB TTSA TCR_1  CCLR[1:0] CKEG[1:0] TPSC[2:0] TIOR_1 IOB[3:0] IOA[3:0]

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 686 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TIER_1 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_1 TCFD  TCFU TCFV   TGFB TGFA TCNT_1 TGRA_1 TGRB_1 MTU2 TICCR     I2BE I2AE I1BE I1AE TCR_2  CCLR[1:0] CKEG[1:0] TPSC[2:0] TIOR_2 IOB[3:0] IOA[3:0] TIER_2 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_2 TCFD  TCFU TCFV   TGFB TGFA TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TIORU_5    IOC[4:0] TCNTV_5 TGRV_5

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 687 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module TIORV_5    IOC[4:0] MTU2 TCNTW_5 TGRW_5 TIORW_5    IOC[4:0] TSR_5      CMFU5 CMFV5 CMFW5 TIER_5      TGIE5U TGIE5V TGIE5W TSTR_5      CSTU5 CSTV5 CSTW5 TCNTCMPCLR      CMPCLR5U CMPCLR5V CMPCLR5W AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR0 A/D (Channel 0) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR1 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR2 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR3 ADF ADIE   TRGE  CONADF STC ADCSR_0 CKSL[1:0] ADM[1:0] ADCS CH[2:0] AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR4 A/D (Channel 1) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR5 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR6 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR7

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 688 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module ADF ADIE   TRGE  CONADF STC ADCSR_1 CKSL[1:0] ADM[1:0] ADCS CH[2:0] A/D (Channel 1) FCCS FWE   FLER    SCO FLASH FKEY K[7:0] FTDAR TDER TDA[6:0] CMF CMIE     CKS[1:0] CMCNT_0 CMCOR_0 CMF CMIE     CKS[1:0] CMCNT_1 CMCOR_1 POE3F  POE1F POE0F    PIE1 POE ICSR1 POE3M[1:0]   POE1M[1:0] POE0M[1:0] OSF1      OCE1 OIE1 OCSR1    POE8F   POE8E PIE3 ICSR3 SPOER       MTU2CH0HIZ MTU2CH34HIZ

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 689 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module POECR1     MTU2PE3ZE MTU2PE2ZE MTU2PE1ZE MTU2PE0ZE POE  MTU2P1CZE MTU2P2CZE MTU2P3CZE     POECR2 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR I/O PADRL (SH7125) PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR (SH7124) PA7DR PA6DR  PA4DR PA3DR  PA1DR PA0DR PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR PFC PAIORL (SH7125) PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR       PA9IOR PA8IOR PAIORL (SH7124) PA7IOR PA6IOR  PA4IOR PA3IOR  PA1IOR PA0IOR  PA15MD2 PA15MD1 PA15MD0  PA14MD2 PA14MD1 PA14MD0 PACRL4 (SH7125)  PA13MD2 PA13MD1 PA13MD0  PA12MD2 PA12MD1 PA12MD0  PA11MD2 PA11MD1 PA11MD0  PA10MD2 PA10MD1 PA10MD0 PACRL3 (SH7125)  PA9MD2 PA9MD1 PA9MD0  PA8MD2 PA8MD1 PA8MD0 (SH7124)  PA9MD2 PA9MD1 PA9MD0  PA8MD2 PA8MD1 PA8MD0  PA7MD2 PA7MD1 PA7MD0  PA6MD2 PA6MD1 PA6MD0 PACRL2 (SH7125)  PA5MD2 PA5MD1 PA5MD0  PA4MD2 PA4MD1 PA4MD0  PA7MD2 PA7MD1 PA7MD0  PA6MD2 PA6MD1 PA6MD0 PACRL2 (SH7124)      PA4MD2 PA4MD1 PA4MD0  PA3MD2 PA3MD1 PA3MD0  PA2MD2 PA2MD1 PA2MD0 PACRL1 (SH7125)  PA1MD2 PA1MD1 PA1MD0  PA0MD2 PA0MD1 PA0MD0  PA3MD2 PA3MD1 PA3MD0     PACRL1 (SH7124)  PA1MD2 PA1MD1 PA1MD0  PA0MD2 PA0MD1 PA0MD0 PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR PA8PR I/O PAPRL (SH7125) PA7PR PA6PR PA5PR PA4PR PA3 PR PA2PR PA1PR PA0PR (SH7124) PA7PR PA6PR  PA4PR PA3PR  PA1PR PA0PR

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 690 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module (SH7125)   PB5DR  PB3DR PB2DR PB1DR  (SH7124)   PB5DR  PB3DR  PB1DR  (SH7125)   PB5IOR  PB3IOR PB2IOR PB1IOR  (SH7124)   PB5IOR  PB3IOR  PB1IOR  (SH7125)  PB5MD2 PB5MD1 PB5MD0     (SH7124)  PB5MD2 PB5MD1 PB5MD0      PB3MD2 PB3MD1 PB3MD0  PB2MD2 PB2MD1 PB2MD0 PBCRL1 (SH7125)  PB1MD2 PB1MD1 PB1MD0      PB3MD2 PB3MD1 PB3MD0     PBCRL1 (SH7124)  PB1MD2 PB1MD1 PB1MD0    

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 691 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module (SH7125)   PB5PR  PB3PR PB2PR PB1PR  (SH7124)   PB5PR  PB3PR  PB1PR  PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PEDRL (SH7125) PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PEDRL (SH7124)     PE3DR PE2DR PE1DR PE0DR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PFC PEIORL (SH7125) PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PEIORL (SH7124)     PE3IOR PE2IOR PE1IOR PE0IOR  PE15MD2 PE15MD1 PE15MD0  PE14MD2 PE14MD1 PE14MD0 PECRL4   PE13MD1 PE13MD0  PE12MD2 PE12MD1 PE12MD0  PE11MD2 PE11MD1 PE11MD0  PE10MD2 PE10MD1 PE10MD0 PECRL3  PE9MD2 PE9MD1 PE9MD0  PE8MD2 PE8MD1 PE8MD0  PE7MD2 PE7MD1 PE7MD0  PE6MD2 PE6MD1 PE6MD0 PECRL2 (SH7125)  PE5MD2 PE5MD1 PE5MD0  PE4MD2 PE4MD1 PE4MD0  PE3MD2 PE3MD1 PE3MD0  PE2MD2 PE2MD1 PE2MD0 PECRL1  PE1MD2 PE1MD1 PE1MD0   PE0MD1 PE0MD0 PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR I/O PEPRL (SH7125) PE7PR PE6PR PE5PR PE4PR PE3 PR PE2PR PE1PR PE0PR PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR PEPRL (SH7124)     PE3PR PE2PR PE1PR PE0PR

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 692 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR  IFC[2:0] BFC[2:0] PFC[2] CPG FRQCR PFC[1:0]    MPFC[2:0] Power-down modes STBCR3   MSTP13 MSTP12 MSTP11    STBCR4  MSTP22 MSTP21    MSTP17 MSTP16 STBCR5       MSTP[25:24] STBCR6 UBCRST HIZ     STBYMD  W T C N T W D T WTCSR TME WT/IT RSTS WOVF IOVF CKS[2:0] OSCCR      OSCSTOP  OSCERS CPG RAMCR    RAME     Power-down modes TRG11S[3:0] TRG01S[3:0] A/D ADTSR_0 TRG1S[3:0] TRG0S[3:0] NMIL       NMIE INTC ICR0 IRQ31S IRQ30S IRQ21S IRQ20S IR Q11S IRQ10S IRQ01S IRQ00S     IRQ3L IRQ2L IRQ1L IRQ0L IRQSR     IRQ3F IRQ2F IRQ1F IRQ0F IRQ0 IRQ0 IRQ0 IRQ0 IR Q1 IRQ1 IRQ1 IRQ1 IPRA IRQ2 IRQ2 IRQ2 IRQ2 IR Q3 IRQ3 IRQ3 IRQ3

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 693 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU 2_0 MTU2_0 MTU2_0 MTU2_0 INTC IPRD MTU2_1 MTU2_1 MTU2_1 MTU2_1 MT U2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MT U2_2 MTU2_2 MTU2_2 MTU2_2 IPRE MTU2_3 MTU2_3 MTU2_3 MTU2_3 MT U2_3 MTU2_3 MTU2_3 MTU2_3 MTU2_4 MTU2_4 MTU2_4 MTU2_4 MT U2_4 MTU2_4 MTU2_4 MTU2_4 IPRF MTU2_5 MTU2_5 MTU2_5 MTU2_5 POE(MT U2) POE(MTU2) POE(MTU2) POE(MTU2) CMT_0 CMT_0 CMT_0 CMT_0 CM T_1 CMT_1 CMT_1 CMT_1 IPRJ     WDT WDT WDT WDT A/D_0,1 A/D_0,1 A/D_0,1 A/D_0,1     IPRK SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 IPRL BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 UBC BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BARA BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMRA BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 CDA[1:0] IDA[1:0] RWA[1:0] SZA[1:0]

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 694 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module BDA31 BDA30 BDA29 BDA28 BD A27 BDA26 BDA25 BDA24 UBC BDA23 BDA22 BDA21 BDA20 BD A19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BD A11 BDA10 BDA9 BDA8 BDRA BDA7 BDA6 BDA5 BDA4 BD A3 BDA2 BDA1 BDA0 BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMRA BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BARB BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMRB BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 CDB[1:0] IDB[1:0] RWB[1:0] SZB[1:0] BDB31 BDB30 BDB29 BDB28 BD B27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BD B19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BD B11 BDB10 BDB9 BDB8 BDRB BDB7 BDB6 BDB5 BDB4 BD B3 BDB2 BDB1 BDB0 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMRB BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 SCMFCA SCMFCB SCMFDA SCMFDB PCTE PCBA   BRCR DBEA PCBB DBEB  SEQ   ETBE

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 695 of 758 REJ09B0243-0300 Register Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module SVF    BSA27 BSA26 BSA25 BSA24 UBC BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BRSR BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 DVF    BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BD A19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BD A11 BDA10 BDA9 BDA8 BRDR BDA7 BDA6 BDA5 BDA4 BD A3 BDA2 BDA1 BDA0     BET[11:8] BETR BET[7:0]

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 696 of 758 REJ09B0243-0300

20.3 Register States in Each Operating Mode

Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module SCSMR_0 Initialized Retained Initialized Initialized Retained SCBRR_0 Initialized Retained Initialized Initialized Retained SCSCR_0 Initialized Retained Initialized Initialized Retained SCTDR_0 Initialized Retained Initialized Initialized Retained SCSSR_0 Initialized Retained Initialized Initialized Retained SCRDR_0 Initialized Retained In itialized Initialized Retained SCSDCR_0 Initialized Retained Initialized Initialized Retained SCSPTR_0 Initialized Retained Initialized Initialized Retained SCI (Channel 0) SCSMR_1 Initialized Retained Initialized Initialized Retained SCBRR_1 Initialized Retained Initialized Initialized Retained SCSCR_1 Initialized Retained Initialized Initialized Retained SCTDR_1 Initialized Retained Initialized Initialized Retained SCSSR_1 Initialized Retained Initialized Initialized Retained SCRDR_1 Initialized Retained In itialized Initialized Retained SCSDCR_1 Initialized Retained Initialized Initialized Retained SCSPTR_1 Initialized Retained Initialized Initialized Retained SCI (Channel 1) SCSMR_2 Initialized Retained Initialized Initialized Retained SCBRR_2 Initialized Retained Initialized Initialized Retained SCSCR_2 Initialized Retained Initialized Initialized Retained SCTDR_2 Initialized Retained Initialized Initialized Retained SCSSR_2 Initialized Retained Initialized Initialized Retained SCRDR_2 Initialized Retained In itialized Initialized Retained SCSDCR_2 Initialized Retained Initialized Initialized Retained SCSPTR_2 Initialized Retained Initialized Initialized Retained SCI (Channel 2) TCR_3 Initialized Retained Initialized Initialized Retained MTU2 TCR_4 Initialized Retained Initialized Initialized Retained TMDR_3 Initialized Retained Initialized Initialized Retained TMDR_4 Initialized Retained Initialized Initialized Retained TIORH_3 Initialized Retained Initialized Initialized Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 697 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module TIORL_3 Initialized Retained Initialized Initialized Retained MTU2 TIORH_4 Initialized Retained Initialized Initialized Retained TIORL_4 Initialized Retained Initialized Initialized Retained TIER_3 Initialized Retained Initialized Initialized Retained TIER_4 Initialized Retained Initialized Initialized Retained TOER Initialized Retained Initialized Initialized Retained TGCR Initialized Retained Initialized Initialized Retained TOCR1 Initialized Retained Initialized Initialized Retained TOCR2 Initialized Retained Initialized Initialized Retained TCNT_3 Initialized Retained Initialized Initialized Retained TCNT_4 Initialized Retained Initialized Initialized Retained TCDR Initialized Retained Init ialized Initialized Retained TDDR Initialized Retained Init ialized Initialized Retained TGRA_3 Initialized Retained Initialized Initialized Retained TGRB_3 Initialized Retained Initialized Initialized Retained TGRA_4 Initialized Retained Initialized Initialized Retained TGRB_4 Initialized Retained Initialized Initialized Retained TCNTS Initialized Retained Initialized Initialized Retained TCBR Initialized Retained Initialized Initialized Retained TGRC_3 Initialized Retained Initialized Initialized Retained TGRD_3 Initialized Retained Initialized Initialized Retained TGRC_4 Initialized Retained Initialized Initialized Retained TGRD_4 Initialized Retained Initialized Initialized Retained TSR_3 Initialized Retained Initialized Initialized Retained TSR_4 Initialized Retained Initialized Initialized Retained TITCR Initialized Retained Initialized Initialized Retained TITCNT Initialized Retained Initialized Initialized Retained TBTER Initialized Retained Initialized Initialized Retained TDER Initialized Retained Initialized Initialized Retained TOLBR Initialized Retained Initialized Initialized Retained TBTM_3 Initialized Retained Initialized Initialized Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 698 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module TBTM_4 Initialized Retained Initialized Initialized Retained MTU2 TADCR Initialized Retained Init ialized Initialized Retained TADCORA_4 Initialized Retained Initialized Initialized Retained TADCORB_4 Initialized Retained Initialized Initialized Retained TADCOBRA_4 Initialized Retained Initialized Initialized Retained TADCOBRB_4 Initialized Retained Initialized Initialized Retained TWCR Initialized Retained Initialized Initialized Retained TSTR Initialized Retained Initialized Initialized Retained TSYR Initialized Retained Initialized Initialized Retained TCSYSTR Initialized Retai ned Initialized Initialized Retained TRWER Initialized Retained Initialized Initialized Retained TCR_0 Initialized Retained Initialized Initialized Retained TMDR_0 Initialized Retained Initialized Initialized Retained TIORH_0 Initialized Retained Initialized Initialized Retained TIORL_0 Initialized Retained Initialized Initialized Retained TIER_0 Initialized Retained Initialized Initialized Retained TSR_0 Initialized Retained Initialized Initialized Retained TCNT_0 Initialized Retained Initialized Initialized Retained TGRA_0 Initialized Retained Initialized Initialized Retained TGRB_0 Initialized Retained Initialized Initialized Retained TGRC_0 Initialized Retained Initialized Initialized Retained TGRD_0 Initialized Retained Initialized Initialized Retained TGRE_0 Initialized Retained Initialized Initialized Retained TGRF_0 Initialized Retained Initialized Initialized Retained TIER2_0 Initialized Retained Initialized Initialized Retained TSR2_0 Initialized Retained Initialized Initialized Retained TBTM_0 Initialized Retained Initialized Initialized Retained TCR_1 Initialized Retained Initialized Initialized Retained TMDR_1 Initialized Retained Initialized Initialized Retained TIOR_1 Initialized Retained Initialized Initialized Retained TIER_1 Initialized Retained Initialized Initialized Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 699 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module TSR_1 Initialized Retained Initialized Initialized Retained MTU2 TCNT_1 Initialized Retained Initialized Initialized Retained TGRA_1 Initialized Retained Initialized Initialized Retained TGRB_1 Initialized Retained Initialized Initialized Retained TICCR Initialized Retained Init ialized Initialized Retained TCR_2 Initialized Retained Initialized Initialized Retained TMDR_2 Initialized Retained Initialized Initialized Retained TIOR_2 Initialized Retained Initialized Initialized Retained TIER_2 Initialized Retained Initialized Initialized Retained TSR_2 Initialized Retained Initialized Initialized Retained TCNT_2 Initialized Retained Initialized Initialized Retained TGRA_2 Initialized Retained Initialized Initialized Retained TGRB_2 Initialized Retained Initialized Initialized Retained TCNTU_5 Initialized Retained Initialized Initialized Retained TGRU_5 Initialized Retained Initialized Initialized Retained TCRU_5 Initialized Retained Initialized Initialized Retained TIORU_5 Initialized Retained Initialized Initialized Retained TCNTV_5 Initialized Retained Initialized Initialized Retained TGRV_5 Initialized Retained Initialized Initialized Retained TCRV_5 Initialized Retained Initialized Initialized Retained TIORV_5 Initialized Retained Initialized Initialized Retained TCNTW_5 Initialized Retained Initialized Initialized Retained TGRW_5 Initialized Retained Initialized Initialized Retained TCRW_5 Initialized Retained Initialized Initialized Retained TIORW_5 Initialized Retained Initialized Initialized Retained TSR_5 Initialized Retained Initialized Initialized Retained TIER_5 Initialized Retained Initialized Initialized Retained TSTR5 Initialized Retained Initialized Initialized Retained TCNTCMPCLR Initialized Retained Initialized Initialized Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 700 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module ADDR0 Initialized Retained Initialized Initialized Retained A/D (Channel 0) ADDR1 Initialized Retained Init ialized Initialized Retained ADDR2 Initialized Retained Init ialized Initialized Retained ADDR3 Initialized Retained Init ialized Initialized Retained ADCSR_0 Initialized Retained Initialized Initialized Retained ADCR_0 Initialized Retained Initialized Initialized Retained ADDR4 Initialized Retained Initialized Initialized Retained A/D (Channel 1) ADDR5 Initialized Retained Init ialized Initialized Retained ADDR6 Initialized Retained Init ialized Initialized Retained ADDR7 Initialized Retained Init ialized Initialized Retained ADCSR_1 Initialized Retained Initialized Initialized Retained ADCR_1 Initialized Retained Initialized Initialized Retained FCCS Initialized Retained Initialized Initialized Retained FLASH FPCS Initialized Retained Initialized Initialized Retained FECS Initialized Retained Initialized Initialized Retained FKEY Initialized Retai ned Initialized Initialized Retained FTDAR Initialized Retained Initialized Initialized Retained CMSTR Initialized Retained Initialized Initialized Retained CMT CMCSR_0 Initialized Retained Initialized Initialized Retained CMCNT_0 Initialized Retained Initialized Initialized Retained CMCOR_0 Initialized Retained Initialized Initialized Retained CMCSR_1 Initialized Retained Initialized Initialized Retained CMCNT_1 Initialized Retained Initialized Initialized Retained CMCOR_1 Initialized Retained Initialized Initialized Retained ICSR1 Initialized Retained Retained  Retained POE OCSR1 Initialized Retained Retained  Retained ICSR3 Initialized Retained Retained  Retained SPOER Initialized Retained Retained  Retained POECR1 Initialized Retained Retained  Retained POECR2 Initialized Retained Retained  Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 701 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module PADRL Initialized Retained Retained  Retained I/O PAIORL Initialized Retained Retained  Retained PFC PACRL4 Initialized Retained Retained  Retained PACRL3 Initialized Retained Retained  Retained PACRL2 Initialized Retained Retained  Retained PACRL1 Initialized Retained Retained  Retained PAPRL Initialized Retai ned Retained  Retained I/O PBDRH Initialized Retained Retained  Retained PBDRL Initialized Retained Retained  Retained PBIORH Initialized Retained Retained  Retained PFC PBIORL Initialized Retained Retained  Retained PBCRH1 Initialized Retained Retained  Retained PBCRL2 Initialized Retained Retained  Retained PBCRL1 Initialized Retained Retained  Retained PBPRH Initialized Retained Retained  Retained I/O PBPRL Initialized Retai ned Retained  Retained PEDRL Initialized Retained Retained  Retained PEIORL Initialized Retained Retained  Retained PFC PECRL4 Initialized Retained Retained  Retained PECRL3 Initialized Retained Retained  Retained PECRL2 Initialized Retained Retained  Retained PECRL1 Initialized Retained Retained  Retained PEPRL Initialized Retai ned Retained  Retained I/O IFCR Initialized Retained Retained  Retained PFC PFDRL Initialized Retained Retained  Retained I/O FRQCR Initialized * Retained Retained  Retained CPG STBCR1 Initialized Retained Retained  Retained STBCR2 Initialized Retained Retained  Retained Power-down modes STBCR3 Initialized Retained Retained  Retained STBCR4 Initialized Retained Retained  Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 702 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module STBCR5 Initialized Retained Retained  Retained STBCR6 Initialized Retained Retained  Retained Power-down modes WTCNT Initialized * Retained Retained  Retained WDT WTCSR Initialized * Retained Retained  Retained OSCCR Initialized * Retained Retained *  Retained CPG RAMCR Initialized Retained Retained  Retained Power-down modes ADTSR_0 Initialized Retained Retained Retained Retained A/D ICR0 Initialized Initialized Retained  Retained INTC IRQCR Initialized Initialized Retained  Retained IRQSR Initialized Initialized Retained  Retained IPRA Initialized Initialized Retained  Retained IPRB Initialized Initialized Retained  Retained IPRC Initialized Initialized Retained  Retained IPRD Initialized Initialized Retained  Retained IPRE Initialized Initialized Retained  Retained IPRF Initialized Initialized Retained  Retained IPRH Initialized Initialized Retained  Retained IPRI Initialized Initialized Retained  Retained IPRJ Initialized Initialized Retained  Retained IPRK Initialized Initialized Retained  Retained IPRL Initialized Initialized Retained  Retained IPRM Initialized Initialized Retained  Retained BARA Initialized Retained Retained Initialized Retained UBC BAMRA Initialized Retained Retained Initialized Retained BBRA Initialized Retained Retained Initialized Retained BDRA Initialized Retained Retained Initialized Retained BDMRA Initialized Retained Retained Initialized Retained BARB Initialized Retained Retained Initialized Retained BAMRB Initialized Retained Retained Initialized Retained BBRB Initialized Retained Retained Initialized Retained

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 703 of 758 REJ09B0243-0300 Register Abbreviation Power-on reset Manual reset Software Standby Module Standby Sleep Module BDRB Initialized Retained Retained Initialized Retained UBC BDMRB Initialized Retained Retained Initialized Retained BRCR Initialized Retained Reta ined Initialized Retained BRSR Initialized Retained Retained Initialized Retained BRDR Initialized Retained Reta ined Initialized Retained BETR Initialized Retained Retained Initialized Retained Notes: 1. Not initialized by a WDT power-on reset. 2. The OSCSTOP bit is not initialized by a WDT power-on reset. 3. The OSCSTOP bit is initialized.

Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 704 of 758 REJ09B0243-0300

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 705 of 758 REJ09B0243-0300 Section 21 Electrical Characteristics All values for electrical characteristics are preliminary, and are subject to change without notice as a result of characteristics evaluation.

21.1 Absolute Maximum Ratings

Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage V CC −0.3 to + 7.0 V Input voltage (except analog input) V in −0.3 to VCC + 0.3 V Analog power supply voltage AV CC −0.3 to + 7.0 V Analog reference voltage AV ref −0.3 to AVCC + 0.3 V Analog input voltage V an −0.3 to AVCC + 0.3 V Operating temperature Consumer specifications Topr −20 to + 85 °C Industrial specifications −40 to + 85 °C Storage temperature T stg −55 to + 125 °C [Operating Precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage.

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 706 of 758 REJ09B0243-0300

21.2 DC Characteristics

Tables 21.2 and 21.3 list DC characteristics. Table 21.2 DC Characteristics Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Typ. Max. Unit Test Conditions RES, MRES, NMI, FWE, MD1, ASEMD0, EXTAL VIH V CC − 0.7 — V CC + 0.3 V Analog ports 2.2 — AV CC + 0.3 V Input high-level voltage (other than Schmitt trigger input voltage) Other input pins 2.2 — V CC + 0.3 V RES, MRES, NMI, FWE, MD1, ASEMD0, EXTAL −0.3 — 0.5 V Input low-level voltage (other than Schmitt trigger input voltage) Other input pins VIL −0.3 — 0.8 V VT+ V CC − 0.5 — — V VT– — — 1.0 V Schmitt trigger input voltage IRQ3 to IRQ0, POE8, POE3, POE1, POE0, TCLKA to TCLKD, TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TIC5U, TIC5V, TIC5WS, SCK0 to SCK3, RXD0 to RXD3 V T+–VT– 0.4 — — V V CC = 4.5 V to 5.5 V Input leak current All input pins (except ASEMD0) | I in | — — 1.0 µA Input pull-up MOS current ASEMD0, POE3 –I pu — — 800 µA V in = 0 V Tri-state leakage current (OFF state) Ports A, B, E | I tsi |   1.0 µA

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 707 of 758 REJ09B0243-0300 Item Symbol Min. Typ. Max. Unit Test Conditions PE9, PE11 to PE15 V CC − 0.8   V I OH = –5 mA WDTOVF V CC − 0.5   V I OH = –100 µA VCC − 0.5   V I OH = –200 µA VCC − 1.0   V I OH = –1 mA Output high voltage All other output pins VOH VCC − 1.5   V I OH = –2 mA (reference values) PE9, PE11 to PE15   1.4 V I OL = 15 mA Output low voltage All other output pins VOL   0.4 V I OL = 1.6 mA Input capacitance All input pins C in   20 pF V in = 0 V f = 1 MHz Ta = 25°C Normal operation  52 70 mA I φ = 50 MHz Sleep  33 50 mA I φ = 50 MHz   5 mA T a ≤ 50°C Supply current Software standby ICC   15 mA 50 °C < Ta During A/D conversion  3 5 mA The value per module Waiting for A/D conversion   2 mA The value per module Analog power supply current Standby AI CC   15 µA [Operating Precautions] 1. When the A/D converter is not used, do not leave the AV CC and AVSS pins open. all output pins unloaded.

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 708 of 758 REJ09B0243-0300 Table 21.3 Permitted Output Current Values Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Typ. Max. Unit Permissible current in low-level output (per pin) I OL   2.0 * mA Permissible current in low-level output (total) Σ IOL   80 mA Permissible current in high-level output (per pin) –IOH   2.0 * mA Permissible current in high-level output (total) Σ –IOH   25 mA [Operating Precautions] To assure LSI reliability, do not exceed the output values listed in table 21.3. Note: * I OL = 15 mA (Max.)/–IOH = 5 mA (Max.) for pins PE9 and PE11 to PE15. However, at least three pins are permitted to have simultaneously IOL/–IOH > 2.0 mA among these pins.

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 709 of 758 REJ09B0243-0300

21.3 AC Characteristics

Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 21.4 Maximum Operating Frequency Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Typ. Max. Unit Remarks CPU (Iφ) 10 — 50 Operating frequency Peripheral module (Pφ) f 10 — 40 MHz

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 710 of 758 REJ09B0243-0300

21.3.1 Clock Timing

Table 21.5 Clock Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure EXTAL clock input frequency f EX 10 12.5 MHz EXTAL clock input cycle time t EXcyc 80 100 ns EXTAL clock input low pulse width t EXL 20  ns EXTAL clock input high pulse width t EXH 20  ns EXTAL clock input rising time t EXr  5 ns EXTAL clock input falling time t EXf  5 ns Figure 21.1 CK (Bφ) clock frequency (reference values) fOP 10 40 MHz CK (Bφ) clock cycle time (reference values) tcyc 25 100 ns Power-on oscillation stabilization time t OSC1 10  ms Figure 21.2 Oscillation stabilization time on return from standby 1 tOSC2 10  ms Figure 21.3 Oscillation stabilization time on return from standby 2 tOSC3 10  ms Figure 21.4 Note: * Depends on the frequency control register (FRQCR). tEXH tEXf tEXr tEXL tEXcyc VIH VIH VIH 1/2 VCC 1/2 VCCVIL VIL EXTAL (input) Figure 21.1 Timing of EXTAL Input Clock Signal

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 712 of 758 REJ09B0243-0300

21.3.2 Control Signal Timing

Table 21.6 Control Signal Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure RES pulse width t RESW 20 * — t Bcyc* RES setup time* (reference values) t RESS 65 — ns RES hold time (reference values) t RESH 15 — ns MRES pulse width t MRESW 20 * — t Bcyc* MRES setup time* (reference values) t MRESS 25 — ns MRES hold time (reference values) t MRESH 15 — ns Figures 21.2, 21.3, 21.5, 21.6 MD1, FWE setup time t MDS 20 — t Bcyc* Figure 21.5 NMI setup time* (reference values) t NMIS 60 — ns Figure 21.6 NMI hold time (reference values) t NMIH 10 — ns IRQ3 to IRQ0 setup time* (reference values) tIRQS 35 — ns IRQ3 to IRQ0 hold time (reference values) tIRQH 35 — ns IRQOUT output delay time (reference values) tIRQOD — 100 ns Figure 21.7 Notes: 1. The RES, MRES, NMI, and IRQ3 to IRQ0 signals are asynchronous signals. When the setup time is satisfied, change of signal level is detected at the rising edge of the clock. If not, the detection is delayed until the rising edge of the clock. 2. In standby mode, t RESW = tOSC2 (10 ms). 3. In standby mode, t MRESW = tOSC2 (10 ms). 4. t Bcyc indicates the bus clock cycle time (Bφ = CK).

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 714 of 758 REJ09B0243-0300 tIRQODtIRQOD CK IRQOUT Figure 21.7 Interrupt Signal Output Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 715 of 758 REJ09B0243-0300

21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing

Table 21.7 Multi Function Timer Pulse Unit 2 (MTU2) Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure Output compare output delay time (reference values) tTOCD  50 ns Figure 21.8 Input capture input setup time (reference values) tTICS 20  ns Input capture input pulse width (single edge) tTICWH/L 1.5  t MPcyc Input capture input pulse width (both edges) tTICWH/L 2.5  t MPcyc Timer input setup time (reference values) tTCKS 20  ns Figure 21.9 Timer clock pulse width (single edge) t TCKWH/L 1.5  t MPcyc Timer clock pulse width (both edges) t TCKWH/L 2.5  t MPcyc Timer clock pulse width (phase counting mode) tTCKWH/L 2.5  t MPcyc Note: t MPcyc indicates the MTU2 clock (MPφ) cycle. Output compare output Input capture input CK tTOCD tTICS tTICWH/L Figure 21.8 MTU2 Input/Output Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 716 of 758 REJ09B0243-0300 CK TCLKA to TCLKD tTCKS tTCKS tTCKWHtTCKWL Figure 21.9 MTU2 Clock Input Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 717 of 758 REJ09B0243-0300

21.3.4 I/O Port Timing

Table 21.8 I/O Port Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure Port output data delay time (reference values) tPWD  50 ns Figure 21.10 Port input low pulse width t PRWL 2  t Pcyc Port input high pulse width t PRWH 2  t Pcyc tPRWH/L tPWD CK Port (read) Port (write) Figure 21.10 I/O Port Input/Output Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 718 of 758 REJ09B0243-0300

21.3.5 Watchdog Timer (WDT) Timing

Table 21.9 Watchdog Timer (WDT) Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure WDTOVF delay time (reference values) tWOVD — 50 ns Figure 21.11 tWOVDtWOVD CK WDTOVF Figure 21.11 WDT Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 719 of 758 REJ09B0243-0300

21.3.6 Serial Communication Interface (SCI) Timing

Table 21.10 Serial Communication Interface (SCI) Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure Input clock cycle (asynchronous) t scyc 4  t pcyc Input clock cycle (clock synchronous) t scyc 6  t pcyc Figure 21.12 Input clock pulse width t sckw 0.4 0.6 t scyc Input clock rising time t sckr  1.5 t pcyc Input clock falling time t sckf  1.5 t pcyc Transmit data delay time t TXD  4 t pcyc + 10 ns Receive data setup time t RXS 4 t pcyc  ns Receive data hold time Asynchronous tRXH 4 t pcyc  ns Transmit data delay time t TXD  3 t pcyc + 10 ns Receive data setup time t RXS 2 t pcyc + 50  ns Receive data hold time Clock synchronous tRXH 2 t pcyc  ns Figure 21.13 Note: t pcyc indicates the peripheral clock (Pφ) cycle. tsckw VIH VIH VIH VIH VIL VIL VIL SCK0 to SCK2 tsckr tsckf tscyc Figure 21.12 Input Clock Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 720 of 758 REJ09B0243-0300 tscyc SCK0 to SCK2 (input/output) TXD0 to TXD2 (transmit data) RXD0 to RXD2 (receive data) SCI input/output timing (clock synchronous mode) tTXD tRXS tRXH CK TXD0 to TXD2 (transmit data) RXD0 to RXD2 (receive data) SCI input/output timing (asynchronous mode) Tn tTXD tRXS tRXH Figure 21.13 SCI Input/Output Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 721 of 758 REJ09B0243-0300

21.3.7 Port Output Enable (POE) Timing

Table 21.11 Port Output Enable (POE) Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Max. Unit Reference Figure POE input setup time (reference values) tPOES 50  ns Figure 21.14 POE input pulse width t POEW 1.5  t pcyc Note: t pcyc indicates the peripheral clock (Pφ) cycle. CK POEn input tPOES tPOEW Figure 21.14 POE Input Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 722 of 758 REJ09B0243-0300

21.3.8 A/D Converter Timing

Table 21.12 A/D Converter Timing Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Typ. Max. Unit Reference Figure External trigger input start delay time (reference values) tTRGS 25 — — ns Figure 21.15 CK ADTRG input tTRGS Figure 21.15 External Trigger Input Timing

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 723 of 758 REJ09B0243-0300

21.3.9 Conditions for Testing AC Characteristics

• Input signal level: VIL (Max.)/VIH (Min.)
• Output signal reference level: 2.0 V (high level), 0.8 V (low level) IOL IOH CL VREF LSI output pin DUT output Notes: C L is the total value that includes the capacitance of the measurement instrument and is set as follows for the respective pins. 30pF: All other output pins I OL = 1.6 mA and IOH = -200 mA in the test conditions. Figure 21.16 Output Load Circuit

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 724 of 758 REJ09B0243-0300

21.4 A/D Converter Characteristics

Table 21.13 A/D Converter Characteristics Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 bit A/D conversion time — — 2.0 µs Analog input capacitance — — 20 pF Permitted analog signal source impedance — — 1 * /3* k Ω Non-linear error — — ±3.0* /±5.0* LSB Offset error — — ±3.0* /±5.0* LSB Full-scale error — — ±3.0* /±5.0* LSB Quantization error — — ±0.5 LSB Absolute error — — ±4.0* /±6.0* LSB Notes: 1. It is assumed that A/D conversion time ≥ 4.0 µs. 2. It is assumed that A/D conversion time < 4.0 µs.

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 725 of 758 REJ09B0243-0300

21.5 Flash Memory Characteristics

Table 21.14 Flash Memory Characteristics Conditions: V CC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Min. Typ. Max. Unit Programming time* t P — 1 10 ms/128 bytes — 40 130 ms/4 Kbytes block — 300 800 ms/32 Kbytes block Erase time* t E — 600 1500 ms/64 Kbytes block — 1.2 3 s/128 Kbytes Programming time (total) * Σ tP — 0.6 1.5 s/64 Kbytes — 1.3 3.5 s/128 Kbytes Erase time (total) * Σ tE — 0.7 2 s/64 Kbytes — 2.5 6.5 s/128 Kbytes Programming and erase time (total) * Σ tPE — 1.3 3.5 s/64 Kbytes Reprogramming count N WEC 100 * — — Times Notes: 1. Programming/erasure time is data-dependent. 2. Programming/erasure time does not include data transfer time. 3. Minimum number to guarantee all the characteristics after reprogramming. (Guaranteed within the range from 1 to min. value) 4. Characteristics when reprogramming is performed within the specified number of times including min. value.

Section 21 Electrical Characteristics Rev. 3.00 Sep. 27, 2007 Page 726 of 758 REJ09B0243-0300

21.6 Usage Note

21.6.1 Notes on Connecting VCL Capacitor

This LSI includes an internal step-down circuit to automatically reduce the internal power supply voltage to an appropriate level. Between this internal stepped-down power supply (V CL pin) and the VSS pin, a capacitor (ranging from 0.1 to 0.47 µF) for stabilizing the internal voltage needs to be connected. Connection of the external capacitor is shown in figure 21.17. The external capacitor should be located near the pin. Do not apply any power supply voltage to the V CL pin. One capacitor ranging from 0.1 to 0.47 µF One capacitor ranging from 0.1 to 0.47 µF External power-supply stabilizing capacitor Do not apply any power supply voltage to the VCL pin. Use multilayer ceramic capacitors (one capacitor ranging from 0.1 to 0.47 µF for each V CL pin), which should be located near the pin. Note: VCL VSS VCLVSS Figure 21.17 Connection of VCL Capacitor

Rev. 3.00 Sep. 27, 2007 Page 727 of 758 REJ09B0243-0300 Appendix A. Pin States Pin initial states differ according to MCU operating modes. See section 15, Pin Function Controller (PFC), for details. Table A.1 Pin States (SH7125) Pin Function Pin State Reset State Power-Down State Type Pin Name Power-On Manual Software Standby Sleep Oscillation Stop Detected POE Function Used XTAL O O L O O O Clock EXTAL I I I I I I RES I I I I I I MRES Z I Z I Z I System control WDTOVF O * O O O O O MD1 I I I I I I ASEMD0 I * I * I * I * I * I * Operating mode control FWE I I I I I I NMI I I I I I I IRQ0 to IRQ3 Z I I I I I Interrupt IRQOUT Z O Z O Z O MTU2 TCLKA to TCLKD Z I Z I I I TIOC0A to TIOC0D Z I/O K * I/O I/O Z TIOC1A, TIOC1B Z I/O K * I/O I/O I/O TIOC2A, TIOC2B Z I/O K * I/O I/O I/O TIOC3A, TIOC3C Z I/O K * I/O I/O I/O TIOC3B, TIOC3D Z I/O Z I/O Z Z MTU2 TIOC4A to TIOC4D Z I/O Z I/O Z Z TIC5U, TIC5V, TIC5W Z I Z I I I POE POE0, POE1, POE8 Z I Z I I I POE3 I * I * Z I * I * I *

Rev. 3.00 Sep. 27, 2007 Page 728 of 758 REJ09B0243-0300 Pin Function Pin State Reset State Power-Down State Type Pin Name Power-On Manual Software Standby Sleep Oscillation Stop Detected POE Function Used SCI SCK0 to SCK2 Z I/O Z I/O I/O I/O RXD0 to RXD2 Z I Z I I I TXD0 to TXD2 Z O O * O O O AN0 to AN7 Z I Z I I I A/D Converter ADTRG Z I Z I I I I/O Ports PA0 to PA15 Z I/O K * I/O I/O I/O PB1 to PB3, PB5, PB16 Z I/O K * I/O I/O I/O PE0 to PE3 Z I/O K * I/O I/O Z PE4 to PE8, PE10 Z I/O K * I/O I/O I/O PE9, PE11 to PE15 Z I/O Z I/O Z Z PF0 to PF7 Z I Z I I I [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pull- down with a resistance of at least 1 MΩ as required. 3. Pulled-up inside the LSI when there is no input.

Rev. 3.00 Sep. 27, 2007 Page 729 of 758 REJ09B0243-0300 Table A.2 Pin States (SH7124) Pin Function Pin State Reset State Power-Down State Type Pin Name Power-On Manual Software Standby Sleep Oscillation Stop Detected POE Function Used XTAL O O L O O O Clock EXTAL I I I I I I RES I I I I I I MRES Z I Z I Z I System control WDTOVF O * O O O O O MD1 I I I I I I ASEMD0 I * I * I * I * I * I * Operating mode control FWE I I I I I I NMI I I I I I I IRQ1 to IRQ3 Z I I I I I Interrupt IRQOUT Z O Z O Z O MTU2 TCLKA to TCLKD Z I Z I I I TIOC0A to TIOC0D Z I/O K * I/O I/O Z TIOC3A, TIOC3C Z I/O K * I/O I/O I/O TIOC3B, TIOC3D Z I/O Z I/O Z Z TIOC4A to TIOC4D Z I/O Z I/O Z Z TIC5U, TIC5V, TIC5W Z I Z I I I POE POE0, POE1, POE8 Z I Z I I I SCI SCK0, SCK2 Z I/O Z I/O I/O I/O RXD0 to RXD2 Z I Z I I I TXD0 to TXD2 Z O O * O O O A/D Converter AN0 to AN7 Z I Z I I I

Rev. 3.00 Sep. 27, 2007 Page 730 of 758 REJ09B0243-0300 Pin Function Pin State Reset State Power-Down State Type Pin Name Power-On Manual Software Standby Sleep Oscillation Stop Detected POE Function Used I/O Ports PA0, PA1, PA3, PA4, PA6 to PA9 Z I/O K * I/O I/O I/O PB1, PB3, PB5 Z I/O K * I/O I/O I/O PE0 to PE3 Z I/O K * I/O I/O Z PE8, PE10 Z I/O K * I/O I/O I/O PE9, PE11 to PE15 Z I/O Z I/O Z Z PF0 to PF7 Z I Z I I I [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pull- down with a resistance of at least 1 MΩ as required. 3. Pulled-up inside the LSI when there is no input.

Rev. 3.00 Sep. 27, 2007 Page 731 of 758 REJ09B0243-0300 B. Product Code Lineup Product Type Product Code Package (Package Code) Consumer product R5F71253N50FP Industrial product R5F71253D50FP LQFP-64 (FP-64K) Consumer product R5F71253N50FA Industrial product R5F71253D50FA QFP-64 (FP-64H) Consumer product R5F71253N50NP Flash memory version (on-chip 128-kbyte) Industrial product R5F71253D50NP VQFN-64 (TNP-64BV) Consumer product R5F71252N50FP Industrial product R5F71252D50FP LQFP-64 (FP-64K) Consumer product R5F71252N50FA SH7125 Flash memory version (on-chip 64-kbyte) Industrial product R5F71252D50FA QFP-64 (FP-64H) Consumer product R5F71243N50FP Flash memory version (on-chip 128-kbyte) Industrial product R5F71243D50FP LQFP-48 (FP-48F) Consumer product R5F71242N50FP Industrial product R5F71242D50FP Consumer product R5F71242N50NP VQFN-52 Flash memory version (on-chip 64-kbyte) Industrial product R5F71242D50NP Consumer product R5F71241N50FP LQFP-48 (FP-48F) Industrial product R5F71241D50FP Consumer product R5F71241N50NP VQFN-52 SH7124 Flash memory version (on-chip 32-kbyte) Industrial product R5F71241D50NP

Rev. 3.00 Sep. 27, 2007 Page 732 of 758 REJ09B0243-0300 C. Package Dimensions Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Index mark 11 6 3348 F x y bp HE E HD D ZD ZE Detail F A c A2 A1 L P-LQFP64-10x10-0.50 0.3g MASS[Typ.] 64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A RENESAS CodeJEITA Package Code Previous Code 1.0 0.125 0.18 1.25 1.25 0.08 0.200.1450.09 0.250.200.15 MaxNomMin Dimension in Millimeters Symbol Reference 10.110.09.9D 10.110.09.9E 1.4A2 12.212.011.8 12.212.011.8 1.7A 0.150.10.05 0.650.50.35L x 8°0° c 0.5e 0.08y HD HE bp ZD ZE e Figure C.1 LQFP-64

Rev. 3.00 Sep. 27, 2007 Page 733 of 758 REJ09B0243-0300 NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *3 p E D E D xMy F Z Z D H E H b 2 1 Detail F c A A L A L Terminal cross section p c b c b PRQP0064GB-AP-QFP64-14x14-0.80 0.8 1.0 1.0 0.15 0.10 8°0° 0.250.10 0.15 0.35 0.00 0.450.370.29 0.220.170.12 3.05 16.9 17.2 17.5 D E D p E D L Z Z y x c b b A H A E A c e e L H 1.2g MASS[Typ.] FP-64H/FP-64HV RENESAS CodeJEITA Package Code Previous Code 1.10.80.5 MaxNomMin Dimension in Millimeters Symbol Reference 2.70 17.517.216.9 1.6 θ θ Figure C.2 QFP-64

Rev. 3.00 Sep. 27, 2007 Page 734 of 758 REJ09B0243-0300 PLQP0048JA-AP-LQFP48-10x10-0.65 1.425 11.8 12.0 12.2 0.13 0.60.50.4 0.15 0.30 1.45 12.212.011.8 1.70 0.150.10.05 0.370.320.27 0.220.170.12 0.65 8°0° 0.10 1.0 1.425 FP-48F/FP-48FV RENESAS CodeJEITA Package Code Previous Code MaxNomMin Dimension in Millimeters Symbol Reference 0.4g MASS[Typ.] E D p E D L Z Z y x c b b A H A E D A c e e L H Index mark y Mx F 11 2 D E D E pb Z Z H H D E Detail F c A L A L A p Terminal cross section b c c b θθ NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Figure C.3 LQFP-48

Rev. 3.00 Sep. 27, 2007 Page 735 of 758 REJ09B0243-0300 0.95 0.60 0.16 0.05 0.2 0.2 0.22 Reference Symbol Dimension in Millimeters Min Nom Max 8.2 8.2 0.20 0.4 1.0 1.0 8.0 8.0 0.05 0.230.180.13 t Lp y x b A E D e HD c HE 0.89 0.005 0.02 0.04 0.50 0.70 0.17 0.25 ZD ZE 2 1 49 32 48 33 x nb1 p 1 c E D D E y x4 t b L e c A AA Z Z H E H D P-VQFN64-8x8-0.40 0.12g MASS[Typ.] TNP-64B/TNP-64BVPVQN0064LB-A RENESAS CodeJEITA Package Code Previous Code Figure C.4 VQFN-64

Rev. 3.00 Sep. 27, 2007 Page 736 of 758 REJ09B0243-0300 NOTE) DO NOT INCLUDE MOLD FLASH. ZE ZD HE c HD e D E A b x y Lp t 0.13 0.18 0.23 0.05 7.0 7.0 1.1 1.1 0.4 0.20 7.2 7.2 MaxNomMin Dimension in Millimeters Symbol Reference 0.22 0.20 0.20 0.05 0.16 0.60 0.95 0.89 0.005 0.02 0.04 0.50 0.70 0.17 0.25 39 27 p 1 c E D D E y nxx4 t A A A Z Z b e H D H E L c P-VQFN52-7x7-0.40 0.095g MASS[Typ.] -PVQN0052LE-A RENESAS CodeJEITA Package Code Previous Code Figure C.5 VQFN-52

Rev. 3.00 Sep. 27, 2007 Page 737 of 758 REJ09B0243-0300 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) – – Added VQFN-64 and VQFN-52 specifications Descriptions of on-chip 32-kbyte flash memory for SH7124 Deleted Items Specification Multi-function timer pulse unit 2 (MTU2)

• Pulse output modes One shot, toggle, PWM, complementary PWM, and reset-synchronized PWM modes Table 1.1 Features 4 Amended Instruction T Bit SUBV Rm,Rn Underflow Table 2.12 Arithmetic Operation Instructions

4.1 Features 55 Deleted

• Five clocks generated independently An internal clock (If) for the CPU and cache; a peripheral clock (Pf) for the on-chip peripheral modules; a bus clock (Bf = CK) for the external bus interface; and a MTU2 clock (MPf) for the on-chip MTU2 module. Table 4.4 Frequency Division Ratios Specifiable with FRQCR

60 Deleted

Notes: 2. The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. This output frequency must be 50 MHz or lower.

Rev. 3.00 Sep. 27, 2007 Page 738 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

4.4.1 Frequency Control Register

(FRQCR)

61 Added/Deleted

Before making changes to FRQCR, set the module stop bit in the standby control register 2, 3, 4, 5, and 6 to 1 and stop clock supply to each module except the CPU, on-chip ROM, and on-chip-RAM. Added Bit Bit Name Description 14 to 12 IFC[2:0] Internal Clock (Iφ) Frequency Division Ratio If a prohibited value is specified, subsequent operation is not guaranteed. 11 to 9 BFC[2:0] Bus Clock (Bφ) Frequency Division Ratio If a prohibited value is specified, subsequent operation is not guaranteed. 8 to 6 PFC[2:0] Peripheral Clock (Pφ) Frequency Division Ratio If a prohibited value is specified, subsequent operation is not guaranteed. 2 to 0 MPFC[2:0] MTU2 Clock (MPφ) Frequency Division Ratio If a prohibited value is specified, subsequent operation is not guaranteed. (FRQCR) 62,

4.5 Changing Frequency 65 Added/Deleted

1. The clock frequencies are immediately changed to the specified values after FRQCR setting is completed. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11Bf + 7Pf. n: Division ratio specified by the BFC bit in FRQCR cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Note: (1 to 24n) depends on the internal state.

Rev. 3.00 Sep. 27, 2007 Page 739 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Added Conditions for Transition to Reset State Internal State Type RES WDT overflow MRES CPU, INTC On-Chip Peripheral Module POE, PFC, I/O Port Power- on reset High Overflow High Initialized Initialized Initailzed High Not overflowed Low Initialized Not initialized Not initialized Manual reset High Overflow High Initialized Not initialized Not initialized Table 5.5 Reset Status 75

7.2.13 Branch source Register

(BRSR)

132 Amended

This flag bit is cleared to 0 by a power-on reset or manual reset when BRSR is read or, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset.

7.2.14 Branch Destination

Register (BRDR)

133 Amended

This flag bit is cleared to 0 by a power-on reset or manual reset when BRDR is read or, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. Amended On-chip Peripheral Module INTC PFC, Port Connection Bus Width 16 16 Number of Access Cycles (1 + n) × lclk + (1 + m) × Bclk + 2 × Pclk Write (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk Number of Access Cycles Read (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk + 2 × Iclk Table 8.2 Connection Bus Width of on-chip Peripheral Module and the Number of Access Cycles 148

Rev. 3.00 Sep. 27, 2007 Page 740 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

8.4 Access to on-chip Peripheral

148 Added

The L bus access takes one Iclk cycle, I bus access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer to the I bus is a period of 3 Iclk cycles.

148 Amended

In the case shown in figure 8.1, where Bclk = Pclk = 1:1, the timeperiod required for access by the CPU is (13 + n) × Iclk + 1 × Bclk + 2 × Pclk.

149 Amended

When Iclk:Bclk = 1:1, a period of 3 Iclk + Bclk is required. In the case shown in figure 8.2, where Bclk = Pclk = 1:1, the timeperiod required for access by the CPU is (13 + n) × Iclk + 1 × Bclk + 2 × Pclk. Figure 8.2 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:4:1) 149, 150 Added Figure 8.3 shows an example of timing of read access to the peripheral bus when Iclk:Bclk:Pclk = 4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for write access. In the case of reading, however, values output onto the peripheral bus must be transferred to the CPU. Transfers from the external bus to the I bus and from the I bus to the L bus are again performed in synchronization with rising edges of the respective bus clocks. 2 × Iclk cycles of period is required because Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where n = 0 and m = 1, the period required for access by the CPU is 3 × Iclk + 2 × Bclk + 2 × Pclk + 2 × Iclk.

Rev. 3.00 Sep. 27, 2007 Page 741 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Figure 8.3 Timing of Read Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:2:1)

150 Added

TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Input capture register Capture at trough in complementary PWM mode Table 9.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) 187

Rev. 3.00 Sep. 27, 2007 Page 742 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Figure 9.41 Example of Operation without Dead Time

278 Amended

Compare register TGRA_4 Output waveform Output waveform Output waveform is active-low. Data1 Data2 Initial output Initial output Figure 9.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0)

305 Changed

Figure 9.78 Example of External Pulse Width Measurement (Measuring High Pulse Width)

312 Amended

0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 TIC5U TCNT5_U MPφ 0007 000A 000B

9.7.22 Simultaneous Capture of

TCNT_1 and TCNT_2 in Cascade Connection

347 Added

The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input- capture input as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time.

10.6.1 Pin State when a Power-

On Reset is Issued from the Watchdog Timer

400 Added

When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (Pf), after which the function is switched to general input. This also occurs when a power-on reset is issued from the WDT for pins that are being handled as high impedance due to short-circuit detection by the MTU2 and MTU2S. Figure 10.5 shows the state of a pin for which the POE input has selected high impedance handling with the timer output selected when a power-on reset is issued from the WDT.

Rev. 3.00 Sep. 27, 2007 Page 743 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Figure 10.5 Pin State when a Power-On Reset is Issued from the Watchdog Timer Timer outputPin state General input Timer output General input High impedance state Timer output 1Pφ cycle POE input Pφ PFC setting value Power-on reset by WDT Figure 11.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock is Specified to Pφ/32 by CKS2 to CKS0)

409 Added

(power-on reset selected) Internal reset signal (manual reset selected)

35 Pφ + one cycle of count clock

12.3.2 Receive Data Register

(SCRDR)

415 Amended

Bit: Initial value: R/W: 7654321 0 R RR R R R R R - -- - -- --

12.3.4 Transmit Data Register

(SCTDR)

416 Amended

Bit: Initial value: R/W: 7654321 0 R/W R/W R/W R/W R/W R/W R/W R/W - ---- - - -

12.3.8 Serial Port Register

(SCSPTR)

428 Amended

Bit: Initial value: R/W: 76543210 00000 0 R/W - - - R/W R/W Undefined R/W Undefined EIO - - - SPB1IO SPB1DT - SPB0DTSPB0IO WW

Rev. 3.00 Sep. 27, 2007 Page 744 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Amended Bit Bit Name Initial Value R/W Description

2 SPB1DT Undefined

R/W Clock Port Data in Serial Port Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output

1 SPB0IO

Controls the TxD pins together with the TE bit in SCSCR and the SPB0DT bit. Reserved This bit is always read as 0. The write value should always be 0.

0 SPB0DT Undefined

W …SC SCR …SP B0IO bit …SP B0DT bit TxD pin… 0 0 0 Settin g prohib ited (initial state) 1 * * Low output (SCSPTR) 429

Rev. 3.00 Sep. 27, 2007 Page 745 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

12.4.3 Clock Synchronous Mode

(Channel 1 in the SH7124 is not Available)

455 Added

When only reception is performed, the synchronous clock continues to be output until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source. If the internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same time as receiving the n characters of data.

12.4.4 Multiprocessor

463 Amended

On reception of receive character with a 1 multiprocessor bit, the MPB bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed.

12.4.5 Multiprocessor Serial Data

465 Description added. 12.7.4 Sending a Break Signal 472 Description of the SPB0IO bit deleted.

13.4.2 Continuous Scan Mode 488 Deleted

In 2-channel scan mode, since the channels are divided into group 0 and group 1, even though group 0 is operating in continuous scan mode, the contents of the A/D data registers for group 1 are retained. Similarly, even though group 1 is operating in continuous scan mode, the contents of the A/D data registers for group 0 are retained. Note that a group 1 conversion request issued during group 0 A/D conversion is ignored. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request. In 2-channel scan mode, when A/D conversion is to be started by software, selection of group 0 or group 1 is determined by the CH2 to CH0 bits in ADCSR_0 to ADCSR_1. When A/D conversion is to be started by triggering, regardless of the setting of the CH2 to CH0 bits in ADCSR_0 to ADCSR_1, A/D conversion for group 0 is started by the trigger source set by the TRG0S3 to TRG0S0 and TRG1S3 to TRG1S0 bits in ADTSR, and A/D conversion for group 1 is started by the trigger source set by the TRG01S3 to TRG01S0 and TRG11S3 to TRG11S0 bits in ADTSR.

Rev. 3.00 Sep. 27, 2007 Page 746 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

13.4.3 Single-Cycle Scan Mode 489 Deleted

In 2-channel scan mode, since the channels are divided into group 0 and group 1, even though group 0 is operating in single-cycle scan mode, the contents of the A/D data registers for group 1 are retained. Similarly, even though group 1 is operating in single-cycle scan mode, the contents of the A/D data registers for group 0 are retained. Note that a group 1 conversion request issued during group 0 A/D conversion is ignored. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request. In 2-channel scan mode, when A/D conversion is to be started by software, selection of group 0 or group 1 is determined by the CH2 to CH0 bits in ADCSR_0 to ADCSR_1. When A/D conversion is to be started by triggering, regardless of the setting of the CH2 to CH0 bits in ADCSR_0 to ADCSR_1, A/D conversion for group 0 is started by the trigger source set by the TRG0S3 to TRG0S0 and TRG1S3 to TRG1S0 bits in ADTSR, and A/D conversion for group 1 is started by the trigger source set by the TRG01S3 to TRG01S0 and TRG11S3 to TRG11S0 bits in ADTSR. 13.4.7 2-Channel Scanning 493 Added In 2-channel scan mode, since the four channels of analog input are divided into groups 0 and 1, triggers for activation of groups 0 and 1 are independently specifiable. Conversion end interrupts in 2-channel scan mode can be generated either on completion of group 0 or group 1 or on completion of group 0 and group 1. If conversion is to be started by triggers, the different sources for groups 0 and 1 are specified in ADTSR. A request for conversion by group 1 generated during conversion by group 0 is ignored. Figure 13.4 shows an example of operation when TRG4AN of the MTU2 has been specified as the A/D conversion start request by group 0 and TRG4BN of the MTU2 has been specified as the A/D conversion start request by group

Rev. 3.00 Sep. 27, 2007 Page 747 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Figure 13.4 Example of 2-Channel Scanning

493 Added

TADCORA_4 TGRA_3 TADCORB_4 H'0000 TCNT_4 A/D conversion start request CONADF bit in ADCSR = 1 CONADF bit in ADCSR = 0 A/D conversion end (ADF) AN0 conversion AN1 conversion AN2 conversion AN3 conversion

13.6 Definitions of A/D Conversion

495 Amended

(see figure 13.413.5) (see figure 13.513.6) Figure 13.5 Definitions of A/D Conversion Accuracy 496 Figure 13.413.5) Figure 13.6 Definitions of A/D Conversion Accuracy 497 Figure 13.513.6

13.7.2 Permissible Signal Source

498 (see figure 13.613.7)

13.7.4 Range of Analog Power

Supply and Other Pin Settings

499 AVss ≤ VAN ≤ AVccAVref

13.7.6 Notes on Noise

500 A protection circuit should be connected in order to

prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown in figure 13.713.8. Figure 13.8 Example of Analog Input Protection Circuit 500 Figure 13.713.8

Rev. 3.00 Sep. 27, 2007 Page 748 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

17.1 Features 573 Amended

This mode uses the dedicated socket adapter and PROM programmer.

17.1 Features 574 Amended

The operating frequency at programming/erasing is a maximum of 40 MHz (Pφ).

17.2.3 Mode Comparison 577 Amended

The comparison table of programming and erasing related items about boot mode, and user program mode, and programmer mode is shown in table 17.2. Amended Programming/ erasing environment On-Board Programming Writer Mode Boot Mode User Program Mode Off-Board Programming Table 17.2 Comparison of Programming Modes 577

17.4.3 Programming/Erasing

597 Amended

Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT.

17.5.2 User Program Mode (Only

in On-Chip 128-Kbyte and 64- Kbyte ROM Version)

611 Added

After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. in On-Chip 128-Kbyte and 64- Kbyte ROM Version)

616 Added

After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value.

17.7.2 Other Notes 623 Amended

Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum.

Rev. 3.00 Sep. 27, 2007 Page 749 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

17.8.1 Specification of the

Standard Serial Communications Interface in Boot Mode

631 Amended

Size (1 byte): Number of characters in the device code (fixed at 4)

17.9 Off-Board Programming

656 Amended

A PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-Kbyte flash memory on-chip MCU device type (F-ZTAT128DV5).

18.1.3 Initial Values in RAM 658 Added

After power has been supplied, initial values in RAM remain undefined until RAM is written. Amended Bit Bit Name Description 4, 3  This bit is always read as 1. The write value should always be 1.

19.3.4 Standby Control Register 4

(STBCR4) 665 Amended Bit Bit Name Description 1, 0 MSTP[25:24] 00: UBC operates 01: Setting prohibited 10: Setting prohibited 11: Clock supply to UBC halted

19.3.5 Standby Control Register 5

(STBCR5) 666 Amended Bit Bit Name Description

7 UBCRST UBC Software Reset

Resetting the PC trace unit of UBC is controlled by software. Clearing this bit to 0 puts the PC trace unit of the UBC module into the power-on reset state. 0: Puts the PC trace unit of UBC into the reset state 1: Releases reset in the PC trace unit of UBC

19.3.6 Standby Control Register 6

(STBCR6) 667

Rev. 3.00 Sep. 27, 2007 Page 750 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details)

19.4.2 Canceling Sleep Mode 669 Added

Do not cancel sleep mode with an interrupt.

19.7.2 Executing the SLEEP

672 Added

Apply either of the following measures before executing the SLEEP instruction to initiate the transition to sleep mode or software standby mode. Measure A: Stop the generation of interrupts from on- chip peripheral modules, IRQ interrupts, and the NMI interrupt before executing the SLEEP instruction. Measure B: Change the value in FRQCR to the initial value, H'36DB, and then dummy-read FRQCR twice before executing the SLEEP instruction. Amended Item MD1, FWE setup time

21.3.2 Control Signal Timing 712

Figure 21.5 Reset Input Timing 713 Amended MD1, FWE Amended Item Symbol Port output data delay time (reference values) tPWD Port input low pulse width tPRWL Port input high pulse width tPRWH Table 21.8 I/O Port Timing 717

Rev. 3.00 Sep. 27, 2007 Page 751 of 758 REJ09B0243-0300 Item Page Revision (See Manual for Details) Figure 21.10 I/O Port Input/Output Timing 717 tPRWH/L tPWD CK Port (read) Port (write) Amended Item Min. Transmit data delay time  Receive data setup time 2 tpcyc + 50 Receive data hold time Clock synchronous 2 tpcyc + 50 Table 21.10 Serial Communication Interface (SCI) Timing 719 Amended Product Type Product Code Package (Package Code) R5F71253N50FP R5F71253D50FP LQFP-64 (FP-64K) R5F71253N50FA Flash memory version (on-chip 128-kbyte) R5F71253D50FA QFP-64 (FP-64H) R5F71252N50FP R5F71252D50FP LQFP-64 (FP-64K) R5F71252N50FA SH7125 Flash memory version (on-chip 64-kbyte R5F71252D50FA QFP-64 (FP-64H) R5F71243N50FP Flash memory version (on-chip 128-kbyte) R5F71243D50FP R5F71243N50FA SH7124 Flash memory version (on-chip 64-kbyte) R5F71243D50FA LQFP-48 (FP-48F) B. Product Code Lineup 731

Rev. 3.00 Sep. 27, 2007 Page 752 of 758 REJ09B0243-0300

Rev. 3.00 Sep. 27, 2007 Page 753 of 758 REJ09B0243-0300 Index A A/D converter start request AC characteristics measurement B C Calculating exception handling vector D E F

Rev. 3.00 Sep. 27, 2007 Page 754 of 758 REJ09B0243-0300 G H I Initiation intervals of user branch Interrupt exception handling L M Module standby mode Multi-function timer pulse Multiply and accumulate registers Multiprocessor communication N Notes on connecting V Notes on slot illegal instruction O P

Rev. 3.00 Sep. 27, 2007 Page 755 of 758 REJ09B0243-0300 Pin states of this LSI in each Q R Range of analog power supply and Register

Rev. 3.00 Sep. 27, 2007 Page 756 of 758 REJ09B0243-0300 Register address table (in the order Register states in each operating mode ... 696 S

Rev. 3.00 Sep. 27, 2007 Page 757 of 758 REJ09B0243-0300 Serial communication interface (SCI) .... 411 Stack after interrupt exception Stack states after exception T Target pins and conditions for high- The address map for the operating U V Vector numbers and vector table W

Rev. 3.00 Sep. 27, 2007 Page 758 of 758 REJ09B0243-0300

Renesas 32-Bit RISC Microcomputer Hardware Manual SH7125 Group, SH7124 Group Publication Date: Rev.1.00, Mar. 25, 2005 Rev.3.00, Sep. 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2007. Renesas Technology Corp., All rights reserved. Printed in Japan.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology Singapore Pte. Ltd.

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SH7125 Group, SH7124 Group Hardware Manual