SH3002

SH3002 SEMTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 22

Technical content

Features

♦ Highly integrated IC - 3 mm x 3 mm x 0.9 mm 16-lead MLP (QFN) package ♦ CPU Supervisor - Low VDD reset programmable from 2.3 V to 4.3 V - Both active-high and active-low reset outputs ♦ Clock Management System - Replaces high-frequency (HF) crystal or resonator - Programmable clock output from 32.768 kHz to 16 MHz - Speed shift between multiple clock frequencies - Adjustable spectrum spreading for EMI reduction - Directly supports microcontroller STOP function - Deep sleep with instantaneous auto-wakeup ♦ Operates from 2.3 V to 5.5 V - Ideal for battery-operated devices ♦ I DD <850 µA / 2 MHz, <3 mA / 16 MHz, <10 µA / standby Pin Configuration 3mm MLP (QFN) Package SH3002 µB TM 5 6 7 8 16 15 14 13 VSS VREG VDD NC NC NC VSS VSS RREF NRST TEST (VSS) RST CLK32 IO/INT CLKIN CLKOUT Typical Application Circuit SH3002 µB TM µController VDD XIN XOUT GPIO WITH INT NRESET GND CBYPASS Covered by US Patent No. 6,903,986 Semtech, the Semtech logo, MicroBuddy, µBuddy, and µB are marks of Semtech Corporation. All other marks belong to their respective owners.

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 2 V1.20 www.semtech.com

Description

Ordering Information

SH3002IMLTR IC MLP 3 x 3 mm, 16 pins, temp. range -40° C to +85° C EVK-SH3000USB SH3000 evaluation kit SH3000EK.pdf SH3000 Evaluation Kit User Guide SH3000UM.pdf SH3000 Reference Manual Block Diagram CLK32 Microcontroller VDD 32.768 KHZ XIN XOUT RESET I/O PIN VSS NC VREG LF Oscillator Reset Drivers & Logic VDD Monitor HF Oscillator & FLL Periodic Interrupt / Wake-up Timer RC Oscillator Regulators Nonvolatile Memory Calibration & Default Settings Serial I/O Control Logic Clock Driver & Start/Stop Logic Post-scaler 2 3 1516 Interrupt VDD VSS NC NC Voltage Reference CLKOUT CLKIN RREF RST NRST TEST IO/INT SH3002 µBuddy™ VSS

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 3 V1.20 www.semtech.com Pin Descriptions Pin Name Type Function 1 V SS Power Ground, 0 V. All V SS pins and TEST (VSS) pin must be connected together.

2 V REG Power

Output of internal Voltage Regulator, 2.2 V nominal. This pin can power external loads of <5 mA. If load is “noisy” it requires a bypass capacitor. May be left unconnected or used as a high logic level signal for CLKSEL pin (see below). 3 V DD Power Main power supply, +2.3 to +5.5 V.

4 NC Not connected - reserved

5 NC Not connected - reserved

6 NC Not connected - reserved

7 V SS Power Ground, 0 V. All V SS pins and TEST (VSS) pin must be connected together. 8 V SS Power Ground, 0 V. All V SS pins and TEST (VSS) pin must be connected together. 9 R REF Analog Optional 1 MOhm external bias resistor for the internal 32.768 kHz RC oscillator. Can be used to set, trim or modulate the internal RC oscillator. Keep open if not used.

10 NRST Digital Out

Active low system reset output. Asserted with a strong low state when a reset condition occurs. Weakly pulled to VDD internally when not active. This signal is valid for VDD as low as 1 V. Keep open if not used.

11 RST Digital Out

Active high system reset output. Asserted with a strong high state when a reset condition occurs. Weakly pulled to VSS internally when not active. This signal is valid for VDD as low as 1 V. Keep open if not used. 12 T EST (VSS) Digital In Factory test enable. All V SS pins and TEST (VSS) pin must be connected together.

13 CLK32 Digital Out

Buffered internal 32.768 kHz clock, derived according to the CLKSEL pin setting. This pin uses backup power for the buffer when VDD is not present. When driving high, this signal is either at VBAK or VDD (if VDD is higher than the reset threshold). When enabled, this signal runs continuously independent of CLKOUT activity. Minimize the external load to reduce power consumption during backup operations. When disabled, this pin is driven to VSS. Keep open if not used.

14 IO/I NT I/O

Serial communications interface and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to VDD when inactive. Keep open if not used.

15 CLK IN Digital In

Clock activity sense input. Used to detect when the target microcontroller enters stop mode (which disables its clock). Connect to the microcontroller’s clock output or oscillator output pin. Connect to VSS when not used. CLKIN must not be left open. 16 CLK OUT Digital Out Programmable high frequency clock output. Connect to the target microcontroller’s clock input or oscillator input pin. Keep open if not used.

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 4 V1.20 www.semtech.com Functional Description The SH3002 is a single-chip support system for microcontrollers, microprocessors, DSPs and ASICs. It consists of four major functional blocks, each block having numerous enhancements over alternative solutions. The major modules are the CPU Supervisor, the Clock Management System, and the Auxiliary functions. The entire chip is controlled by the set of internal registers and accessed via the single-pin serial interface. All of the settings, configuration, and calibration or operating parameters are programmable and re- programmable at any time. All of the parameters required for stand-alone operations are initialized on reset from the built-in factory-programmed nonvolatile memory. This allows the SH3002 to operate autonomously for most of its supervisory functions. The stand-alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential benefit of the SH3002 might not be realized. In the preferred configuration, where the SH3002 is tightly coupled to the target micro, the SH3002 offers an unprecedented level of design flexibility in clock and power usage management. The SH3002 is a particularly desirable integration because the built-in features interact and meld to produce more useful system level functions. For example, on power up, the SH3002 can quickly release the reset lines on its CPU Supervisor module because the clock signal from the Clock Management System is guaranteed to be running and stabilized. An ordinary reset circuit must hold reset active for a long time to allow an unknown crystal to start up and stabilize. The SH3002 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as necessary with no external support. The clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. Users should consider the interactions of the major functional blocks to gain the maximum advantage from the SH3002. The individual functional blocks are described in the following sections.

monitor (Brownout Detector), see Figure 1. system solution than stand-alone components. source of the reset to the system software. steps of 33 mV, see Table 1. Table 1. Programmable VBO Values guaranteed to be valid for a VDD level of 1.0 V. power glitching is present). from the beginning of the brownout). and unpredictable crystal start-up times. initialization of the target micro can proceed normally. Figure 1. CPU Supervisor --- Low VDD / Brownout Detector, Watchdog, Reset logic & Drivers

frequency” clock synthesizer (see Figure 4). (and HF oscillator stopped for energy savings). the host processor issued a STOP instruction. approach can be as much as 100x – 10,000x slower. post-divider (see Figure 4). ± 0.025%, and maintain it to ± 0.5% over temperature. performance and functionality. Oscillator System is described later in this document. Figure 4. Simplified HF Oscillator System

requires a long settling time on re-start. output frequency of 1.024 MHz. EMI standards is costly and complicated. figures in the 8-16 MHz range. according to the configuration setting. A microcontroller might not have a STOP command. internal RAM alive while the clock is stopped. Table 2. EMI reduction with Spectrum Spreading

0 X X Off 0 0

circuits and to the dedicated output pin, CLK32. over the entire temperature and supply voltage range.

1 MΩ 1% or

Figure 5. Simplified LF Oscillator System

used to create alarms, with practically unlimited duration. go back to sleep, until the next periodic interrupt. 36.4 hours, creates the Timer. current value from the counter can be read at any time. Timer Value latch when the least significant byte is read. a low ripple reference is required. Figure 6. Periodic Interrupt / Wakeup timer

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 11 V1.20 www.semtech.com Interrupt and Serial Interface A single line is used to convey bi-directional information between the SH3002 and the processor, and as the interrupt line to the processor. The polarity of the interrupt signal is programmable. The SH3002 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. The bit rate is automatically determined by the SH3002. . At the fastest possible rate, a read or write access of a single byte from the register bank takes 5 µs. The SH3002 contains 36 addressable registers located at 0x00–0x1F. Some of these registers are accessed through a page operation. Pin 14, IO/Int, is the serial communications interface and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to V DD when inactive. As shown in Figure 7, the SH3002 and the host communicate with serial data streams. The host always initiates communication. A data stream consists of the following (in this order):

• 3-bit start field
• 3-bit read/write code
• 5-bit address field
• 1 guard bit
• 8-bit data field
• 2 parity bits Plus, for write streams only:
• 1 guard bit
• 2 acknowledge (ACK) bits The 3-bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. The 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. This protects against early glitches that might otherwise put the interface into an invalid read or write access mode. The 5-bit address field contains the address of the register. A single guard bit gives the interface a safe period in which to change data direction. The value of a guard bit does not matter. The 8-bit data field is written to (read from) the register. Two parity bits: The first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit is the inverse of the first. For write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write access. Two guard bits are appended to the end of the access stream (read or write). The host can not start the next access before receiving these bits. The interface is self-timed based on the duration of the start bit field, and communication can take place whenever CLK OUT is active, either at 32.768 kHz or at a higher frequency. If the host microcontroller is running synchronously to the CLK OUT generated by the SH3002 (which should generally be the case), then a minimum of

4 CLKOUT cycles per bit are required to maintain

communication integrity. If the host’s serial interface is asynchronous to CLKOUT, then a minimum of 52 cycles per bit are necessary. A maximum of 1024 CLKOUT cycles per bit field is supported. Table 3 displays the minimum and maximum bit periods for the serial communications for CLKOUT frequencies of 16 MHz, 8 MHz, and 2 MHz. Table 3: Minimum/Maximum Serial Bit Timing CLKOUT Frequency Minimum Bit Period (host synchronous to CLKOUT) Minimum Bit Period (host asynchronous to CLKOUT) Maximum Bit Period 16 MHz 250 ns 3.25 µs 63.9 µs 8 MHz 500 ns 6.5 µs 127 µs

2 MHz 2 µs 26 µs 511 µs

The serial communications line to the SH3002 (Pin 14, IO/Int) also serves as the interrupt to the host microcontroller. The polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the IPol_RCtune register (R0x11). This pin is asserted for four cycles of CLK OUT, and then returns to the inactive state. The interrupt line is used by the Periodic Interrupt/Wake-up Timer to interrupt the host when it reaches its end of count.

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 12 V1.20 www.semtech.com IO/INT timing scenarios 1. INT disabled, uP initiates write access. Active high interrupt. uBuddyIOOut uPIOOut A0 A4 XXX D0 D7... 2. INT active (high), uP initiates write access uBuddyIOOut uPIOOut CombinedIO XXX State Idle Pre- start Start Post- XXX State If the interrupt did not get cleared, then it will activate again here 4. INT disabled, uP initiates read access uBuddyIOOut uPIOOut A0 A4 XXX... State Idle Pre- start Start Post- D0 D7... P0 P1 P0 P1 P0 P1 P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 A0 A4 XXX D0 D7... XXX Pre- start Start Post- XXX P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 ACK0 ACK1 Guard2 Guard3 Guard2 Guard3Pendin g-start IN TIdle Pendin g-start IN T 3. INT active (low), uP initiates write access uBuddyIOOut uPIOOut CombinedIO State If the interrupt did not get cleared, then it will activate again here A0 A4 XXX D0 D7... XXX Pre- start Start Post- XXX P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 Guard2 Guard3Pendin g-start IN TIdle Pendin g-start IN T ACK0 ACK1 RW0 RW1 RW2 Guard3 Figure 7: Serial Communication Timing Diagram

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 13 V1.20 www.semtech.com Note: The SH3002 is ESD-sensitive. Description Symbol Min Max Units Supply voltages on VDD relative to ground V DD -0.5 5.5 V Input voltage on CLKIN, IO/INT, TEST V IN1 -0.5 V DD + 0.5 V Input voltage on CLKSEL V IN2 -0.5 V REG + 0.5 V Input current on any pin except VREG I IN1 10 mA Input current on VREG I IN2 150 mA Ambient operating temperature T OP -40 85 ºC Storage temperature T STG -55 160 ºC Operating Characteristics Parameter Symbol Min Typ Max Units Notes Case temperature T OP –40 +85 °C Supply voltage V DD 2.3 5.5 V Supply current, CLKOUT = 16 MHz* I DD 3 mA Supply current, CLKOUT = 8 MHz* I DD 1.8 mA Supply current, CLKOUT = 2 MHz* I DD 0.9 mA Standby current, 32.768 kHz RC oscillator** I SB 10 µA CLK32 disabled *Note: Assuming load on CLK OUT < 20 pf **Note: Assuming temperature < 60ºC Electrical Specifications Absolute Maximum Ratings

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 14 V1.20 www.semtech.com Operating characteristics of 32.768 kHz RC oscillator Parameter Symbol Min Typ Max Units External 1 MOhm referenced nominal frequency Fext 32.768 kHz Internal 1 MOhm referenced nominal frequency Fint 32.768 kHz CLK32 duty cycle DC 40 60 % Programmed frequency accuracy at 25°C Fst -1.5 +1.5 % Absolute accuracy over temperature and supply (external 1 MOhm) Fde ±2 % Absolute accuracy over temperature and supply (internal 1 MOhm) Fdi ±3 % Frequency temperature stability (ext. 1 MOhm) Fse 100 ppm/°C Frequency temperature stability (int. 1 MOhm) Fsi 200 ppm/°C Power on startup time Tst 70 µs CLK32 cycle to cycle jitter J 0.1 % Operating characteristics of programmable reset Parameter Symbol Min Typ Max Units VDD switching threshold for Min code (Start-up default = 2.3 V) Vbo(min) 2.27 2.3 2.33 V VDD switching threshold for Max code Vbo(max) 4.2 4.3 4.4 V VDD threshold resolution Vres 33 mV VDD hysteresis Vhys 50 mV Falling VDD threshold switch delay Td 2.5 µs Threshold digital-analog converter (DAC) settling time Tdac 4 ms Minimum VDD for valid nRST VDDmin 1 V

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 15 V1.20 www.semtech.com Operating characteristics of the high-frequency oscillator (HFO) Parameter Symbol Min Typ Max Units Minimum operating frequency (Start-up default = 2 MHz) Fmin 5.6 8 MHz Maximum operating frequency Fmax 16.8 21 MHz Frequency resolution Fres 2 kHz Programmed frequency accuracy at 25°C Fst -0.3 +0.3 % Frequency drift over temperature and supply Fdrift ±0.5 % CLKOUT cycle to cycle jitter (spread spectrum off) J 0.1 % Startup time from standby Tstart 2 µs Settling time to 0.1% after HF digitally-controlled oscillator (DCO) code change Tsett 10 µs CLKOUT duty cycle DC 40 60 % Frequency temperature stability Fts 100 ppm/°C Short term frequency stability Fs 0.5 %/sec Minimum spread spectrum range SSmin 32 kHz Maximum spread spectrum range SSmax 256 kHz CLKOUT rise/fall time (20 pF load) Trf 3 ns CLKOUT logic output low (4 mA load) Vol 0.25 0.4 V CLKOUT logic output high (4 mA load) Voh -0.4 -0.25 Ref V DD

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 16 V1.20 www.semtech.com Free Running HF DCO Frequency Deviation over Temperature for All Frequencies -16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 2000 4000 -60 -40 -20 0 20 40 60 80 100 120 140 Temp. ºC ppm Deviation Internal 32.768 kHz Oscillator Frequency over Temperature 31800 32000 32200 32400 32600 32800 33000 33200 33400 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (ºC) Frequency (Hz)

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 17 V1.20 www.semtech.com Standby Current over Temperature (VDD = 5 V) 0.0 5.0 10.0 15.0 20.0 25.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (ºC) VDD Current (µA) Internal 32.768 kHz Standby current over VDD (Temp. = 25ºC) 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD Current (µA) Internal 32.768 kHz

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 18 V1.20 www.semtech.com VDD Current vs CLKOUT Frequency (VDD = 5.5 V, Temp. = 25ºC) 500 1000 1500 2000 2500 3000 3500 02468 1 0 1 2 1 4 1 6 1 8 Frequency (MHz) VDD Current (µA) Operating VDD Current over VDD (CLKOUT = 16 MHz, Temp = 25ºC) 2000 2200 2400 2600 2800 3000 3200 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD Current (µA)

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 19 V1.20 www.semtech.com Free Running HF DCO Short Term Frequency Stability (CLKOUT = 8 MHz) -400 -300 -200 -100 100 200 300 -500 500 1500 2500 3500 4500 5500 6500 Time (seconds) ppm Deviation FLL Locked HF DCO Jitter over Jitter Bandwidth (CLKOUT = 12.8 MHz) 100 1000 10000 100000 0.1 1 10 100 1000 10000 100000 Jitter Bandwidth (kHz) rms Jitter (ps)

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 20 V1.20 www.semtech.com Package Outline Drawing MLP 3 x 3 mm 16 pins

SH3002 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 21 V1.20 www.semtech.com For sales information and product literature, contact: Semtech Corporation Human Interface Device (HID) and System Management Division

200 Flynn Road

Camarillo, CA 93012-8790 sales@semtech.com http://www.semtech.com/ (805)498-2111 Telephone (805)498-3804 Fax Copyright ©2002-2003 Semtech Corporation. All rights reserved. Semtech, the Semtech logo, MicroBuddy, µBuddy, and µB are marks of Semtech Corporation. All other marks belong to their respective owners. LIMITED LICENSE GRANTED: NO WARRANTIES MADE This specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Any suggestions or comments by Semtech concerning use of this product are opinion only, and Semtech makes no warranty as to results to be obtained in any specific application. A license is hereby granted to reproduce and distribute this specification for internal use only. No other license, expressed or implied to any other intellectual property rights is granted or intended hereby. Authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. Authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.

Filename: sh3002.doc Directory: U:\\working file\\nathan\\08_09_05 Template: C:\\Documents and Settings\\lcarey\\Application Data\\Microsoft\\Templates\\Normal.dot Title: SH3002 MicroBuddy™ data sheet Subject: Reset Management and Clock Management Support IC for Microcontrollers Author: Semtech Corporation Keywords: Comments: Creation Date: 1/24/2003 10:42 AM Change Number: 75 Last Saved On: 8/8/2005 9:40 AM Last Saved By: NJohn Total Editing Time: 260 Minutes Last Printed On: 8/9/2005 2:34 PM As of Last Complete Printing Number of Pages: 21 Number of Words: 4,388 (approx.) Number of Characters: 25,012 (approx.)