SH3000

SH3000 SEMTECH | Alldatasheet

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Features

♦ Highly integrated IC - 3mm x 3mm x 0.9 mm 16-lead MLP (QFN) package ♦ CPU Supervisor - Low VDD reset programmable from 2.3 V to 4.3 V - Watchdog timer with programmable timeout periods - Both active-high and active-low reset outputs ♦ Clock Management System - Replaces High-Frequency (HF) crystal or resonator - Programmable clock output from 32 kHz to 16 MHz - Speed shift between multiple clock frequencies - Adjustable spectrum spreading for EMI reduction - Directly supports microcontroller STOP function - Deep sleep with instantaneous auto-wakeup ♦ Real Time Support - 179-year real time clock, battery backup capable - Dedicated 32 kHz buffered clock output - Built-in trim for 32.768 kHz oscillator to ± 4ppm - Programmable periodic interrupt / wakeup timer ♦ Auxiliary functions - 4-byte (32-bit) scratchpad RAM, loaded on reset with factory-set value (zero or optional ID code) - All settings programmable in real-time, defaults restored from OTP memory on reset ♦ Operates from 2.3 V to 5.5 V ♦ I DD <850µA / 2MHz, <3mA / 16MHz, <10µA/standby ♦ IBUP <2µA / IBSB <50nA (battery backup / standby) ♦ Protected by issued and pending US and International Patents Pin Configuration 3mm MLP (QFN) Package SH3000 µB TM 5 6 7 8 16 15 14 13 VSS VREG VDD VBAK XIN XOUT CLKSEL VSS RREF NRST TEST (VSS) RST CLK32 IO/INT CLKIN CLKOUT Typical Application Circuit with High Clock Accuracy SH3000 µB TM µController VDD XIN XOUT GPIO WITH INT NRESET GND CBYPASS Covered by US Patent No. 6,903,986 Semtech, the Semtech logo, MicroBuddy, µBuddy, and µB are marks of Semtech Corporation. All other marks belong to their respective owners.

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 2 V1.15 www.semtech.com

Description

Ordering Information

SH3000IMLTR IC MLP 3 x 3 mm 16 pins, -40° C to +85° C SH3000IMLTRT IC MLP 3 x 3 mm 16 pins, -40° C to +85° C, Lead Free EVK-SH3000USB Evaluation kit SH3000EK.pdf Evaluation kit user manual SH3000UM.pdf User manual Block Diagram CLK32 Microcontroller VDD 32KHZ XIN XOUT RESET I/O PIN CLKSEL VBAK VREG LF Oscillator Select Logic Reset Drivers & Logic VDD Monitor Watchdog HF Oscillator & FLL Real Time Clock Periodic Interrupt / Wake-up Timer XTAL Oscillator RC Oscillator Regulators & Battery Back-up OTP Memory Calibration & Default Settings Serial I/O Control Logic Clock Driver & Start/Stop Logic Post-scaler 2 3 1516 Interrupt VDD VSS XIN XOUT Voltage Reference CLKOUT CLKIN RREF RST NRST TEST IO/INT SH3000 µBuddy™ VSS

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 3 V1.15 www.semtech.com Pin Descriptions Pin Name Type Function 1 V SS Power Ground, 0 V. All V SS pins and TEST (VSS) pin must be connected together.

2 V REG Power

Output of internal Voltage Regulator, 2.2 V nominal. This pin can power external loads of <5 mA. If load is “noisy” it requires a bypass capacitor. May be left unconnected or used as a high logic level signal for CLKSEL pin (see below). 3 V DD Power Main power supply, +2.3 to +5.5 V.

4 V BAK Power

voltage can be higher or lower than VDD. Connect a backup battery or backup capacitor (with external recharge circuit). Connect to VDD if not used.

5 X IN Analog In

6 X OUT Analog Out

Oscillator pins for optional external low frequency crystal, typically 32.768 kHz watch crystal with nominal 12.5 pF load capacitance. Keep open or connect to VSS if not used.

7 CLK SEL Digital In

A logic low level selects the internal 32 kHz RC oscillator (CLKSEL tied to VSS). A high state on this pin selects the 32 kHz crystal oscillator (CLKSEL is connected to VREG). The SH3000 always starts up using the internal 32 kHz RC oscillator. If CLKSEL is high, the internal 32 kHz clock switches to the crystal oscillator once it has stabilized, and RC oscillator is disabled for power conservation. Do not connect CLKSEL to any signals except VSS or VREG. CLKSEL must not be left open. 8 V SS Power Ground, 0 V. All V SS pins and TEST (VSS) pin must be connected together. 9 R REF Analog Optional 1MOhm external bias resistor for the internal 32 kHz RC oscillator. Can be used to set, trim or modulate the internal RC oscillator. Keep open if not used.

10 NRST Digital Out

Active low system reset output. Asserted with a strong low state when a reset condition occurs. Weakly pulled to VDD internally when not active. This signal is valid for VDD as low as 1 V. Keep open if not used.

11 RST Digital Out

Active high system reset output. Asserted with a strong high state when a reset condition occurs. Weakly pulled to VSS internally when not active. This signal is valid for VDD as low as 1 V. Keep open if not used. 12 T EST (VSS) Digital In Factory test enable. All V SS pins and TEST (VSS) pin must be connected together.

13 CLK32 Digital Out

Buffered internal 32 kHz clock, derived according to the CLKSEL pin setting. This pin uses backup power for the buffer when VDD is not present. When driving high, this signal is either at VBAK or VDD (if VDD is higher than the reset threshold). When enabled, this signal runs continuously independent of CLKOUT activity. Minimize the external load to reduce power consumption during backup operations. When disabled, this pin is driven to VSS. Keep open if not used.

14 IO/I NT I/O

Serial communications interface and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to VDD when inactive. Keep open if not used.

15 CLK IN Digital In

Clock activity sense input. Used to detect when the target microcontroller enters stop mode (which disables its clock). Connect to the microcontroller’s clock output or oscillator output pin. Connect to VSS when not used. CLKIN must not be left open. 16 CLK OUT Digital Out Programmable high frequency clock output. Connect to the target microcontroller’s clock input or oscillator input pin. Keep open if not used.

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 4 V1.15 www.semtech.com Functional Description The SH3000 is a single-chip support system for microcontrollers, microprocessors, DSPs and ASICs. It consists of four major functional blocks, each block having numerous enhancements over alternative solutions. The major modules are the CPU Supervisor, the Clock Management System, the Real Time Support, and the Auxiliary functions. The entire chip is controlled by the set of internal registers and accessed via the single-pin serial interface. All of the settings, configuration, and calibration or operating parameters are programmable and re- programmable at any time. All of the parameters required for stand-alone operations are initialized on reset from the built-in factory-programmed OTP nonvolatile memory. This allows the SH3000 to operate autonomously for most of its supervisory functions. The stand-alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential benefit of the SH3000 may not be realized. In the preferred configuration, where the SH3000 is tightly coupled to the target micro, the SH3000 offers an unprecedented level of design flexibility in clock and power usage management. The SH3000 is a particularly desirable integration because the built-in features interact and meld to produce more useful system level functions. For example, on power up, the SH3000 can quickly release the reset lines on its CPU Supervisor module because the clock signal from the Clock Management System is guaranteed to be running and stabilized. An ordinary reset circuit must hold reset active for a long time to allow an unknown crystal to start up and stabilize. The SH3000 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as necessary with no external support. The clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. Users should consider the interactions of the major functional blocks to gain the maximum advantage from the SH3000. The individual functional blocks are described in the following sections.

frequency” clock synthesizer (see Figure 4). oscillator stopped for energy savings). the host processor issued a STOP instruction. approach may be as much as 100x – 10,000x slower. post-divider (see Figure 4). Figure 4. Simplified HF Oscillator System

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 8 V1.15 www.semtech.com When the HF oscillator is operating alone, it can set the frequency of the clock on the CLKOUT pin to ±0.025%, and maintain it to ±0.5% over temperature. This compares favorable with the typical ±0.5% initial clock accuracy and ±0.6% overall temperature stability of ceramic resonators. The SH3000 replaces the typical resonator, using less space and providing better performance and functionality. The HF oscillator can also be locked to the internal 32 kHz signal. The absolute accuracy and stability of the HF clock depends on the quality of the 32.768 kHz internally generated clock; the low-frequency (LF) Oscillator System is described later in this document. When the Real Time Clock module of the SH3000 is used for high-accuracy timekeeping, an external 32.768 kHz watch crystal used as a reference for RTC provides excellent accuracy and stability for the Clock Management System. The SH3000 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32 kHz reference. This architecture has several advantages over the common PLL (Phase Locked Loop) systems, including the ability to stop and re-start without frequency transients or instability, and with instant settling to a correct frequency. The conventional PLL approach invariably includes a Low-Pass Filter that requires a long settling time on re-start. The primary purpose of the FLL is the maintenance of the correct frequency while the ambient temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action from the FLL system is also small and gradual, commensurate with the temperature variation. The FLL system in the SH3000 is unconditionally stable. To set a new frequency for the FLL, the host processor writes the 13-bit Frequency Set value. The resulting output frequency is calculated using simple formulas [1] and [2] (reference frequency is 32.768 kHz): F OSC = 2048 Hz * (Frequency Set value + 1) [1] FOUT = FOSC / (Post-divider setting) [2] For example, a post-divider setting of ÷8 and the Frequency Set value of 4000 (0x0FA0) produce an output frequency of 1.024 MHz.

EMI standards is costly and complicated. figures in the 8-16 MHz range. according to the configuration setting. Table 3. EMI reduction with Spectrum Spreading

0 X X Off 0 0

Figure 5. Simplified LF Oscillator System internal 32 kHz clock for accuracy. support components provides sufficient accuracy. circuits and to the dedicated output pin, CLK32.

changes by a permanent OTP write-protect flag. frequency 4ppm for a 10°C change in temperature. minutes per month for the typical RTC chip. 179-years of calendar operations (see Figure 6). the counting-chain when the Fractions register is written. absent, if backup power is available. Figure 6. Real Time Clock and Periodic Interrupt / Wakeup timer

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 12 V1.15 www.semtech.com Periodic Interrupt / Wakeup Timer Simple and versatile, the Periodic Interrupt / Wakeup Timer can be used to create very accurate recurring interrupts for use by the host micro. With some minimum software support from the host processor, it can also be used to create alarms, with practically unlimited duration. While the timer is running, the host processor may be halted, consuming no energy. The interrupt wakes up the processor, which can perform the requisite task and go back to sleep, until the next periodic interrupt. This mode of operation can achieve extremely low average power consumption. A 32-bit counter clocked by 32.768 kHz, producing a minimum interval of 30.5 µs and the maximum interval of 36.4 hours, creates the Timer. After reset, the Timer is stopped until the new value for the time interval is written into the 4-byte Time Interval register. When the least significant byte (LSB) is written, the whole value is moved to the Time Interval latch, the counter is reset and starts to increment with the 32 kHz clock. When the 32-bit comparator detects a match, an interrupt is generated and the counter is reset and starts the next timing cycle. Although the counter cannot be written to, the current value from the counter can be read at any time. The whole 32-bit value is loaded into the 32-bit Current Timer Value latch when the least significant byte is read. This prevents errors stemming from the finite time between the readings of individual bytes of the current value. Auxiliary functions Scratchpad RAM and ID number Four (4) bytes of general-purpose RAM reside on the SH3000. Immediately after reset, they are loaded with the factory-programmed values in the OTP memory. For a standard device these values are 0x00, 0x00, 0x00, 0x00. Unique serial numbers or other information could be located there. Please contact the factory for custom requirements. Voltage Regulator Pin V REG can be used as a nominal 2.20 V reference voltage or a supply source for small loads (<2 mA). A bypass capacitor may be necessary between this pin and VSS if the load generates large current transients or a low ripple reference is required.

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 13 V1.15 www.semtech.com Interrupt and Serial Interface A single line is used to convey bi-directional information between the SH3000 and the processor, and as the interrupt line to the processor. The polarity of the interrupt signal is programmable. The SH3000 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. The bit rate is automatically determined by the SH3000. . At the fastest possible rate, a read or write access of a single byte from the register bank takes 5 µs. The SH3000 contains 36 addressable registers located at 0x00–0x1F. Some of these registers are accessed through a page operation. Pin 14, IO/Int, is the serial communications interface and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to V DD when inactive. As shown in Figure 8, the SH3000 and the host communicate with serial data streams. The host always initiates communication. A data stream consists of the following (in this order):

• 3-bit start field
• 3-bit read/write code
• 5-bit address field
• 1 guard bit
• 8-bit data field
• 2 parity bits Plus, for write streams only:
• 1 guard bit
• 2 acknowledge (ACK) bits The 3-bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. The 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. This protects against early glitches hat might otherwise put the interface into an invalid read or write access mode. The 5-bit address field contains the address of the register. A single guard bit gives the interface a safe period in which to change data direction. The value of a guard bit does not matter. The 8-bit data field is written to (read from) the register. Two parity bits: The first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit is the inverse of the first. For write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write access. Two guard bits are appended to the end of the access stream (read or write). The host can not start the next access before receiving these bits. The interface is self-timed based on the duration of the start bit field, and communication can take place whenever CLKout is active, either at 32 kHz or at a higher frequency. If the host microcontroller is running synchronously to the CLKout generated by the SH3000 (which should generally be the case), then a minimum of

4 CLKout cycles per bit are required to maintain

communication integrity. If the host’s serial interface is asynchronous to CLKout, then a minimum of 52 cycles per bit are necessary. A maximum of 1024 CLKout cycles per bit field is supported. Table 4 displays the minimum and maximum bit periods for the serial communications for CLKout frequencies of 16 MHz, 8 MHz, and 2 MHz. Table 4: Minimum/Maximum Serial Bit Timing CLKOUT Frequency Minimum Bit Period (host synchronous to CLKOUT) Minimum Bit Period (host asynchronous to CLKOUT) Maximum Bit Period 16 MHz 250 ns 3.25 µs 64 µs 8 MHz 500 ns 6.5 µs 128 µs

2 MHz 2 µs 26 µs 512 µs

The serial communications line to the SH3000 (Pin 14, IO/Int) also serves as the interrupt to the host microcontroller. The polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the IPol_RCtune register (R0x11). This pin is asserted for four cycles of CLKout, and then returns to the inactive state. The interrupt line is used by the Periodic Interrupt/Wake-up Timer to interrupt the host when it reaches its end of count.

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 14 V1.15 www.semtech.com IO/INT timing scenarios 1. INT disabled, uP initiates write access. Active high interrupt. uBuddyIOOut uPIOOut A0 A4 XXX D0 D7... 2. INT active (high), uP initiates write access uBuddyIOOut uPIOOut CombinedIO XXX State Idle Pre- start Start Post- XXX State If the interrupt did not get cleared, then it will activate again here 4. INT disabled, uP initiates read access uBuddyIOOut uPIOOut A0 A4 XXX... State Idle Pre- start Start Post- D0 D7... P0 P1 P0 P1 P0 P1 P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 A0 A4 XXX D0 D7... XXX Pre- start Start Post- XXX P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 ACK0 ACK1 Guard2 Guard3 Guard2 Guard3Pendin g-start IN TIdle Pendin g-start IN T 3. INT active (low), uP initiates write access uBuddyIOOut uPIOOut CombinedIO State If the interrupt did not get cleared, then it will activate again here A0 A4 XXX D0 D7... XXX Pre- start Start Post- XXX P0 P1 P0 P1 P0 P1 ACK0 ACK1 ACK0 ACK1RW0 RW1 RW2 Guard2 Guard3Pendin g-start IN TIdle Pendin g-start IN T ACK0 ACK1 RW0 RW1 RW2 Guard3 Figure 7: Serial Communication Timing Diagram

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 15 V1.15 www.semtech.com Note: The SH3000 is ESD-sensitive. Description Symbol Min Max Units Supply voltages on VDD or VBATT relative to ground V DD -0.5 5.5 V Input voltage on CLKIN, IO/INT, TEST V IN1 -0.5 V DD + 0.5 V Input voltage on CLKSEL V IN2 -0.5 V REG + 0.5 V Input current on any pin except VREG I IN1 10 mA Input current on VREG I IN2 150 mA Ambient operating temperature T OP -40 85 ºC Storage temperature T STG -50 160 ºC IR Reflow temperature, (soldering for 10 seconds, TR Option) TIRRT 240 ºC IR Reflow temperature, (soldering for 10 seconds, TRT Option) TIRRT 260 ºC Operating Characteristics Parameter Symbol Min Max Units Notes Case temperature T OP –40 +85 °C Supply voltage V DD 2.3 5.5 V Supply current, CLKOUT = 16 MHz* I DD 3 mA Supply current, CLKOUT = 8 MHz* I DD 2 mA Supply current, CLKOUT = 2 MHz* I DD 1 mA Standby current, 32 kHz crystal I SB 8 µA CLK32 disabled Standby current, 32 kHz RC oscillator I SB 10 µA CLK32 disabled Backup Supply Voltage V BAK 2.3 5.5 V Backup current, 32 kHz crystal I BUP 2 µA CLK32 disabled Backup current, 32 kHz RC oscillator I BUP 8 µA CLK32 disabled Backup standby current I BSB 50 nA V DD > VBO *Note: Assuming load on CLKOUT < 20 pf **Note: Assuming temperature < 60ºC Electrical Specifications Absolute Maximum Ratings

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 16 V1.15 www.semtech.com Operating characteristics with crystal oscillator Parameter Symbol Min Typ Max Units Crystal operating frequency Fop 32.768 kHz CLK32 duty cycle DC 25 75 % Startup time Tst 3 secs Minimum XIN/XOUT padding capacitance Cmin 9 10 11 pF Maximum XIN/XOUT padding capacitance Cmax 36 40 44 pF Padding capacitance resolution Cres 1.8 2 2.2 pF XIN switching threshold Vth 0.6 V XIN to CLK32 delay Td 1 µ s CLK32 frequency stability (crystal-dependent) Fs 1 ppm/°C CLK32 cycle to cycle jitter J 0.1 CLK32 rise/fall time (10 pF load) Trf 20 ns CLK32 logic output low (0.5 mA load) Vol 0.25 0.5 V CLK32 logic output high (0.5 mA load) Voh -0.5 -0.25 Ref V DD* *Note: VDD here is VDD during normal operation and VBAK during battery backup. Operating characteristics of 32 kHz RC oscillator Parameter Symbol Min Typ Max Units External 1 MOhm referenced nominal frequency Fext 32.768 kHz Internal 1 MOhm referenced nominal frequency Fint 32.768 kHz CLK32 duty cycle DC 40 60 % Programmed frequency accuracy at 25°C Fst -1 +1 % Absolute accuracy over temperature and supply (external 1 MOhm) Fde -2 +2 % Absolute accuracy over temperature and supply (internal 1 MOhm) Fdi -3 +3 % Frequency temperature stability (ext. 1 MOhm) Fse 100 ppm/°C Frequency temperature stability (int. 1 MOhm) Fsi 200 ppm/°C Power on startup time Tst 100 µs CLK32 cycle to cycle jitter J 0.2 %

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 17 V1.15 www.semtech.com Operating characteristics of programmable reset Parameter Symbol Min Typ Max Units VDD switching threshold (Start-up default = 2.3 V) Vbo 2.27 2.3 4.4 V VDD threshold resolution Vres 25 33 41 mV VDD hysteresis Vhys 25 100 mV Falling VDD threshold switch delay Td 1 5 us Threshold digital-analog converter (DAC) settling time Tdac 5 ms Minimum VDD for valid nRST and RST VDDmin 1 V Operating characteristics of the high-frequency oscillator (HFO) Parameter Symbol Min Typ Max Units Minimum operating frequency (Start-up default = 2 MHz) Fmin 5.6 8 MHz Maximum operating frequency Fmax 16.8 21 MHz Frequency resolution Fres 2 kHz Programmed frequency accuracy at 25°C Fst -0.2 +0.2 % Frequency drift over temperature and supply Fdrift -0.5 +0.5 % CLKOUT cycle to cycle jitter (spread spectrum off) J 0.2 % Startup time from standby Tstart 2 µs Settling time to 0.1% after HF digitally-controlled oscillator (DCO) code change Tsett 10 µs CLKOUT duty cycle DC 40 60 % Frequency temperature stability Fts 100 ppm/°C Short term frequency stability Fs 0.1 %/sec Minimum spread spectrum range SSmin 26 32 38 kHz Maximum spread spectrum range SSmax 204 256 306 kHz CLKOUT rise/fall time (20 pF load) Trf 5 ns CLKOUT logic output low (4 mA load) Vol 0.25 0.4 V CLKOUT logic output high (4 mA load) Voh -0.4 -0.25 Ref V DD

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 18 V1.15 www.semtech.com Free Running HF DCO Frequency Deviation over Temperature for All Frequencies -16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 2000 4000 -60 -40 -20 0 20 40 60 80 100 120 140 Temp. ºC ppm Deviation Internal 32 kHz Oscillator Frequency over Temperature 31800 32000 32200 32400 32600 32800 33000 33200 33400 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (ºC) Frequency (Hz)

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 19 V1.15 www.semtech.com 32.768 kHz Crystal Oscillator Frequency Deviation over Temperature -200 -150 -100 -50 -60 -40 -20 0 20 40 60 80 100 120 Temperature (ºC) ppm Deviation Battery Backup Current over Temperature (VBATT = 3 V) -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (ºC) VBATT Current (µA) Internal 32 kHz Crystal 32 kHz

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 20 V1.15 www.semtech.com Standby Current over Temperature (VDD = 5 V) 0.0 5.0 10.0 15.0 20.0 25.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (ºC) VDD Current (µA) Crystal 32 kHz Internal 32 kHz Standby current over VDD (Temp. = 25ºC) 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD Current (µA) Crystal 32 kHz Internal 32 kHz

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 21 V1.15 www.semtech.com VDD Current vs CLKOUT Frequency (VDD = 5.5 V, Temp. = 25ºC) 500 1000 1500 2000 2500 3000 3500 02468 1 0 1 2 1 4 1 6 1 8 Frequency (MHz) VDD Current (µA) Operating VDD Current over VDD (CLKOUT = 16 MHz, Temp = 25ºC) 2000 2200 2400 2600 2800 3000 3200 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD Current (µA)

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 22 V1.15 www.semtech.com Free Running HF DCO Short Term Frequency Stability (CLKOUT = 8 MHz) -400 -300 -200 -100 100 200 300 -500 500 1500 2500 3500 4500 5500 6500 Time (seconds) ppm Deviation FLL Locked HF DCO Jitter over Jitter Bandwidth (CLKOUT = 12.8 MHz) 100 1000 10000 100000 0.1 1 10 100 1000 10000 100000 Jitter Bandwidth (kHz) rms Jitter (ps)

SH3000 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2003-2005 Semtech Corporation 23 V1.15 www.semtech.com Package Outline Drawing MLP 3 x 3 mm 16 pins

©2005 Semtech Corporation www.semtech.com24 Contact Information Semtech Corporation

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