SFW9540 FAIRCHILD | Alldatasheet

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BVDSS = -100 V RDS(on) = 0.2 ID = -17 A -100 -17 -12 -68 ±30 578 -17 13.2 -6.5 3.8 132 0.88 - 55 to +175 300 1.14 62.5 Ωn Avalanche Rugged Technology n Rugged Gate Oxide Technology n Lower Input Capacitance n Improved Gate Charge n Extended Safe Operating Area n 175 o C Operating Temperature n Lower Leakage Current : 10 µA( M a x . ) @ VDS = -100V n Low RDS(ON) : 0.161 Ω (Typ.) Advanced Power MOSFET Thermal Resistance Junction-to-Case Junction-to-Ambient Junction-to-Ambient RθJC RθJA RθJA o C/W Characteristic Max. UnitsSymbol Typ.

FEATURES

  1. Gate 2. Drain 3. Source I2-PAK * When mounted on the minimum pad size recommended (PCB Mount). Absolute Maximum Ratings Drain-to-Source Voltage Continuous Drain Current (TC=25 o Continuous Drain Current (TC=100 o Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (T A=25 o Total Power Dissipation (TC=25 o Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, from case for 5-seconds Characteristic Value UnitsSymbol IDM VGS EAS IAR EAR dv/dt PD ID TJ , TSTG TL A V mJ A mJ V/ns W W o C A o C VDSS V 1/8” Rev. C

-100 -2.0 -0.11 240 7.4 17.8 -4.0 -100 100 -10 -100 0.2 1535 360 125 100 9.5 1180 135 0.7 -17 -68 -4.0 Notes ; Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature L=3.0mH, IAS=-17A, VDD=-25V, RG=27Ω *, Starting TJ =25oC ISD -17A, di/dt 450A/ µs, VDD BVDSS , Starting TJ =25oC Pulse Test : Pulse Width = 250µs, Duty Cycle 2% Essentially Independent of Operating Temperature P-CHANNEL POWER MOSFET Electrical Characteristics (TC=25oC unless otherwise specified) Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse CharacteristicSymbol Max. UnitsTyp.Min. Test Condition Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain( “Miller” ) Charge g fs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd BVDSS ∆BV/∆TJ VGS(th) RDS(on) IGSS IDSS V o C V nA µA Ω pF ns nC V GS=0V,ID=-250µA ID=-250µA See Fig 7 VDS=-5V,ID=-250µA VGS=-20V VGS=20V VDS=-100V VDS=-80V,TC=150 o C VGS=-10V,ID=-8.5A VDS=-40V,ID=-8.5A VDD=-50V,ID=-17A, RG=12 See Fig 13 VDS=-80V,VGS=-10V, ID=-17A See Fig 6 & Fig 12 Drain-to-Source Leakage Current VGS=0V,VDS=-25V,f =1MHz See Fig 5 Source-Drain Diode Ratings and Characteristics Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge I S ISM VSD trr Qrr CharacteristicSymbol Max. Units Typ.Min. Test Condition A V ns µC Integral reverse pn-diode in the MOSFET T J=25 o C,IS=-17A,VGS=0V TJ=25 o C,IF=-17A diF/dt=100A/µs Ω S

@ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC VGS Top : - 1 5 V - 1 0 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom : - 4.5 V -ID , Drain Current [A] -VDS , Drain-Source Voltage [V] 24681 010-1 100 101 25 oC 175 oC - 55 oC @ Notes : 1. VGS = 0 V 2. VDS = -40 V 3. 250 µs Pulse Test -ID , Drain Current [A] -VGS , Gate-Source Voltage [V] 0 8 16 24 32 40 48 56 640.0 0.1 0.2 0.3 0.4 0.5 0.6 @ Note : TJ = 25 oCVGS = -20 V VGS = -10 V RDS(on) , [Ω ] Drain-Source On-Resistance -ID , Drain Current [A] 100 101 175 oC 25 oC @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test -IDR , Reverse Drain Current [A] -VSD , Source-Drain Voltage [V] 100 1010 500 1000 1500 2000 Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd Crss= Cgd @ Notes : 1. VGS = 0 V 2. f = 1 MHz C rss C oss C iss Capacitance [pF] -VDS , Drain-Source Voltage [V] 01 02 03 04 05 00 VDS = -80 V VDS = -50 V VDS = -20 V @ Notes : ID =-17 A -VGS , Gate-Source Voltage [V] QG , Total Gate Charge [nC] P-CHANNEL POWER MOSFET Fig 1. Output Characteristics Fig 2. Transfer Characteristics Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current

-75 -50 -25 0 25 50 75 100 125 150 175 2000.0 0.5 1.0 1.5 2.0 2.5 @ Notes : 1. VGS = -10 V 2. ID = -8.5 A RDS(on) , (Normalized) Drain-Source On-Resistance TJ , Junction Temperature [oC] 100 101 10210-1 100 101 102 10 ms DC 1 ms 0.1 ms @ Notes : 1. TC = 25 oC 2. TJ = 175 oC 3. Single Pulse Operation in This Area is Limited by R DS(on) -ID , Drain Current [A] -VDS , Drain-Source Voltage [V] -75 -50 -25 0 25 50 75 100 125 150 175 2000.8 0.9 1.0 1.1 1.2 @ Notes : 1. VGS = 0 V 2. ID = -250 µA -BVDSS , (Normalized) Drain-Source Breakdown Voltage TJ , Junction Temperature [oC] 25 50 75 100 125 150 1750 20-ID , Drain Current [A] Tc , Case Temperature [oC] 10-5 10-4 10-3 10-2 10-1 100 10110-2 10-1 100 single pulse 0.2 0.1 0.01 0.02 0.05 D=0.5 @ Notes : 1. Zθ JC(t)=1.14 oC/W Max. 2. Duty Factor, D=t1/t2 3. TJM-TC=PDM*Zθ JC(t) Z θJC(t) , Thermal Response t1 , Square Wave Pulse Duration [sec] P-CHANNEL POWER MOSFET Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature Fig 11. Thermal Response PDM. t1. t2.

Fig 12. Gate Charge Test Circuit & Waveform Fig 13. Resistive Switching Test Circuit & Waveforms Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms EAS =L L IAS 2----2 BVDSS -- VDD BVDSS Vin Vout 10% 90% td(on) tr t on t off td(off) tf Charge VGS -10V Qg Qgs Qgd Vary tp to obtain required peak ID -10V VDDC LL VDS ID RG t p DUT BVDSS t p VDD IAS VDS (t) ID (t) Time VDD ( 0.5 rated VDS ) -10V Vout Vin RL DUT RG -3mA VGS Current Sampling (IG) Resistor Current Sampling (ID) Resistor DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT “ Current Regulator ” R1 R2 SFW/I9540

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT VDS L I S DriverVGS RG Compliment of DUT (N-Channel) VGS • dv/dt controlled by “RG”

  • IS controlled by Duty Factor “D” VDD 10V VGS ( Driver ) I S ( DUT ) VDS ( DUT ) VDDBody Diode Forward Voltage Drop Vf IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width