ISL40 YAMAR | Alldatasheet
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Proprietary and Confidential Information of YAMAR Electronics Ltd. © 2007 Yamar Electronics Ltd. 1 DS-ISL40 R1.6
1 GENERAL
The ISL40 is an innovative VLSI solution for low co st network of I/O peripheral devices communicating over a noisy single wire or a battery power line us ing the LIN protocol. It provides the means for an economical network of multiple slave devices for ap plications as controlling motors, reading sensors etc., eliminating the need for a dedicate controller for slave modules. The device operates as an independent LIN slave in a network controlled by a SIG40 master device, which transmits five types of messages to each one of its slaves; Read, Read Change, Write, Sleep and Change Frequency. The ISL40 slave device identifies a LIN message add ressed to its predefined ID. When a Write message is received, the data part of the message i s directed to the corresponding 4 or 8 output pins. When a Read or Read Change message is detected, the slave responds with a LIN2.0 message that contains information on all its 8 inputs or 4 input pins and 4 output pins. A Sleep command enables power saving. Wakeup messages awaken remote devices. The device is based on an original multiplex signal ing technology. The ISL40 has a LIN message handler, a unique signaling modem and coder/decoder that overcome the hostile communication environment over vehicle battery lines. The ISL40 capability of communicating over battery- powered line is useful for a wide range of vehicula r and industrial applications, such as doors, seats, mirrors, climate control, lights etc. Figure 1.1 - Typical ISL40 Applications
2 OVERVIEW
2.1 Signaling System
The ISL40 device operates as an independent slave i n a network controlled by a SIG40 master device that can transmit asynchronous LIN messages to any one of its 15 slave devices. An ISL40 slave device which identifies a Write message addressed to its I D, takes the data part of the message and outputs i t to its output pins, while a master Read message is responded by the slave with a message consisting of its sampled input pins. The device receives and tra nsmits special narrow band signaling carrier, which can be differentiated from noise. The receiver rece ives the signaling patterns, extracting them into t he original bits. The rest of the spectrum is reserved for additional communication channels over the sam e DC noisy lines. YAMAR Ele c tro nics L td Preliminary Data Sheet This information is preliminary and may be changed without not ice ISL40 - Independent DC -LIN Slave For Asynchronous Communication Over Noisy Lines SIG 40 ECU DC Line Id 8/4 Inputs ISL40 4/8 Outputs Slave Id 8/4 Inputs ISL40 4/8 Outputs Slave Master
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2.2 Channels and Network
The ISL40 operates over one of two preset selectabl e channels (frequencies) using a single line such as the vehicle’s battery power line. A SIG40 master and up to 15 ISL40 slave devices can be connected to each of the channels over the same line. Each of them can receive a message that controls either 4 output pins and returns a message consisting of its 8 input pins status or control 8 output pins and return status of its 4 input pins according to the device setup. By selecting other channels, more tha n one network may be used over same line for different applications. Channel frequencies: 3.58MHz to 6.5MHz. Data transfer rate: up to 57.6Kbps. Cable length: Depends on external loads connected to the DC line.
2.3 The ISL40 Device
Figure 2.1 outlines the building blocks of the ISL40 device. M e s s a g e H a n d le r S ig n a lin g G e n e r a to r a n d D e te c to r IS L 4 0 T x /R x O u t p u t In p u t M o d e m C e r a m ic F ilte r T im in g 3 2 .7 6 8 K X ta l O s c illa to r L IN M e s s a g e H a n d le r C e r a m ic F ilte r S le e p C o n tr o l ID Figure 2.1 - ISL40 Logical Blocks
2.4 Power Management
Sleep Mode, controlled by the host, saves power by disabling most of the circuits. During Sleep Mode, the device is switched on for a short period to detect Signaling activity on the bu s. If no activity is detected, the device is switched off.
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3 OPERATION
The following paragraph describes the operation of the ISL40 device.
3.1 Protocol
The device responds to five types of LIN messages: Write, Read, Read Change, Sleep and Change Frequency. When receiving a Write message with the correct ID, the device outputs to its Output pins the data indicated by the message. When receiving a Read massage with the correct ID, the device responds to the LIN message with the content of it’s Input pins followed by the appropriate checksum according to LIN 2.0 protocol. When receiving a Read Change massage with the corre ct ID, the device responds to the LIN message with the first detected change on its input pins fo llowed by the appropriate checksum according to LIN 2.0 protocol. When receiving a Sleep message the device enters into low power-consumption sleep mode. A wakeup message generated by the master or by any of the slaves, wakes up all the devices on the network. When receiving Change-Frequency message, the device switch between its two selected frequencies.
3.1.1 Message Construction
The construction of the five types of messages is as follows: Write message: The Write message consists of five bytes - sync break, sync field, Identifier, data and checksum. The identifier byte begins with the device four ID bits, followed by 00 bits and 2 protection bits. If checksum calculation is successful, the data byt e content is transferred to the corresponding outpu t pins. If the device is set to 4 outputs, the four l ow significant bits (sent first) are transferred to the four output SigOx pins. Otherwise, all 8 bits are transf erred. The checksum is calculated according to LIN2.0 specifications. Figure 3.1 shows a generic write message. Figure 3.1 Write message Read message: The read message gets the status of the ISL40 input pins. The Read command can either get 4 input pins and 4 MSB’s of the output pins or 8 input pins status according to the device setup pins. The Read comman d can request the current state of the input pins or detect any change caused on the pins since the last read command. If the ISL40 configured to have only 4 input pins, the 4 most significant bits of the data byte would be a read back of the 4 MSB’s output pins. Sync break Sync Field [P1, P0, 0, 1, Address] Out [7:0] Checksum ISL40 Outputs at receiving device 3 bit delay Transmitted message
Proprietary and Confidential Information of YAMAR Electronics Ltd. © 2007 Yamar Electronics Ltd. 5 DS-ISL40 R1.6 Figure 3.5 Sleep message Change Frequency message: This type of message consists of 5 bytes - sync break, sync field, “FE” Hex, “00” Hex and checksum. The change frequency message identifier is “FE” Hex and the following data byte “00”Hex. Upon reception of sync break, sync field, “FE” Hex and “00” Hex bytes the frequency changes from F1 to F0 or vise versa. Figure 3.6 Frequency Change message
3.2 Power Management
The device features Sleep mode for power saving. En tering Sleep and waking up are done either locally by dedicated pins, or remotely through activity over the bus.
3.2.1 Entering Sleep mode
The ISL40 can enter sleep mode in the following ways: 1. Local device lowers its nSleep pin. 2. Remote master SIG40 device can enter the ISL40 d evice into Sleep Mode from Normal mode by transmitting the remote sleep message. 3. The AutoSleep pin is high and no reception occur red for about 8 seconds.
3.2.2 Remote wake up process
The ISL40 can wakeup by a remote SIG40 master or IS L40 device transmits a wakeup message over the bus. During Sleep Mode, the ISL40 wakes up peri odically to sense the bus for activity every 32mSec. If a wakeup message is detected, the ISL40 device raises pin INH and lowers pin HDO. If nSleep pin is low upon remote waking up, the local device that lowered it must raise the nSleep back high. Figure 3.6 shows the signals description. Figure 3.7 - Wakeup from bus message
3.2.3 Wakeup from pin Wake
A transition on pin Wake (caused by an external swi tch of the application) is used to wake the device. The device then enters Standby mode, raises pin INH , and transmits a wakeup message to the bus. While transmitting the wakeup message to the bus, t he device lowers pin HDO. After the transmission is complete the device raises pin HDO. After the tr ansmission is completed the device enters Normal Sync break Sync Field 0x3C Zero byte/bytes Checksum INH msg. detected DC -BUS Wakeup Message Normal mode HDO Standby Sync break Sync Field 0xFE Zero byte/bytes Checksum
Proprietary and Confidential Information of YAMAR Electronics Ltd. © 2007 Yamar Electronics Ltd. 6 DS-ISL40 R1.6 mode. If nSleep pin is low upon waking up, the loca l device that lowered it must raise the nSleep back high. Figure 3.8 - Wakeup from Wake
3.3 ISL40 Configuration
Pins Mode 4 and Mode 3 should be connected to Vcc. The ISL40 operates at default with the following parameters: Bit rate: 19.2 Kbps F0=5.5MHz The following configuration pins enable changing of the default values. F0F1-3-0 [4] F0 F1 1111 3.58Mhz 4.5Mhz 1110 3.58Mhz 5.5Mhz 1101 3.58Mhz 6Mhz 1100 3.58Mhz 6.5Mhz 1011 4.5Mhz 5.5Mhz 1010 4.5Mhz 6Mhz 1001 4.5Mhz 6.5Mhz 1000 4.5Mhz Reserved 0111 10.7Mhz Reserved 0110 5.5Mhz Reserved 0101 5.5Mhz Reserved 0100 6Mhz Reserved 0011 6Mhz Reserved 0010 6.5Mhz Reserved 0001 6.5Mhz Reserved 0000(default) 5.5Mhz 6.5Mhz BitRate1-0 [2] 10 = 57.6Kbps 01 = Reserved 11 = 38.4Kbps 00 = 19.2Kbps Signal High (“1”) Low (“0”) AutoSleep Auto Sleep On Auto Sleep Off nExtendIn SIG[7:4] are outputs SIG[7:4] are inputs ID[3:0] Defines device ID InterHop InterHop On InterHop Off INH Wake Normal mode DC -BUS Wakeup Message Standby HDO T2 T1 = 30uS-62uS T2 = 92uS -124uS
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4 ISL40 SIGNALS
Device signals are defined in table 4.1. Table 4.1 - Device signals Control signals Configuration signals HDO CMOS O 20 F0F1-0 CMOS+PD I 42 nSleep CMOS I 28 F0F1-1 CMOS+PD I 43 INH CMOS I 24 F0F1-2 CMOS+PD I 34 Wake CMOS I 33 F0F1-3 CMOS+PD I 35 nReset CMOS_Reset+PU I 32 BitRate0 CMOS+PD I 45 InterfHop CMOS + PD I 36 BitRate1 CMOS+PD I 46 Interfer CMOS O 21 Mode3 =1 CMOS+PD I 4 Front-end signals Mode4 =1 CMOS+PD I 7 RxOn CMOS O 16 nExtendIn CMOS+PD I 40 DRxP CMOS I 6 AutoFreqCh CMOS+PD I 26 AutoSleep CMOS+PD I 27 DRxN CMOS I 5 Power signals MF0nF1 CMOS O 41 Vcc Power P 48 TxOn CMOS O 14 Vcc Power P 3 DTxO Buf+Slew+3 State B 13 Gnd Power P 12 OscIn CMOS I 1 Gnd Power P 19 OscOut CMOS O 2 VccPLL Power P 37 GndPLL Power P 47 Sig I/O signals SigIn0 CMOS+PD I 38 SigIn1 CMOS+PD I 39 SigIn2 CMOS I 25 SigIn3 CMOS I 29 SigIO4 BiDirectional+PD B 23 SigIO5 BiDirectional+PD B 15 SigIO6 BiDirectional+PD B 17 SigIO7 BiDirectional+PD B 18 SigO0 CMOS O 8 SigO1 CMOS O 9 SigO2 CMOS O 10 SigO3 CMOS O 11 ID0 CMOS+PD I 30 ID1 CMOS+PD I 31 ID2 CMOS+PD I 44 ID3 CMOS+PD I 22 Interf 21 INH 24 SigIO6 17 DTxO 13 SigIO5 15 HDO 20 SigIO7 18 Gnd 19 RxOn 16 SigIn2 25 TxOn 14 Gnd 12 AutoSleep 27 SigO0 8 OscIn 2 SigO3 11 Id1 31 SigIO4 23 VccPLL 37 SigIn1 39 MF0nF1 41 F0F1-1 43 BitRate1 46 Vcc 48 OscOut 1 Id2 44 Interf Hop 36 SigIn0 38 nExtndIn 40 F0F1-0 42 DRxP 6 nReset 32 SigIn3 29 nSleep 28 Id3 22 AutoFreqChange 26 F0F1-3 35 Wake 33 Mode4 7 SigO2 10 SigO1 9 Id0 30 F0F1-2 34 Mode3 4 Vcc 3 DRxN 5 GndPLL 47 BitRate0 45 ISL40 PD = internal pull down resistor Figure 4.1 - ISL40 Pinout
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4.1 Application interface
4.1.1 HDO
The HDO pin outputs the data that is being received from the DC-BUS. It can be used to monitor the incoming data.
4.1.2 SigIn[0:3]
Four input signals to the ISL40. On a Read or Read Change command the pins status is being send back to the Master in the lower nibble of the returned data byte.
4.1.3 SigO[0:3]
Four output signals from ISL40. The pins state is c hanged when the Master issues a Write command. The pins status is defined in the lower nibble of the Write command’s OUT byte.
4.1.4 SigIO[4:7]
Four input or output signals of the ISL40, dependin g on the nExtendIn pin. When configured as inputs their status is being send back to the Master in th e upper nibble of the return data byte. When they a re configured as outputs their state is defined in the upper nibble of the Write command’s OUT byte. 4.1.5 nExtendIn Determines if the SigIO[4:7] pins are inputs or outputs. 1= outputs, 0 = inputs.
4.1.6 ID[1:4]
Four ID address input pins. Using the ID address ea ch ISL40 on the network or a specified group of ISL40 can receive individual commands.
4.2 Sleep control
4.2.1 AutoSleep
When AutoSleep pin is set to High the device will a utomatically enters sleep mode after about 8 seconds without reception. 4.2.2 nSleep Sleep control input from external signal. Should be connected to High (Vcc).
4.2.3 Wake
Local wakeup input. Negative or positive edge trigg ered. This pin can be connected to an external switch in the application. When the pin is triggere d the device will wake up and send a wake up message to all the devices on the network.
4.2.4 INH
Inhibit output for enabling the host (or an externa l voltage regulator powering the host. This output is LOW when in Sleep Mode, and HIGH in normal operation and after a wakeup event.
4.3 Frequency control
4.3.1 AutoFreqCh
When high, the device automatically switches frequency after about 4 seconds without bus activity.
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4.3.2 InterfHop
When high, a detection of interference, switches th e operating frequency. If at the new frequency, no reception occurred for 2 sec, the operating frequency is switched back. For designs with a single channel this pin should be tied to ground.
4.3.3 Interfer
Output signal is raised while interference is detected on the DC-BUS.
4.3.4 MF0nF1
Indicates the operating frequency, this is the conf igured frequency unless automatic frequency change has been enabled and caused.
4.4 Line Interface
4.4.1 DTxO
Modulated transmit signal output.
4.4.2 TxOn
High when the device is transmitting a message.
4.4.3 RxP
Input to the internal comparator positive pin. It swings around RxN.
4.4.4 RxN
Input to the internal comparator negative pin. Its value should be about Vcc/2.
4.4.5 RxOn
High when the device is in receive mode.
4.4.6 Power Signals
There are three sets of power signals, (Vcc, Gnd)*2 and VccPLL, GndPLL. See 4.7 for details. VCC VccPLL VCC VCC VCC VCC VCC VCC VCC Analog Interface Protection Network Vcc = 3.3V I/O lines Configuration lines (connect to Gnd or Vcc) DC-Powerline TxOn RxOn R23 3.3K R11 R10 6.8 2.2 D1BAS31 0.1u 2.2nF/200V 10M R24 39K 32.768KHz 22 /0.25W 12p 47p 0.1 R9 6.8 1n C10 R13 2.2 C12 R19 470 12p PZT2222 R15 4.3K R12 R18 R17 3.9K R34 330 330K C101 0.1u FSA3157 3 6 2 5 R101 100K 100 C57 0.1u C150 >47uF ISL40 BitRate0 45 GndPLL 47 DRxN 5 Vcc 3Mode3 4 F0F1-2 34 Id0 30 SigO1 9SigO2 10 Mode4 7 Wake 33 F0F1-3 35 AutoFreqChange 26 Id3 22 nSleep 28 SigIn3 29 nReset 32 DRxP 6 F0F1-0 42 nExtndIn 40 SigIn0 38 Interf Hop 36 Id2 44 OscOut 1 Vcc 48 BitRate1 46 F0F1-1 43 MF0nF1 41 SigIn1 39 VccPLL 37 SigIO4 23 Id1 31 SigO3 11 OscIn 2 SigO0 8 AutoSleep 27 Gnd 12 TxOn 14 SigIn2 25 RxOn 16 Gnd 19 SigIO7 18 HDO 20 SigIO5 15 DTxO 13 SigIO6 17 INH 24 Interf 21 R14 Ceramic Filter In GND Out Figure 4.2 – Typical single channel line interface circuit Note: The FSA3157 can be replaced with an analog switch.
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4.5 Ceramic Filter
The ISL40 is designed to operate with one ceramic f ilter for transmission and reception. However, if switching between two channels is desired, two cera mic filters are required. The minimum allowable bandwidth of the ceramic filters is +/-70 kHz @ 3dB. Narrower bandwidth limits the maximal bit rate. The ISL40 selectable frequencies are designed according to the market available ceramic filters. Nominal freq. 3 db BW 20db BW Insertion loss Stop band attenuation In/Out imped. Murata part # Oscilent part # MHz KHz min. KHz max. dB max. dB min. Ohm *3.58 +/-40 530 6.0 25 530 SFSH3.58MCB 4.5 +/-70 750 6.0 30 1000 SFSL4.5MDB 773-0045 5.5 +/-80 750 6.0 30 600 SFSL5.5MDB 773-0055 6.0 +/-80 750 6.0 30 470 SFSL6.0MDB 773-0060 6.5 +/-80 800 6.0 30 470 SFSL6.5MDB 773-0065
- The 3.58MHz frequency can be operated with 9.6Kbps and 19.2Kbps only
4.6 Oscillator
The ISL40 is designed to operate with a low cost 32 .768KHz crystal connected between OscIn and OscOut pins. This type of crystal has the advantag e of very low power consumption and low cost. However there are also drawbacks. It is very sensit ive to noise and has a temperature dependency that should be carefully considered when selecting the crystal. The following guidelines should be used when designing the PCB: 1. Design the trace length as short as possible. 2. Avoid thin line on resonator traces (< 0.010"), keep them as wide as possible. 3. To avoid noise, protect these signals with Groun d shields. The exact values of C1, C2, R1 and R2 should be determined according to the crystal manufacturer. 4.7 Recommended 32.768KHz Crystal Specifications Type Value Nominal Frequency: 32.768KHz Frequency tolerance @25ºC +/-20 ppm Load capacitance 12.5 pF Serial resistance 50K Ohm (max.) Drive level 1uW (max.) Quality factor 50,000 (max.) Turnover temperature +25ºC +/- 5ºC Parabolic constant -0.04 ppm/ºC² (max.) Aging +/-3 ppm in first year (max.) Operating temperature -40ºC to + 85ºC Storage temperature -55ºC to + 125ºC The overall frequency tolerance should not exceed 200ppm.
4.8 Communication performance
The maximal cable length between extreme devices de pends mainly on the AC impedance of loads connected to that line and number of nodes. The DC cable length has less effect on communication. The SIG40 needs at least 20mVpp for proper receptio n. Good communication should be achieved if an oscilloscope at the SIG40 receiver can see the transmitted signal within the noise.
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4.9 PLL Power Pins
VccPLL should be connected to Vcc. GndPLL should be connected to ground. The PLL supply has to be sufficiently powered, to avoid any fluctuations of power supply. A capacitor of at least 47uF shoul d be connected as close as possible to these pins. It is recommended to keep the lines between 3.3V power supply and the Vcc pins as short as possible with wide PCB traces for Vcc, VccPLL, Gnd and GndPLL.
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5 ELECTRICAL PARAMETERS
5.1 Absolute Maximal Rating
Ambient Temperature under bias -40 °C to 125 °C Storage Temperature -65 °C to 150 °C Voltage on any pin with respect to Vss (except Vdd and ~Reset) -0.6V to Vdd+0.6V Voltage on Vdd with respect to Vss 0 to +7.5V Voltage on ~Reset pin with respect to Vss 0 to +1 4V Total power Dissipation 1.0W Maximum current out of Vss pin 300mA Maximum current into Vdd pin 250mA Maximum Output Current sunk by any I/O pin 25mA Maximum Current source by any I/O pin 25mA
5.2 DC Characteristics
Characteristics Min Typ Max Units Conditions Vdd Supply Voltage 3.0 3.3 3.6 V Idd Supply Current 35 mA Ipd Power Down Current 70 uA
5.3 Operating Temperature
Commercial: 0 °C to 70 °C Industrial: -40 °C to 85 °C