SFC3.3-4 SEMTECH | Alldatasheet
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1 www.semtech.com PROTECTION PRODUCTS SFC3.3-4 Low Voltage ChipClampΤΜΤΜΤΜΤΜΤΜ Flip Chip TVS Diode Array Description Features Device Dimensions Schematic & PIN Configuration Revision 11/13/2008 The SFC3.3-4 is a quad flip chip TVS diode array. They are state-of-the-art devices that utilize solid-state EPD TVS technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconduc- tor components from damage or latch-up due to electrostatic discharge (ESD) and other voltage in- duced transient events. The SFC3.3-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures approximately 1.5 by 1.0 mm. It has a very low profile of < 0.65 mm. This is a crucial specification for many portable applica- tions. Each device will protect up to four data or I/O lines. The flip chip design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. The devices are constructed using Semtech’s propri- etary EPD process technology. The EPD process pro- vides low standoff voltages with significant reductions in leakage currents and capacitance over silicon- avalanche diode processes. They may be used to meet the ESD immunity require- ments of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge).
Applications
Mechanical Characteristics Cell Phone Handsets and Accessories Personal Digital Assistants (PDAs) Notebook and Hand Held Computers Portable Instrumentation Pagers Smart Cards MP3 Players 150 Watts peak pulse power (tp = 8/20µs) Transient protection for data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20µs) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 3.3V Solid-state EPD TVS technology JEDEC MO-211, 0.50 mm Flip Chip Package Non-conductive top side coating Marking : Marking Code Packaging : Tape and Reel SFC3.3-4 Maximum Dimensions (mm) 3 x 2 Grid Flip Chip TVS (Bottom View) 12 3 A B
2 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 Absolute Maximum Rating Electrical Characteristics (T=25oC) retemaraPl obmySs noitidnoCm uminiMl acipyTm umixaMs tinU egatloVffO-dnatSesreveRV MWR 3.3V egatloVhguorhT-hcnuPV TP I TP Aµ2=5 .3V egatloVkcaB-panSV BS I BS Am05=8 .2V tnerruCegakaeLesreveRI R V MWR C°52=T,V3.3=5 0.05 .0A µ egatloVgnipmalCV C I PP sµ02/8=pt,A1= dnuorGotO/IynA 5.4V egatloVgnipmalCV C I PP sµ02/8=pt,A5= dnuorGotO/IynA 8.6V egatloVgnipmalCV C I PP sµ02/8=pt,A51= dnuorGotO/IynA 5.9V egatloVgnipmalCdrawroFV F I PP sµ02/8=pt,A1= O/IynaotdnuorG 7.1V ecnaticapaCnoitcnuJC j dnanipO/IhcaE dnuorG VR zHM1=f,V0= 570 01F p gnitaRl obmySe ulaVs tinU )sµ02/8=pt(rewoPesluPkaePP kp 051s ttaW )sµ02/8=pt(tnerruCesluPkaePI PP 51A )riA(2-4-00016CEIrepDSE )tcatnoC(2-4-00016CEIrepDSE V DSE 52> 51> Vk erutarepmeTgnitarepOT J 521+ot55-C ° erutarepmeTegarotST GTS 051+ot55-C °
3 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 100 110 0 25 50 75 100 125 150 Ambient Temperature - T A (oC) % of Rated Power or IPP Clamping Voltage vs. Peak Pulse Current 100 110 0 5 10 15 20 25 30 Time (µs) Percent of IPP e td = IPP/2 Waveform Parameters: tr = 8µs td = 20µs Pulse Waveform Forward Voltage vs. Forward Current 0.00 2.00 4.00 6.00 8.00 10.00 12.00 0 5 10 15 20 Peak Pulse Current - I PP (A) Clamping Voltage - VC (V) Waveform Parameters: tr = 8µs td = 20µs L to L L to G 0.00 1.00 2.00 3.00 4.00 05 1 0 1 5 2 0 Peak Pulse Current - I PP (A) Clamping Voltage - VC (V) Waveform Parameters: tr = 8µs td = 20µs Normalized Junction Capacitance vs. Reverse Voltage 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (µs) Peak Pulse Power - Ppk (kW) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 01234 Reverse Voltage - VR (V) CJ(VR) / CJ(VR=0) f = 1 MHz
4 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 Device Schematic and Pin Configuration Layout Example Device Connection Options The SFC3.3-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 and B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Due to the “snap-back” characteristics of the low voltage TVS, it is not recommended that any of the I/O bumps be directly connected to a DC source greater than snap-back votlage (V SB) as the device can latch on as described the EPD TVS characteristics section. Flip Chip TVS Flip chip TVS devices are wafer level chip scale pack- ages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are com- patible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed how- ever for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC3.3-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.225 ± 0.010 mm with a solder mask opening of 0.350 ± 0.025 mm. Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coat- ings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems To Protected IC To Protected IC To Connector Ground Applications Information 6 54 12 3 A B
5 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 and should be avoided. Stencil Design A properly designed stencil is key to achieving ad- equate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using the reflow requirements for IPC/JEDEC standard J-STD-020 for assembly of small body components. During reflow, the component will self-align itself on the pad. EPD TVS Characteristics The SFC3.3-4 is constructed using Semtech’s propri- etary EPD technology. The structure of the EPD TVS is vastly different from the traditional pn-junction devices. At voltages below 5V, high leakage current and junction capacitance render conventional avalanche technology impractical for most applications. However, by utilizing the EPD technology, the SFC3.3-4 can effectively operate at 3.3V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in tradi- tional silicon-avalanche TVS diodes. Since the EPD TVS devices use a 4-layer structure, they exhibit a slightly different IV characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage (V RWM). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage PT) is exceeded. Unlike a conventional device, the low voltage TVS will exhibit a slight negative resistance characteristic as it conducts current. This characteris- tic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. When the TVS is conducting current, it will exhibit a slight “snap-back” or negative resistance characteris- tics due to its structures. This point is defined on the curve by the snap-back voltage (V SB) and snap-back current (ISB). To return to a non-conducting state, the Stencil Design Assembly Guideline for Pb-Free Soldering The following are recommendations for the assembly of this device: retemaraPylbmessAn oitadnemmoceR noitisopmoCllaBredloSu C7.0/gA8.3/nS5.59 ngiseDlicnetSredloSn gisedbPnSehtsaemaS ssenkcihTlicnetSredloS) "400.0(mm001.0 noitisopmoCetsaPredloS) 9.0-5.0(uC)4-3(gAnS epyTetsaPredloSr ellamsroerehpsezis4epyT eliforPwolfeRredloS0 20-DTS-JCEDEJrep ngiseDdaPredloSBCPn giseDbPnSehtsaemaS hsiniFdaPBCPi NuAroPSO current through the device must fall below the I SB (approximately <50mA) and the voltage must fall below the VSB (normally 2.8 volts for a 3.3V device). If a 3.3V TVS is connected to 3.3V DC source, it will never fall below the snap-back voltage of 2.8V and will therefore stay in a conducting state. The SFC3.3-4 is the first device to combine the advan- tages of flip chip technology with those of the EPD process technology.
6 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 Land Pattern - 3x2 Grid Flip Chip Outline Drawing - 3x2 Grid Flip Chip CL CL 6X Ø0.225
0.50 TYP
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE NOTES: YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 0.150±0.025 0.10 C 0.05 C 12 3 AA B 6X Ø0.175-0.225
0.05 C A B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS NOTES: 1.47±0.03 0.97±0.03 A B C 0.50 0.50 2. REFERENCE JEDEC REGISTRATION MO-211. INDEX AREA A1 CORNER Sn95.5/Ag3.8/Cu0.7 FOR Pb-FREE DEVICES.
7 2008 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC3.3-4 Marking Codes rebmuNtraP gnikraM edoC 4-3.3CFSU 34F rebmuNtraP hctiP noitpO repytQ leeR eziSleeR TCB.4-3.3CFS )1( mm20 00,3h cnI7
Ordering Information
Tape Specifications Device Orientation Pin A1Pin A1Pin A1 Contact Information Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 Marking Codes Notes (1) Lead Free Solder Balls Tape and Reel Specification TTTTTop Coating:op Coating:op Coating:op Coating:op Coating: The top (non-bump side) of the device is a black non-conductive coating. This material is compliant with UL 94V-0 flammability requirements. ChipClamp is a mark of Semtech Corporation