SFC2309-200

SFC2309-200 SEMTECH | Alldatasheet

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1 www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Flip Chip TVS Diode with T-Filter for Color LCD Interface Protection Description Features PIN Configuration Revision 06/11/03 5 x 5 Grid Flip Chip (Ball Side View) The SFC2309-200 is a low pass filter array with integrated TVS diodes. It is designed to suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic equipment. This state-of-the-art device utilizes solid- state silicon-avalanche technology for superior clamp- ing performance and DC electrical characteristics. They have been optimized for protection of colorprotection of colorprotection of colorprotection of colorprotection of color LCD panelsLCD panelsLCD panelsLCD panelsLCD panels in cellular phones and other portable electronics. The device consists of ten identical circuits comprised of TVS diodes for ESD protection, and a resistor - capacitor network for EMI/RFI filtering. A series resistor value of 200 Ω and a capacitance value of 45pF is used to achieve 25dB minimum attenuation from 800MHz to 3GHz. Each line features two stages of TVS diode protection. The TVS diodes provide effective suppression of ESD voltages in excess of ±15kV (air discharge) and ±8kV (contact discharge) per IEC 61000-4-2, level 4. The device is a 25-bump, 0.5mm pitch flip chip array with a 5x5 bump grid. It measures 2.6 x 2.6 x 0.65mm. The solder bumps have a nominal diameter of 0.315mm. Mechanical Characteristics Circuit Diagram LOW PASS FILTER

Applications

‹ Color LCD Panel Protection ‹ Cell Phone Handsets and Accessories ‹ Personal Digital Assistants (PDA’s) ‹ Notebook & Hand Held Computers ‹ JEDEC MO-211, Variation BF, 0.50 mm Pitch Flip Chip ‹ Nominal Dimensions: 2.6 x 2.6 x 0.65 mm ‹ Bump Diameter: 315±20 µm ‹ Marking : Marking code, dot at ball A1 ‹ Packaging : Tape and Reel per EIA 481 ‹ Flip Chip bidirectional EMI/RFI filter with integrated ESD protection ‹ ESD protection to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) ‹ Filter performance: 25dB minimum attenuation 800MHz to 3GHz ‹ TVS working voltage: 5V ‹ Resistor: 200 Ω ‹ Input Capacitance:45pF ‹ Protection and filtering for ten lines Circuit 10x C NI Fp54 RS 002 Ω

2 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Absolute Maximum Rating

Electrical Characteristics

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3 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Typical Characteristics Capacitance vs. Reverse Voltage Typical Insertion Loss S21 (Each Line) Analog Crosstalk (Each Line) ESD Clamping (8kV Contact) CH1 S21 LOG 6 dB/ REF 0 dB START . 030 000 MHz STOP 3 000 . 000 000 MHz Cor CH1 S21 LOG 20 dB/ REF 0 dB START . 030 000 MHz STOP 3 000 . 000 000 MHz Cor 0123456 Reverse Voltage - VR (V) Capacitance - CJ (pF) f = 1 MHz

4 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Applications Information Device Connection Options The SFC2309-200 has solder bumps located in a 5 x 5 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 5 along the horizontal axis and letters A - E along the vertical axis. The input of the lines to be protected are connected at bumps A1 - A5 and B1 - B5. The line outputs are connected at bumps D1 - D5 and E1 - E5. Bumps C1 - C5 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Wafer Level CSP TVS CSP TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manu- facturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with cur- rent pick and place equipment further reducing manu- facturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting flip chip devices. Solder mask defined (SMD) pads produce stress points at the solder mask to solder ball interface that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.275 ± 0.010 mm with a minimum solder mask opening of 0.325 mm. Grid Courtyard The recommended grid placement courtyard is 2.7 x 2.7 mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PCB, the highest recommended density is when one courtyard touches another. Pin Identification and Configuration (Ball Side View) niPn oitacifitnedI 5A-1A5 ,4,3,2,1seniL,tupnI 5B-1B0 1,9,8,7,6seniL,tupnI 5C-1Cd nuorG 5D-1D0 1,9,8,7,6seniL,tuptuO 5E-1E5 ,4,3,2,1seniL,tuptuO Layout Example (Ball Side View) 162738 4 9 5 1 0 617283 9 4 1 0 5 Output Input

5 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Applications Information Recommended NSMD Pad and Stencil Aperture Solder Reflow Profile Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coat- ings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Stencil Design A properly designed stencil is key to achieving ad- equate solder volume without compromising assembly yields. A 0.100mmto 0.200mm thick, laser cut, electro- polished stencil with 0.330mm apertures corners with rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using standard SMT reflow processes. As with any component, ther- mal profiles at specific board locations can vary & must be determined by the manufacturer. The flip chip TVS peak reflow temperature is 230 ± 10 °C for a maxi- mum time of 10 seconds. Time above eutectic tem- perature (183 °C) should be 50 ± 10 seconds. During reflow, the component self-aligns itself on the pad. Circuit Board Layout Recommendations for Suppres- sion of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: z Place the TVS near the input terminals or connec- tors to restrict transient coupling. z Minimize the path length between the TVS and the protected line. z Minimize all conductive loops including power and ground loops. z The ESD transient return path to ground should be kept as short as possible. z Never run critical signals near board edges. z Use ground planes whenever possible.

6 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Applications Information Implementation Example Baseband Controller LCD Display SFC2309-200 SFC2309-200 Baseband Controller LCD Display SFC2309-200 SFC2309-200

7 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Applications Information

50 Ohms

(Output) To Connector (Input) Insertion Loss Measurement Conditions Insertion Loss The insertion loss of the device is the ratio of the power delivered to the load with and without the filter in the circuit. This parameter is dependent upon the impedance of the source and the load. The standard impedance of test equipment that is used to measure filter frequency response is 50 Ω. In order to obtain an accurate measurement of the filter performance, an evaluation board with 50 Ω transmission lines are used. The test conditions for the SFC2309-200 are shown below. The evaluation board contains SMA connectors at each of the circuits inputs and outputs. The connections are made with 50 Ω traces. An HP 8753E network analyzer with an internal spectrum analyzer and tracking generator is used. This equip- ment has the capability to sweep the device from 3kHz to 3GHz. The analyzer’s source (R S) impedance is equal to the load (R L) impedance which is equal to 50Ω. Insertion Loss S21 CH1 S21 LOG 6 dB/ REF 0 dB START . 030 000 MHz STOP 3 000 . 000 000 MHz Cor

8 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Applications Information SFC2309-200 Spice Model & Parameters SFC2309-200 Spice Model sretemaraPecipS002-9032CFS retemaraPt inU) SVT(1D) SVT(2D SIp mA4 1-E14 1-E1 VBt loV1 .71 .7 JVt loV2 6.02 6.0 SRm hO4 21.04 21.0 VBIp mA3 -E13 -E1 OJCd araF2 1-E522 1-E52 TTc es9 -E145.29 -E145.2 M- -8 01.08 01.0 N- -5 0.15 0.1 GEV e1 1.11 1.1 Line In Line Out

9 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Land Pattern Outline Drawing 0.275 0.5 0.5

10 2003 Semtech Corp. www.semtech.com PRELIMINARYPROTECTION PRODUCTS SFC2309-200 Contact Information Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 Marking Ordering Information Top View Showing Laser Mark -200 2309 Lotcode rebmuNtraP seireS rotsiseR repytQ leeR eziSleeR CT.002-9032CFS0 02 Ω 0003h cnI7 Tape and Reel Specification Tape Specifications Device Orientation in Tape Pin A1 SFC2309 -200 SFC2309 -200 SFC2309 -200 SFC2309 -200 SFC2309 -200 Add “T” suffix for lead free bumps. Ex: SFC2309-200.TCT