Memory

SES900

NXP Semiconductors

DDR memory module temp sensor with integrated SPD, 3.3 V Rev. 07-29 January 2010

Manufacturer: NXP Semiconductors

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General description The NXP Semiconductors SE97 measures temperature from −40 °C to +125 °C with JEDEC Grade B ±1 °C accuracy between +75 °C and +95 °C and also provide 256 bytes of EEPROM memory communicating via the I2C-bus/SMBus. It is typically mounted on a Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature Sensor Component specification and also replacing the Serial Presence Detect (SPD) which is used to store memory module and vendor information. The SE97 thermal sensor operates over the VDD range of 3.0 V to 3.6 V and the EEPROM Placing the Temp Sensor (TS) on a DIMM allows accurate monitoring of the DIMM module temperature to better estimate the DRAM case temperature (Tcase) to prevent it from exceeding the maximum operating temperature of 85 °C. The chip set throttles the memory traffic based on the actual temperatures instead of the calculated worst-case temperature or the ambient temperature using a temp sensor mounted on the motherboard. There is up to 30 % improvement in thin and light notebooks that are using one or two 1 GB SO-DIMM modules. The TS is required on DDR3 RDIMM and RDIMM ECC. Future uses of the TS will include more dynamic control over thermal throttling, the ability to use the Alarm Window to create multiple temperature zones for dynamic throttling and to save processor time by scaling the memory refresh rate. The TS consists of a ΔΣ Analog-to-Digital Converter (ADC) that monitors and updates its own temperature readings 10 times per second, converts the reading to a digital data, and latches them into the data temperature register. User-programmable registers, the specification of upper/lower alarm and critical temperature trip points, EVENT output control, and temperature shutdown, provide flexibility for DIMM temperature-sensing applications. When the temperature changes beyond the specified boundary limits, the SE97 outputs an EVENT signal using an open-drain output that can be pulled up between 0.9 V and 3.6 V. The user has the option of setting the EVENT output signal polarity as either an active LOW or active HIGH comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. The EVENT output can even be configured as a critical temperature output. The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes (address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write Protected (RWP) by software. This allows DRAM vendor and product information to be stored and write protected. The upper 128 bytes (address 80h to FFh) are not write protected and can be used for general purpose data storage. SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Rev. 07 — 29 January 2010 Product data sheet

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 2 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V The SE97 has a single die for both the temp sensor and EEPROM for higher reliability and supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identity of the device. Three address pins allow up to eight devices to be controlled on a single bus. 2. Features

2.1 General features

JEDEC (JC-42.4) TSE 2002B3 DIMM ± 0.5 °C (typ.) between 75 °C and 95 °C temperature sensor plus 256-byte serial EEPROM for Serial Presence Detect (SPD) Optimized for voltage range: 3.0 V to 3.6 V, but SPD can be read down to 1.7 V Shutdown current: 0.1 μA (typ.) and 5.0 μA (max.) 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz SMBus ALERT Response Address and TIMEOUT (programmable) ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Available packages: TSSOP8, HVSON8, HXSON8, HWSON8 (JEDEC PSON8 VCED-3)

2.2 Temperature sensor features

11-bit ADC Temperature-to-Digital converter with 0.125 °C resolution Operating current: 250 μA (typ.) and 400 μA (max.) Programmable hysteresis threshold: off, 0 °C, 1.5 °C, 3 °C, 6 °C Over/under/critical temperature EVENT output B grade accuracy: ±0.5 °C/±1 °C (typ./max.) → +75 °C to +95 °C ±1.0 °C/±2 °C (typ./max.) → +40 °C to +125 °C ±2.0 °C/±3 °C (typ./max.) →− 40 °C to +125 °C

2.3 Serial EEPROM features

Operating current: Write → 0.6 mA (typ.) for 3.5 ms (typ.) Read → 100 μA (typ.) Organized as 1 block of 256 bytes [(256 × 8) bits] 100,000 write/erase cycles and 10 years of data retention Permanent and Reversible Software Write Protect Software Write Protection for the lower 128 bytes

SE97_7 © NXP B.V. 2010. All rights reserved. [1] SE97TL and SE97TP offer improved V POR/EVENT IOL. [2] Industry standard 2 mm × 3m m × 0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm × 4 mm pitch tape 4 k quantity reels. marking will start with ‘P’ for SPHK and ‘n’ for APB. Table 1. Ordering information

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 4 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 5. Block diagram Fig 1. Block diagram of SE97 002aab349 SCL SDA EVENT 2-kbit EEPROM NO WRITE PROTECT SOFTWARE WRITE PROTECT SE97 VSS SMBus/I2C-BUS INTERFACE VDD FFh 7Fh 00h TEMPERATURE REGISTER CRITICAL ALARM TRIP UPPER ALARM TRIP LOWER ALARM TRIP CAPABILITY MANUFACTURING ID DEVICE/REV ID SMBus TIMEOUT/ALERT CONFIGURATION

HYSTERESIS
SHUT DOWN TEMP SENSOR
LOCK PROTECTION
EVENT OUTPUT ON/OFF
EVENT OUTPUT POLARITY
EVENT OUTPUT STATUS
CLEAR EVENT OUTPUT STATUS POINTER REGISTER BAND GAP TEMPERATURE SENSOR 11-BIT ΔΣ ADC POR 10 V OVERVOLTAGE FILTER R 30 kΩ to 800 kΩ R 30 kΩ to 800 kΩ R 30 kΩ to 800 kΩ 80h

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 5 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 6. Pinning information

6.1 Pinning

Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for HXSON8 Fig 4. Pin configuration for HVSON8 Fig 5. Pin configuration for HWSON8 (SOT1069-1) Fig 6. Pin configuration for HWSON8 (SOT1069-2) SE97PW A0 V DD A1 EVENT A2 SCL VSS SDA 002aab805 terminal 1 index area 1A0 SE97TL 002aad548 Transparent top view 2A1 3A2 5VSS VDD EVENT SCL SDA 002aab803 SE97TK SDA VSS SCL A1 EVENT A0 VDD Transparent top view 4 5 3 6 2 7 1 8 terminal 1 index area terminal 1 index area 1A0 SE97TP 002aad768 Transparent top view 2A1 3A2 5VSS VDD EVENT SCL SDA VSS VDD EVENT SCL SDA terminal 1 index area SE97TP/S900 002aaf007 Transparent top view

6.2 Pin description

Table 2. Pin description input is overvoltage tolerant to support software write protection. (open-drain). Must have external pull-up resistor.

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 7 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 7. Functional description

7.1 Serial bus interface

The SE97 communicates with a host controller by means of the 2-wire serial bus (I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device supports SMBus, I2C-bus Standard-mode and Fast-mode. The I2C-bus standard speed is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus fast speed from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must be installed on these pins.

7.2 Slave address

The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. The A0, A1 and A2 pins are pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software write protect. When it is driven higher than 7.8 V, writing a special command would put the EEPROM in reversible write protect mode (see Section 7.10.2 “ Memory protection”). Each pin is sampled at the start of each I2C-bus/SMBus access. The temperature sensor’s fixed address is ‘0011b’. The EEPROM’s fixed address for the normal EEPROM read/write is ‘1010b’, and for EEPROM software protection command is ‘0110b’. Refer to Figure 7. a. Temperature sensor b. EEPROM (nor mal read/write) c. EEPROM (software protection command) Fig 7. Slave address R/W 002aab304 0 0 1 1 A2 A1 A0 fixed hardware selectable slave address MSB LSB X R/W 002aab351 1 0 1 0 A2 A1 A0 fixed hardware selectable slave address MSB LSB X R/W 002aab352 0 1 1 0 A2 A1 A0 fixed hardware selectable slave address MSB LSB X

7.3 EVENT output condition

The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT (CONFIG[7]) bands can be locked. Figure 8 shows an example of the measured temperature versus time, with the corresponding behavior of the EVENT output in each of these modes. Upon device power-up, the default condition for the EVENT output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can be read (CONFIG[4]) and cleared (CONFIG[5]).

Advisory note: – NXP device: After power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. – Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. – Work-around: In order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. – SE97B will allow bit 2 or bit 0 to be changed even if bit 3 is set. If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output remains asserted during shutdown.

7.3.1 EVENT pin output voltage levels and resistor sizing

The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and would not affect the output. From the system perspective, there will be a practical limit. That limit will be the voltage necessary for the device monitoring the interrupt pin to detect a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another thing to consider is the value of the pull-up resistor. When a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the EVENT pin.

7.3.2 EVENT thresholds

7.3.2.1 Alarm window

The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower temperature trip point as modified by hysteresis as programmed in the Configuration register. When enabled, the EVENT output triggers whenever entering or exiting (crossing above or below) the alarm window.

Advisory note: – NXP Device: The EVENT output can be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. – Competitor Device: The EVENT output can be cleared only through the Clear EVENT bit (CEVNT). – Work-around: Only clear EVENT output using the Clear EVENT bit (CEVNT). – There will be no change to NXP devices. The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm Trip.
Advisory note: – NXP device: Requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. – Competitor devices: Compares the alarm limit with temperature register at any time, so they get the EVENT output immediately when new UPPER or LOWER Alarm Windows and the EVENT output are set at the same time. – Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). – SE97B will compare alarm window and temperature register immediately.

7.3.2.2 Critical trip

The Tth(crit) temperature setting is programmed in the Critical Alarm Trip register (04h) as modified by hysteresis as programmed in the Configuration register. When the temperature reaches the critical temperature value in this register (and EVENT is enabled), the EVENT output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. The Event cannot be cleared through the Clear EVENT bit (CEVNT) or SMBus ALERT. The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip.

Advisory note: – NXP device: Requires one conversion cycle (125 ms) after setting the Alarm Window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output.

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 11 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V – Competitor devices: Compares the Alarm Window with temperature register at any time, so they get the EVENT output immediately when new Tth(crit) and EVENT output are set at the same time. – Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1). Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before EVENT output is enabled and Event value is checked. 1. Set Tth(crit). 2. Doing something else (make sure that exceeds 125 ms). 3. Enable the EVENT output (EOCTL = 1). 4. Wait 20 μs. 5. Read Event value. – SE97B will compare alarm window and temperature register immediately.

7.3.3 EVENT operation modes

7.3.3.1 Comparator mode

In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip resister if T th(crit) only is selected). Reads/writes on the registers do not affect the EVENT output in comparator mode. The EVENT signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. The comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range.

7.3.3.2 Interrupt mode

In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window threshold. After such an event occurs, writing a 1 to the Clear EVENT bit (CEVNT) in the configuration register de-asserts the EVENT output until the next trigger condition occurs. In interrupt mode, EVENT asserts when the temperature crosses the alarm upper boundary. If the EVENT output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, EVENT asserts again. Because the temperature is greater than the critical temperature threshold, a Clear EVENT command does not clear the EVENT output. Once the temperature drops below the critical temperature, EVENT de-asserts immediately.

Advisory note: – NXP device: If the EVENT output is not cleared before the temperature goes above the critical temperature threshold EVENT de-asserts immediately when temperature drops below the critical temperature. – Competitor devices: If the EVENT output is not cleared before or when the temperature is in the critical temperature threshold, EVENT will remain asserted after the temperature drops below the critical temperature until a Clear EVENT command.

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 12 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V – Work-around: Always clear the EVENT output before temperature exceeds the critical temperature. – SE97B will keep EVENT asserted after the temperature drops below the critical temperature until a Clear EVENT command de-asserts EVENT.

7.4 Conversion rate

The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second—the faster the conversion rate, the faster the temperature reading is updated. The SE97’s conversion rate is at least 8 Hz or 125 ms.

7.4.1 What temperature is read when conversion is in progress

The SE97 has been designed to ensure a valid temperature is always available. When a read to the temperature register is initiated through the SMBus, the device checks to see if the temperature conversion process (Analog-to-Digital conversion) is complete and a new temperature is available:

If the temperature conversion process is complete, then the new temperature value is sent out on the SMBus.
If the temperature conversion process in not complete, then the previous temperature value is sent out on the SMBus. It is possible that while SMBus Master is reading the temperature register, a new temperature conversion completes. However, this will not affect the data (MSB or LSB) that is being shifted out. On the next read of the temperature register, the new temperature value will be shifted out.

7.5 Power-up default condition

After power-on, the SE97 is initialized to the following default condition:

Starts monitoring local sensor
EVENT register is cleared; EVENT output is pulled HIGH by external pull-ups
EVENT hysteresis is defaulted to 0 °C
Command pointer is defaulted to ‘00h’
Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are defaulted to 0 °C
Capability register is defaulted to ‘0017h’ for the B grade
Operational mode: comparator
SMBus register is defaulted to ‘00h’

7.6 Device initialization

SE97 temperature sensors have programmable registers, which, upon power-up, default to zero. The open-drain EVENT output is default to being disabled, comparator mode and active LOW. The alarm trigger registers default to being unprotected. The configuration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT

7.7 SMBus time-out

is disabled by writing a ‘1’ to bit 7 of register 22h. the SMBus time-out specification limit of 10 kHz. The SE97 has no SCL driver, so it cannot hold the SCL line LOW. shutdown bit (SHMD) is set and turns off the oscillator.

7.8 SMBus ALERT Response Address (ARA)

signal LOW, it issues an ARA to which a slave device would respond with its address. that bit is set. Otherwise, the EVENT pin will not get de-asserted. be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications. Table 4. Registers to be initialized

hysteresis = 1.5 °C
EVENT output = Interrupt mode
EVENT output is enabled 02h 0000h 0550h Upper Boundary Alarm Trip register = 85 °C 03h 0000h 1F40h Lower Boundary Alarm Trip register = −20 °C 04h 0000h 05F0h Critical Alarm Trip register = 95 °C 22h 0000h 0000h SMBus register = no change

7.9 SMBus/I 2C-bus interface

The data registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to ‘00h’, the location for the Capability register. The Pointer register latches the last location to which it was set. Each data register falls into one of three types of user accessibility:

Read only
Write only
Write/Read same address A ‘write’ to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways:
If the location latched in the Pointer register is correct (most of the time it is expected that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes.
If the Pointer register needs to be set, then an address byte, pointer byte, repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to timing diagrams Figure 10 to Figure 13 for how to program the device. Fig 9. How SE97 responds to SMBus ALERT Response Address 0 0 0 1 1 A2 Alert Response Address 1 1 0 0S 0 0 0 START bit read acknowledge 002aac685 A1 A0 0 1 P device address no acknowledge STOP bit host NACK and sends a STOP bit Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'. master sends a START bit, ARA and a read command host detects SMBus ALERT A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 10. SMBus/I 2C-bus write to the Pointer register 123456789123456789 SCL A6 A5 A4 A3 A2 A1 A0SDA D7 D6 D5 D4 D3 D2 D1 D0 device address and write register address WAS START ACK by device P STOP A ACK by device 002aab308

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 15 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 11. SMBus/I 2C-bus write to the Pointer register followed by a write data word 123456789123456789 SCL A6 A5 A4 A3 A2 A1 A0SDA D7 D6 D5 D4 D3 D2 D1 D0 device address and write write register address WAS START by host ACK by device A ACK by device (cont.) (cont.) 002aab412 123456789123456789 SCL D15 D14 D13 D12 D11 D10 D9SDA D7 D6 D5 D4 D3 D2 D1 D0 most significant byte data least significant byte data A by host ACK by device P STOP by host A ACK by device A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 12. SMBus/I 2C-bus write to Pointer register followed by a repeated START and an immediate data word read 123456789123456789 SCL A6 A5 A4 A3 A2 A1 A0SDA D7 D6 D5 D4 D3 D2 D1 D0 device address and write read register address WAS START by host ACK by device A ACK by device (cont.) (cont.) 123456789 D15 D14 D13 D12 D11 D10 D9 D8 returned most significant byte data A ACK by host SCL SDA 123456789 SCL A6 A5 A4 A3 A2 A1 A0SDA device address and read RASR repeated START by host ACK by device (cont.) (cont.) 002aac686 123456789 D7 D6 D5 D4 D3 D2 D1 D0 returned least significant byte data P STOP by host A NACK by host

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 16 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 13. SMBus/I 2C-bus word read from register with a pre-set pointer 123456789 D15 D14 D13 D12 D11 D10 D9 D8 returned most significant byte data A ACK by host SCL SDA 123456789 SCL A6 A5 A4 A3 A2 A1 A0SDA device address and read RA ACK by device (cont.) (cont.) 002aac687 123456789 D7 D6 D5 D4 D3 D2 D1 D0 returned least significant byte data P STOPNACK by host S START by host A

7.10 EEPROM operation

The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or 16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported. Communication with the EEPROM is via the 2-wire serial I2C-bus or SMBus. Figure 14 provides an overview of the EEPROM partitioning. The EEPROM can be read over voltage range 1.7 V to 3.6 V, but all write operations must be done 3.0 V to 3.6 V.

7.10.1 Write operations

7.10.1.1 Byte Write

In Byte Write mode the master creates a START condition and then broadcasts the slave address, byte address, and data to be written. The slave acknowledges all 3 bytes by pulling down the SDA line during the ninth clock cycle following each byte. The master creates a STOP condition after the last ACK from the slave, which then starts the internal write operation (see Figure 15). During internal write, the slave will ignore any read/write request from the master. Fig 14. EEPROM partitioning FFh 80h 7Fh 0Fh 00h 00h 01h 07h … 1 page or 16 bytes 8 pages or 128 bytes 16 pages or 256 bytes no write protect write protect by software 002aac812 Fig 15. Byte Write timing 002aab246 0 1 0 A2 A1 A0 0 AS 1 A P slave address (memory) START condition R/W acknowledge from slave acknowledge from slave word address SDA STOP condition; write to the memory is performed data DATA A acknowledge from slave

7.10.1.2 Page Write

The SE97 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four Most Significant Bits (MSB) of the address byte presented to the device after the slave address, while the four Least Significant Bits (LSB) point to the byte within the page. By loading more than one data byte into the device, up to an entire page can be written in one write cycle (see Figure 16). The internal byte address counter will increment automatically after each data byte. If the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around fashion within the selected page. The internal write cycle is started following the STOP condition created by the master.

7.10.1.3 Acknowledge polling

Acknowledge polling can be used to determine if the SE97 is busy writing or is ready to accept commands. Polling is implemented by sending a ‘Selective Read’ command (described in Section 7.10.3 “Read operations”) to the device. The SE97 will not acknowledge the slave address as long as internal write is in progress.

7.10.2 Memory protection

The lower half (the first 128 bytes) of the memory can be write protected by special EEPROM commands without an external control pin. The SE97 features three types of memory write protection instructions, and three respective read Protection instructions. The level of write-protection (set or clear) that has been defined using these instructions remained defined even after power cycle. The memory protection commands are:

Permanent Write Protection (PWP)
Reversible Write Protection (RWP)
Clear Write Protection (CWP)
Read Permanent Write Protection (RPWP)
Read Reversible Write Protection (RRWP)
Read Clear Write Protection (RCWP) Fig 16. Page Write timing 0 1 0 A2 A1 A0 0 AS 1 A slave address (memory) START condition R/W acknowledge from slave acknowledge from slave word address SDA data to memory DATA n A acknowledge from slave 002aab247 P STOP condition; write to the memory is performed data to memory DATA n + 15 A acknowledge from slave

SE97_7 © NXP B.V. 2010. All rights reserved. Table 5 is the summary for normal and memory protection instructions. [1] The most significant bi t, bit 7, is sent first. [2] A0, A1, and A2 are compared against t he respective external pins on the SE97. [3] V I(ov) ranges from 7.8 V to 10 V. read/write bit. This bit is set to 1 or 0 for read and write protection, respectively. write protection instructions (i.e., PWP, RWP, CWP). Table 5. EEPROM commands summary (1) Refer to Table 6 regarding the exact state of the acknowledge bit.

7.10.2.1 Permanent Write Protection (PWP)

fixed address of 0110b) to access the write-protection settings.

7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP)

again with a CRWP instruction. (A1 and A2), as shown in Table 5. (1) Refer to Table 7 regarding the exact state of the acknowledge bit. Table 6. Acknowledge when writing data or defining write protection Instructions with R/W bit = 0.

7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection

the instructions are issued.

7.10.3 Read operations

7.10.3.1 Current address read

issuing a No Acknowledge on the ninth bit then followed by a STOP condition.

7.10.3.2 Selective read

Table 7. Acknowledge when reading the write protection Instructions with R/W bit = 1.

7.10.3.3 Sequential read

If the master acknowledges the first data byte transmitted by the SE97, then the device will continue transmitting as long as each data byte is acknowledged by the master (Figure 21). If the end of memory is reached during sequential Read, the address counter will ‘wrap around’ to the beginning of memory, and so on. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Fig 20. Selective read timing 0 1 0 A2 A1 A0 0 AS 1 A slave address (memory) START condition R/W acknowledge from slave acknowledge from slave word address SDA 002aac901 P STOP condition data from memory A no acknowledge from master 0 1 0 A2 A1 A0S 1 slave address (memory) START condition 1 A R/W acknowledge from slave Fig 21. Sequential read timing 0 1 0 A2 A1 A0 1 AS 1 A slave address (memory) START condition R/W acknowledge from slave acknowledge from master data from memory SDA data from memory DATA n + 1 A acknowledge from master 002aab253 P STOP condition data from memory DATA n + X A no acknowledge from master DATA n

7.11 Hot plugging

robust and not prone to false operation. in reset until SCL is released.

8.1 Register overview

is an 8-bit register. All other registers are 16-bit. reset by removing and re-applying its power. Table 8. Register summary

8.2 Capability register (00h, 16-bit read-only)

be implemented. Bit 5 is changed from ‘0’ to ‘1’ on the future 1.7 V to 3.6 V SE97B. Table 9. Capability register (address 00h) bit allocation Table 10. Capability register (address 00h) bit description 15:6 RFU Reserved for future use; must be zero. 5 VHV High voltage standoff for pin A0. support JC42.4 ballot 1435.00. 4:3 TRES Temperature resolution. 1 HACC Higher accuracy (set during manufacture).

8.3 Configuration register (01h, 16-bit read/write)

Table 11. Configuration register (address 01h) bit allocation Table 12. Configuration register (address 01h) bit description 15:11 RFU reserved for future use; must be ‘0’. cannot be altered until unlocked.

The EEPROM read works over the entire supply range of 1.7 V to 3.6 V whether or not SHMD is set because it does not need oscillator to function. There is no undervoltage lockout, the device no longer responds at some voltage below 1.7 V.
EEPROM write works over the supply range of 3.0 V to 3.6 V, but not if SHMD is set since the oscillator is needed to write to EEPROM. There is an undervoltage lockout around 2.7 V that disables the RRPROM write operation.
Thermal sensor is operational over the supply range of 3.0 V to 3.6 V, but not if SHMD is set since the oscillator is needed. There is an undervoltage lockout around 2.7 V that disables the temp sensor. Thermal sensor auto turn-off feature: It was determined during testing of the SE97TP on 5 May 2008 that the Thermal Sensor auto turn-off feature was not compatible with the JEDEC power supply maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was disabled for all SE97 samples/production devices tested after 6 May (wk 0818 date code is when the devices were assembled). If there is a slow ramp rate on the supply voltage to 3.3 V the SE97 would be EE read only and not Thermal Sensor. This is due to a feature integrated into the device to automatically turn off the oscillator and place the thermal sensor in shutdown if the SE97 was being used in SO-DIMM in notebook applications at 1.8 V to reduce the power consumption on the battery. The feature counts for 30 ms (± 5 ms) after the oscillator starts working (around 1.2 V to 1.7 V) and if at 30 ms the voltage is greater than 2.4 V, the oscillator is left on and the Thermal Sensor functions as normal. But if the voltage is less than 2.4 V at 30 ms, the oscillator is turned off and the SE97 will think the part is in SPD only mode defaulting to the oscillator and Thermal Sensor disabled (SHMD Shutdown Mode bit 8 = 1). The oscillator and Thermal Sensor can be re-enabled by writing a logic 0 to SHMD. It is important in RDIMM/server applications that the Thermal Sensor is working as the default condition since the Thermal Sensor needs to be compatible with the JEDEC power supply ramp rate (maximum ramp rate is 70 ms to 100 ms) so the Thermal Sensor auto turn-off feature was disabled starting on 6 May 2008 by changing a programmable bit on the device during final test. There is no change in performance of the SE97 with this feature turned off and was verified during characterization. There is no way to read the SE97 registers via the I 2C-bus to determine if the Thermal Sensor auto turn-off feature is enabled or disabled. This is set in a factory only register. You need to check the date code or do an operational test (e.g., run up to < 2.4 V, hold, then go to

3.3 V, then read SHMD bit 8 in the Configuration register to see if it is set to

versus samples with this feature disabled in all production devices.

SE97_7 © NXP B.V. 2010. All rights reserved. 7 CTLB Critical Trip Lock bit. write and do not require double writes. 6 AWLB Alarm Window Lock bit. and does not require double writes. 5 CEVNT Clear EVENT (write only). When read, this register always returns zero. 4 ESTAT EVENT Status (read only). EVENT’ bit (CEVNT). Writing to this bit will have no effect. 3 EOCTL EVENT Output Control.

Advisory note: – JEDEC specification requires only the Alarm Window lock bit to be set. – Work-around: Clear both Critical Trip and Alarm Window lock bits. – Future 1.7 V to 3.6 V SE97B will require only the Alarm Window lock bit to be set. 1 EP EVENT Polarity. 0 — active LOW (default) 1 — active HIGH. When either of the Critic al Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.

Table 12. Configuration register (address 01h) bit description …continued

8.4 Temperature format

word with the least significant bit (LSB) equal to 0.125 °C (resolution).

A value of 019Ch will represent 25.75 °C
A value of 07C0h will represent 124 °C
A value of 1E64h will represent −25.75 °C. The unused LSB (bit 0) is set to ‘0’. Bit 11 will have a resolution of 128 °C. The upper 3 bits of the temperature register indicate Trip Status based on the current temperature, and are not affected by the status of the EVENT output. Table 14 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b.

Table 14. Degree Celsius and Temperature Data register

8.5 Temperature Trip Point registers

8.5.1 Upper Boundary Alarm Trip register (16-bit read/write)

avoid superfluous interrupt activity. Table 15. Upper Boundary Alarm Trip register bit allocation Table 16. Upper Boundary Alarm Trip register bit description

12 SIGN Sign (MSB)

8.5.2 Lower Boundary Alarm Trip register (16-bit read/write)

avoid superfluous interrupt activity.

8.5.3 Critical Alarm Trip register (16-bit read/write)

bit 2 = 0.25 °C. RFU bits will always report zero. Table 17. Lower Boundary Alarm Trip register bit allocation Table 18. Lower Boundary Alarm Trip register bit description Table 19. Lower Boundary Alarm Trip register bit allocation Table 20. Critical Alarm Trip register bit description

8.6 Temperature register (16-bit read-only)

Table 21. Temperature register bit allocation Table 22. Temperature register bit description

0 RFU reserved; always ‘0’

8.7 Manufacturer’s ID regi ster (16-bit read-only)

8.8 Device ID register

The SE97 device ID is A2h. The device revision varies by device. [1] 00 for SE97PW, SE97TK (original) is 00h. 01 for SE97TL, SE97TP (improved VPOR and EVENT IOL) is 01h. Table 23. Manufacturer’s ID register bit allocation Table 24. Device ID register bit allocation

8.9 SMBus register

Table 25. SMBus Time-out register bit allocation Table 26. SMBus Time-out register bit description cannot be altered until unlocked. 0 SALRT SMBus ALERT Response Address (ARA). cannot be altered until unlocked.

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 35 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 9. Application design-in information In a typical application, the SE97 behaves as a slave device and interfaces to a bus master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to VDD or VSS without any pull-up resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are 10 kΩ, but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. Fig 23. Typical application showin g SE97 interfacing with 3.3 V host 002aab354 HOST CONTROLLERSE97 SCL SDA EVENT VDD 10 kΩ (3×) VSS slave master 3.3 V Fig 24. SE97 interfacing with 1.1 V host controller 002aad262 HOST CONTROLLERSE97 SCL SDA EVENT VDD 10 kΩ VSS 3.3 V 0.1 μF 10 kΩ PCA9509 mother board 0.1 μF VCC(B) EN VCC(A) 10 kΩ10 kΩ SCL SDA EVENT 0.1 μF 1.1 V

9.1 SE97 in memory module application

Figure 25 shows the SE97 being placed in the memory module application. The SE97 is centered in the memory module to monitor the temperature of the DRAM and also to provide a 2-kbit EEPROM as the Serial Presence Detect (SPD). In the event of overheating, the SE97 triggers the EVENT output and the memory controller throttles the memory bus to slow the DRAM. The memory controller can also read the SE97 and watch the DRAM thermal behavior, taking preventive measures when necessary.

9.2 Layout consideration

The SE97 does not require any additional components other than the host controller to read its temperature. It is recommended that a 0.1 μF bypass capacitor between the VDD and VSS pins is located as close as possible to the power and ground pins for noise protection.

9.3 Thermal considerations

In general, self-heating is the result of power consumption and not a concern, especially with the SE97, which consumes very low power. In the event the SDA and EVENT pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 °C. Equation 1 is the formula to calculate the effect of self-heating: (1) where: ΔT = Tj − Tamb Tj = junction temperature Tamb = ambient temperature Rth(j-a) = package thermal resistance VDD = supply voltage IDD(AV) = average supply current Fig 25. System application 002aac800 SE97 EVENT DIMM DRAM DRAM DRAM DRAM MEMORY CONTROLLER SMBus CPU ΔTR th j-a() VDD IDD AV()×() VOL SDA() IOL ksin() SDA()×() VOL EVENT() IOL ksin() EVENT×()++[ ]

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 40 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V I2C-bus and EEPROM inactive. I 2C-bus, temp sensor and EEPROM inactive. Fig 26. Average supply current Fig 27. Shutdown supply current Temp sensor and EEPROM active. V DD = 3.0 V to 3.6 V. Fig 28. Average supp ly current during EEPROM write Fig 29. Typical temperature accuracy VOL1 =0 . 4V . V OL1 =0 . 4V . Fig 30. EVENT output current SE97PW, SE97TK Fig 31. EVENT output current SE97TL, SE97TP 200 300 100 400 500 IDD(AV) (μA) Tamb (°C) −40 120 8004 0 002aac910 VDD = 3.6 V 3.0 V I sd(VDD) (μA) Tamb (°C) −40 120 8004 0 002aac911 VDD = 3.6 V 3.0 V 200 500 400 300 600 IDD(AV) (μA) 002aac912 Tamb (°C) −40 120 8004 0 VDD = 3.6 V 3.0 V −2.0 3.5 −3.5 Tamb (°C) −50 125 002aad769 1007550250−25 2.0 Tlim(acc) (°C) −1.0 1.0 2.0 8.0 IOL (mA) Tamb (°C) −50 125 002aad258 1007550250−25 6.0 4.0 VDD = 3.0 V to 3.6 V VDD = 1.7 V Tamb (°C) −50 125 002aad767 1007550250−25 VDD = 3.7 V 3.3 V 2.9 V 1.7 V I OL(sink)EVENT (mA)

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 41 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Fig 32. SDA output current Fig 33. Conversion rate Fig 34. Conversion period Fi g 35. EEPROM write cycle time For temp sensor conversion. VDD = 3.0 V to 3.6 V. For EEPROM read operation. VDD = 1.7 V to 3.6 V. Fig 36. Average power-on threshold voltage Fig 37. Average power-on threshold voltage Tamb (°C) −40 120 8004 0 002aac907 VDD = 3.6 V 3.0 V IOL(sink)(SDA) (mA) Tamb (°C) −40 120 8004 0 002aac908 conversion rate (conv/s) 120 100 140 Tconv (ms) 002aac909 Tamb (°C) −40 120 8004 0 T cy(W) (ms) Tamb (°C) −40 120 8004 0 002aac902 2.4 2.6 2.2 2.8 3.0 Vth (V) 2.0 Tamb (°C) −40 120 8004 0 002aac903 1.2 1.4 1.6 V th (V) 1.0 Tamb (°C) −40 120 8004 0 002aac904

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 42 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V VDD = 3.0 V to 3.6 V. From 25 °C (air) to 120 °C (oil bath). (1) TSSOP8 (2) HVSON8, HWSON8, HXSON8 V DD = 3.3 V + 150 mV (p-p); 0.1 μF AC coupling capacitor; no decoupling capacitor; Tamb =2 5 °C. Fig 38. Package thermal response Fig 39. Temperature error versus power supply noise frequency 120 thermal response (%) time (s) 05 4231 002aac905 (1) (2) noise frequency (Hz) 102 108107106103 105104 002aac914 temp error (°C)

SE97_7 © NXP B.V. 2010. All rights reserved. [1] Minimum clock frequency is 0 kHz if SMBus Time-out is disabled. [2] Delay from SDA STOP to SDA START. undefined region of the falling edge of SCL. [4] Delay from SCL HIGH-to-LOW transition to SDA edges. [5] Delay from SCL LOW-to-HIGH transition to restart SDA. [6] Delay from SDA START to first SCL HIGH-to-LOW transition. [7] These parameters tested initially and after a design or process change that affects the parameter. pu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. Table 30. SMBus AC characteristics VDD = 1.7 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design.

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 44 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V [9] The write cycle time is the time elapsed between the STOP co mmand (following the write instruction) and the completion of the internal write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands. S = START condition P = STOP condition Fig 40. AC waveforms 002aae750 tLOW SDA P S tBUF tHD;STA tr tHD;DAT tHIGH tSU;DAT tSU;STA tHD;DAT S P tSU;STO VIH VIL VIH VIL SCL SDA SCL tSU;STO VIH VIL VIH VIL tW STOP condition START condition tSU;STA write cycle tf

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 45 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 12. Package outline Fig 41. Package outline SOT530-1 (TSSOP8) UNIT A1 A max. A2 A3 bp LHE Lp wyvce D(1) E(2) Z(1) θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.13 3.1 2.9 4.5 4.3 0.65 6.5 6.3 0.70 0.35 0°0.1 0.10.10.94 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.5 SOT530-1 MO-153 00-02-24 03-02-18 w Mbp D Z e 0.25 8 5 θ AA2 Lp (A3) detail X L HE E c v M A X A y 2.5 5 mm0 scale TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 1.1 pin 1 index

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 46 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Fig 42. Package outline SOT908-1 (HVSON8) 0.50.21 0.05 0.00 A1 EhbUNIT D(1) ye 1.5 REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 cD h 1.65 1.35 3.1 2.9 2.25 1.95 0.3 0.2 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT908-1 MO-229 E(1) 0.5 0.3 L 0.1 v 0.05 w SOT908-1 HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm A(1) max. 05-09-26 05-10-05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. X terminal 1 index area B AD E detail X A c C yCy1 exposed tie bar (4×) exposed tie bar (4×) b terminal 1 index area e AC B v M C w M Eh Dh L 0 1 2 mm scale

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 47 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Fig 43. Package outline SOT1052-1 (HXSON8) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT1052-1 MO-229 SOT1052-1 Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 DIMENSIONS (mm are the original dimensions) HXSON8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm UNIT mm max nom min 0.5 0.04 2.1 2.0 1.9 1.6 1.4 0.5 3.1 3.0 2.9 1.6 1.4 0.45 0.35 0.3 0.2 0.1 0.05 0.05 A (1) A1 b D D1 E E1 e L v y y1 0 1 2 mm scale terminal 1 index area Dh e 1/2 e Eh L B AD E terminal 1 index area X BAb v M detail X A Cy1 C y (8×) 08-01-11 08-03-11

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 48 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Fig 44. Package outline SOT1069-1 (HWSON8) ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT1069-1 MO-229 sot1069-1_po 08-07-10 09-08-10 Unit mm max nom min 0.80 0.75 0.70 0.05 0.02 0.2 0.30 0.25 0.20 2.1 2.0 1.9 1.6 1.4 1.6 1.4 0.5 0.45 0.35 A (1) Dimensions Note 1. Dimension A is including plating thickness. The package footprint is compatible with JEDEC MO229 HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm SOT1069-1 A1 A2 0.65 0.55 0.45 A 3 bD D 2 E 3.1 3.0 2.9 E 2 eK 0.2 Lv 0.1 y 0.05 0.05 0 1 2 mm scale B AD E terminal 1 index area X BAb v Cy1 C y (8×) detail X A terminal 1 index area e 1/2 e L K

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 49 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V Fig 45. Package outline SOT1069-2 (HWSON8) ReferencesOutline version European projection Issue date IEC JEDEC JEITA sot1069-2_po 09-10-22 09-11-18 Unit mm max nom min 0.80 0.75 0.70 0.05 0.02 0.00 2.1 2.0 1.9 1.6 1.5 1.4 3.1 3.0 2.9 0.5 1.5 0.45 0.40 0.35 0.05 A (1) Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm SOT1069-2 0.65 0.55 0.45 A 0.2 A3 b 0.30 0.25 0.18 D (1) D2 E(1) E2 1.6 1.5 1.4 ee 1 K 0.40 0.35 0.30 Lv 0.1 w 0.05 y 0.05 y 0 1 2 mm scale X C yCy1 terminal 1 index area B AD E detail X A terminal 1 index area b e AC Bv Cw L K 1 4

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 50 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath specifications, including temperature and impurities

13.4 Reflow soldering

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 46) than a SnPb process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 31 and 32 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 46.

Table 31. SnPb eutectic process (from J-STD-020C) Table 32. Lead-free process (from J-STD-020C)

Table 1 “Ordering information”: – added Type number SE97TP/S900 – added Table note [3]
Added (new) Figure 6 “Pin configuration for HWSON8 (SOT1069-2)”
Section 7.7 “SMBus time-out”, 1st paragraph, second sentence: changed from “between 25 ns and 35 ms” to “between 25 ms and 35 ms”
Table 8 “Register summary”, address 07h (Device ID/Revision register): – Default state is split: A200h for SE97PW, SE97TK; A201h for SE97TP, SE97TL
Section 8.8 “Device ID register”: – 1st paragraph, 1st sentence: changed from “The SE97 device ID is A1h.” to “The SE97 device ID is A2h.” – Table note [1] modified
Added (new) Figure 45 “Package outline SOT1069-2 (HWSON8)” SE97_6 20090817 Product data sheet - SE97_5 SE97_5 20090806 Product data sheet - SE97_4 SE97_4 20090130 Product data sheet - SE97_3 SE97_3 20080715 Product data sheet - SE97_2 SE97_2 20071012 Product data sheet - SE97_1 SE97_1 20070524 Objective data sheet - -

SE97_7 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 January 2010 54 of 55 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V 16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.

DDR memory module temp sensor with integrated SPD, 3.3 V © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 January 2010 Document identifier: SE97_7 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents

7.3 EVENT

7.3.1 EVENT pin output voltage levels and

7.3.3 EVENT

7.4.1 What temperature is read when

7.8 SMBus ALERT Response Address

7.9 SMBus/I

7.10.2.2 Reversible Write Protection (RWP) and

Clear Reversible Write Protection (CRWP) . . 20

7.10.2.3 Read Permanent Write Protection (RPWP),

Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection

8.2 Capability register

8.3 Configuration register

8.5.1 Upper Boundary Alarm Trip register

8.5.2 Lower Boundary Alarm Trip register

8.5.3 Critical Ala rm Trip register

8.6 Temperature register

8.7 Manufacturer’s ID register

Product Information

SES900 specifications and overview.

Summary

DDR memory module temp sensor with integrated SPD, 3.3 V Rev. 07-29 January 2010

Description

DDR memory module temp sensor with integrated SPD, 3.3 V Rev. 07-29 January 2010

Source title SES900 Datasheet(PDF) - NXP Semiconductors

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