SERCON410B STMICROELECTRONICS | Alldatasheet
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USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein : 1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when prop- erly used in accordance with instructions for use pro- vided with the product, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can reason- ably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
NOTES: SERCON410B
This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice. May 1994 SERCOS INTERFACE CONTROLLER (Ordering Number: SERGBQA) PQFP100 Single-chip controller for SERCOS interface Real time communication for industrial control systems 8/16-bit bus interface, Intel and Motorola con- trol signals Dual port RAM with 1024 words * 16-bit Data communications via optical fiber rings, RS 485 rings and RS 485 busses Maximum transmission rate of 4 Mbaud with in- ternal clock recovery Maximum transmission rate of 10 Mbaud with external clock recovery Internal repeater for ring connections Full duplex operation Modulation of power of optical transmitter diode Automatic transmission of synchronous and data telegrams in the communication cycle Flexible RAM configuration, communication data stored in RAM (single or double buffer) or transfer via DMA Synchronization by external signal Timing control signals Automatic service channel transmission 100-pin plastic flat-pack casing
Figure 1. SERCON410B Block Diagram
Figure 2. SERCON410B Pin Configuration
1 GENERAL DESCRIPTION
The SERCOS interface controller SERCON410B is an integrated circuit for SERCOS interface com- munication systems. The SERCOS interface is a digital interface for communication between sys- tems which have to exchange information cycli- cally at short, fixed intervals (65 µs to 65 ms). It is appropriate for the synchronous operation of dis- tributed control or test equipment (e.g. connection between drives and numeric control). A SERCOS interface communication system con- sists of one master and several slaves (Fig. 3). These units are connected by a fiber optical ring. This ring starts and ends at the master. The slaves regenerate and repeat their received data or send their own telegrams. By this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves. The optical fiber assures a reliable high- speed data transmission with excellent noise im- munity. The SERCOS interface controller contains all the hardware-related functions of the SERCOS inter- face and considerably reduces thehardware costs and the computing time requirements of the microprocessor. It is the direct link between the electro-optical receiver and transmitter and the mi- croprocessor that executes the control algorithms. The SERCON410B can be used both for SERCOS interface masters and slaves. The circuit contains the following functions (Fig. 1): - Interface to the microprocessor with a data bus width of 8 or 16 bits and with control lines according to Intel or Motorola standards. -A serial interface for making a direct connec- tion with the optical receiver and transmitter of the fiber optic ring or with drivers to an electric ring or bus. Data and clock regeneration, the repeater for ring topologies and the serial transmitter and receiver are integrated. The signals are monitored and test signals gener- ated. The serial interface operates up to 4Mbaud without external circuitry and up to 10 Mbaud with external clock regeneration. -A dual port RAM (1024 * 16 bit) for control and communication data. The organization of the memory is flexible. -Telegram processing for automatic transmis- sion and monitoring of synchronous and data telegrams. Only transmission data which is in- tended for the particular interface user is proc- essed. The transmitted data is either stored in the internal RAM (single or double buffer) or transferred via direct memory access (DMA). The transmission of service channel informa- tion over several communication cycles is exe- cuted automatically. In addition to the SERCOS interface the SER- CON410B can also be used for other real-time communications tasks. As an alternative to the fi- beroptical ring also bus topologies with RS-485 signals are supported (Fig. 4). The SERCON410B is therefore suitable for a wide range of applica- tions. SERCON410B
2 PIN DESCRIPTION
which is stored in the address latch with ALEL and ALEH is input via D15-0. (BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1). access the control registers PCSN0 must equal 0 and PCS1 must equal 1. memory location by the internal telegram processing. the receive FIFO, DMAREQR becomes inactive. FIFO is read, independent of the levels on A6-1 and the chip select signals. beginning of the last write access to the transmit FIFO. the levels on A6-1 and the chip select signals. ADMUX is 1 A15-0 are the outputs of the address latch. (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1). BUSWIDTH 99 I Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). Table 1. SERCON410B I/O Port Function Summary
word are addressed (high byte first). overwritten by the microprocessor. RxD 14 I Receive data for the serial interface. TxD1 16 O Transmit data. The pin can be switched to a high impedance state. can be switched to a high impedance state individual ly. TxDNRZ 24 O NRZ-coded transmit data. 25 O Transmitter active, active low. When transmitting own data IDLE is 0.
34 I SERCOS interface cycle clock: CYC_CLK synchronizes the
communication cycles. The polarity is programmable. polarity and width are programmable. programmable, the pulse width is 1µs. baud rate, the maximum frequency is 64 MHz. Table 1. SERCON410B I/O Port Function Summary(Continued)
SCLKO2 6 O Clock output: outputs the SCLK clock divided by 2. SCLKO4 5 O Clock output: outputs the SCLK clock divided by 4. RSTN 10 I Reset, active low. Must be zero for at least 50 ns after power on. TEST 7 I Test, active high. Has to be tied to V SS . reset. For the in-circuit test and for turning on the powerdown mode.
3 ELECTRICAL CHARACTERISTICS
3.1 ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit VDD Supply Voltage -0.3 to 7.0 V VI Input Voltage V SS - 0.3 to VDD + 0.3 V VO Output Voltage V SS - 0.3 to VDD + 0.3 V TSTG Storage Temperature -55 to +150 °C
3.2 RECOMMENDED OPERATING CONDITIONS
Min. Max. TA Operating Temperature -40 85 °C VDD Operating Supply Voltage 4.75 5.25 V fSCLK Clock Frequency SCLK 64 MHz fMCLK Clock Frequency MCLK 20 MHz fTxC ,fRxC Clock Frequency TxC, RxC 10 MHz Symbol Parameter Test Conditions Value Unit Min. Typ. Max. VIL Input Low Level Voltage 0.8 V VIH Input High Level Voltage 2.4 V VT+ Schmitt trig. +ve threshold All pins except D15-0, A15-0, ALEL, ALEH, RDN, WRN, BHEN, MCSN0-1, PCSN0, PCS1, DMAACKTN, DMAACKRN 2.0 2.4 V VT- Schmitt trig. +ve threshold 0.6 0.8 V (VDD =5 V± 5% TA = -40°C to +85°C, unless otherwise specified)
3.3 DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Value Unit Min. Typ. Max. IIL Low Level Input Current (Pull-up resistor) VI = VSS -450 -50 -30 µA IIH High Level Input Current VI = VDD -10 <1 10 µA VOL Low level Output Voltage, all O- and I/O-pins except TXD6-1IOI = -4 mA 0.4 V VOH High level output voltage, all O- and I/O-pins except TXD6-1IOH = +4 mA 2.4 V VOL High level output voltage, all O- and I/O-pins except TXD6-1IOI = -8 mA 0.4 V VOH High level output voltage, pins TXD6-1 IOH = +8 mA V DD - 0.5 IOZ Tri-state output leakage V O =0Vo rV DD -10 <1 +10 µA IKLU I/O latch-up current V<V SS V>V DD 200mA mA VESD Electrostatic protection C=100 pF, R = 1.5 k 2000 V C PIN Pin capacitance 10 pF DC ELECTRICAL CHARACTERISTICS (Continued) SERCON410B
Figure 5. Timing of Clock MCLK and Related Outputs
3.4 AC ELECTRICAL CHARACTERISTICS
3.4.1 Clock Input MCLK
Figure 6. Timing of Clock SCLK
3.4.2 Clock Input SCLK
Figure 7. Timing of Serial Clock Inputs RxC and TxC and Related Signals
3.4.3 Serial Clock
Figure 8. Timing of Serial Clock Inputs RxC and TxC and Related Signals
3.4.4 Address Latch
Figure 9. Read Access of Control Registers
3.4.5 Read Access of Control Registers
Figure 10. Read Access of Dual Port RAM
3.4.6 Read Access of Dual Port RAM
Figure 11. Write Access to Control Registers
3.4.7 Write Access to Control Registers
Figure 12. Write Access to DUAL Port RAM
3.4.8 Write Access to Dual Port RAM
4 CONTROL REGISTERS AND RAM DATA
4.1 CONTROL REGISTER ADDRESSES
The following table is an overview of the control registers. The address is the word address which is input by A6-1. To calculate the byte address, the value has to be multiplied by two. Thereset val- ues of the control registers are shown inbold. A6-1 Bit Name R/W Value Function 0H 0-15 VERSION R 2 Circuit code (0002H)
0 RSTFL R/W 0
1 SWRST W 0
2 (Not used)
3 REPON R/W 0
4 SREGEN R Level at SREGEN pin
5 REGMODE R/W
Sampling at the middle of bit Sampling according to SERCOS interface specification
6 R/W 0
Baud rate = fSCLK /1 6 Baud rate = fSCLK /3 2
7 POLRXD R/W 0
“Light on” when RxD = 0 “Light on” when RxD = 1
8 PRESYNC R/W 0
9 POLTXD R/W 0
“Light on” when TxD = 0 “Light on” when TxD = 1
10 ENTSBAUD R/W 0
Baud rate selected by SWSBAUD pin Baud rate selected by SWSBAUD control bit
11 SBAUD R Level at pin SBAUD
12 RXDNRZ R/W 0
Receive data is NRZI-coded Receive data is NRZI-coded
13 WRSYNC R/W Direct RAM write access
RAM write access internally synchronized
14 DMAMODE R/W 0
DMAREQR/DMAREQT are static signals DMAREQR/DMAREQT are pulses 15 (Not used) All control registers can be written to and read (R/W), with the exception of the control bits that initiate an action (W). The status registers can only be read (R). When control registers which contain bits that are not used or can only be read, are written to, these bits can be set to 0 or 1; they are not evaluated internally. If control registers are read with bits that are not used, these bits are set to 0. SERCON410B
CONTROL REGISTER ADDRESSES (Continued) A6-1 Bit Name R/W Value Function 0-5 ENTXD1-6 R/W 0 Pin TxDn has a high impedance Pin TxDn is outputting transmit data
6 TXDMODE R/W 0
TxD2-6 is outputting ENTXD2-6 7-9 TMODE0-2 R/W 0-3 4,6 Test functions are controlledvia TM0-1 pins Continuous signal light Zero bit stream Normal operation 10-11 TM0-1 R 0 Level at TM0-1
12 RDIST R 0
Receive data over distortion limit
13 FIBBR R 0
Filler signal or data is received No edges on receive data 14-15 LMODE0-1 R/W L_ERRN active by FIBBR and RDIST L_ERRN active by RDIST L_ERRN active by FIBBR L_ERRN is inactive
0 INTFL0 R 0
1 ENINT0 R/W 0
2 POLINT0 R/W 0
3 INTFL1 R 0
4 ENINT1 R/W 0
5 POLINT1 R/W 0
6 COMACT R 0
No transmission block is processed Transmission block is processed
7 COMBLK R 0
Transmission block 0 is processed Transmission block 1 is processed
8 ENTMT R/W 0
Do not send data telegrams Send data telegrams
9 FLTMT R 0
10 FLRWAIT R 0
Data telegram is not expected Data telegram is expected
11 FLREC R 0
Data telegram is not received Data telegram is received SERCON410B
CONTROL REGISTER ADDRESSES (Continued) A6-1 Bit Name R/W Value Function
12 DMAREQT R 0
DMA request of transmit FIFO inactive DMA request of transmit FIFO active
13 DMAREQR R 0
DMA request of receive FIFO inactive DMA request of receive FIFO active
14 IDLE R Level at IDLE pin
15 RECACTN R Level at RECACTN pin
INT_n R 0 Interrupt event has not occurred Interrupt flag active, interrupt event has occurred CLR_INT_n W 0 Do not modify interrupt flag Clear interrupt flag
0 INT_RDIST R/W Interrupt receive data distorted
1 INT_FIBBR R/W Interrupt no receive data
2 INT_COMBLK0 R/W Interrupt start transmission block 0
3 INT_COMBLK1 R/W Interrupt start transmission block 1
4 INT_COMEND R/W Interrupt end of transmission block
5 INT_PHAS0 R/W Interrupt phase MST = 0.
6 INT_PHASERR R/W Interrupt phase MST errored
7 INT_MSTEARLY R/W Interrupt communication cycle start too early
8 INT_MSTLATE R/W Interrupt communication cycle start too late
9 INT_MSTMISS R/W Interrupt MST missing twice
10 INT_TSTART R/W Interrupt start of transmit telegram
11 INT_TEND R/W Interrupt end of transmit telegram
12 INT_RWAIT R/W Interrupt start waiting for receive telegram
13 INT_RSTART R/W Interrupt start of receive telegram
14 INT_REND R/W Interrupt end of receive telegram
15 INT_RERR R/W Interrupt error of receive telegram
0-7 INT_SC_0-7 R/W Interrupt service container
8 INT_RMISS R/W Interrupt receive telegram missing twice
9-12 INT_TIME0-3 R/W Interrupt time TINT0-3
13 INT_DIVCLK R/W Interrupt DIVCLK signal
14 INT_PROGERR R/W Interrupt programming error
15 INT_NEWADR R/W Interrupt address change
CONTROL REGISTER ADDRESSES (Continued) A6-1 Bit Name R/W Value Function 6H 0-15 EN0_INT_n R/W Interrupt flag does not activate INT0 Interrupt flag activates INT0 Bit assignment same as for address 4H 7H 0-15 EN0_INT_n R/W Interrupt flag does not activate INT0 Interrupt flag activates INT0 Bit assignment same as for address 5H 8H 0-15 EN1_INT_n R/W Interrupt flag does not activate INT1 Interrupt flag activates INT1 Bit assignment same as for address 4H 9H 0-15 EN1_INT_n R/W Interrupt flag does not activate INT1 Interrupt flag activates INT1 Bit assignment same as for address 5H OAH 0-7 PHAS0 R/W Phase for MST transmit (master) or MST receive (slave)(reset value = 0FFH) 8-15 PHAS1 R/W Phase for MST receive (slave) (reset value = 0FFH) OBH 0-7 PHASREC R Phase information of received MST 8-15 RECADR R Address of receive telegram 0CH
0 MSTEN R/W
MST is not transmitted or received MST is transmitted or received (SERCOS interface mode)
1 MSTMASTER R/W
Receive MST (SERCOS interface slave) Transmit and receive MST (SERCOS interface master)
2 COMBLK0 R/W
When phase = PHAS0 transmission block 0 is processed When phase = PHAS0 transmission block 1 is processed
3 COMBLK1 R/W
When phase = PHAS1 transmission block 0 is processed When phase = PHAS1 transmission block 1 is processed
4 CON_CLK R Level at CON_CLK pin
5 ENCONCLK R/W
CON_CLK pin doesn’t become active CON_CLK pin becomes active from TINT0 to TINT1
6 POLCONCLK R/W 0
Signal at CON_CLK is 1-active Signal at CON_CLK is 0-active
7 CYC_CLK R Level at CYC_CLK pin
8 ENCYCCLK R/W
CYC_CLK pin does not trigger timing control CYC_CLK pin triggers timing control after TCYCSTART SERCON410B
CONTROL REGISTER ADDRESSES (Continued) A6-1 Bit Name R/W Value Functio n OCH
9 POLCYCCLK R/W
Timing control triggered by rising edge of CYC_CLK Timing control triggered by falling edge of CYC_CLK
10 CYCSTART W
Trigger timing control after TCYCSTART (master)
11 RDTCNT W 0
12-15 NCYC R/W Number of communcation cycles triggered by CYC_CLK or CYCSTART 0DH 0-7 HS_TIMEOUT R/W Handshake timeout for service channel 8-15 BUSY_TIMEOUT R/W BUSY timeout for service channel 0EH 0-4 MCLKDIV R/W Predivider value: fMCLK/1 MHz - 1 (reset value = 19) 5-7 (Not used) 8-12 MCLKST R/W Initial value for predivider 13-15 (Not used) 0FH 0-15 TSCYC0 R/W SERCOS interface cycle time in•s for transmission block 0 10H 0-15 TSCYC1 R/W SERCOS interface cycle time in•s für transmission block 1 11H 0-15 TCYCDEL R Time at which MST is received, ring delay (master) 12H 0-15 TCNTLT R Stored value of TCNT time counter 13H 0-15 TCNTST R/W Initial value for TCNT time counter 14H 0-15 TCYCSTART R/W Delay in triggering timing control 15H 0-15 JTSCYC1 R/W Receive time window for MST 1 16H 0-15 JTSCYC2 R/W Receive time window for MST 2 17H 0-15 PROGERR_FL R Error flags CLR_PROGERR_FL W Clear error flags 18H 0-15 JTRDEL1 R/W Receive time window for data telegram 1 19H 0-15 JTRDEL2 R/W Receive time window for data telegram 2 1AH 0-15 TINT0 R/W Time at which time interrupt 0 and first edge of CON_CLK occur 1BH 0-15 TINT1 R/W Time at which time interrupt 1 and second edge of CON_CLK occur SERCON410B
CONTROL REGISTER ADDRESSES (Continued) A6-1 Bit Name R/W Value Function 1CH 0-15 TINT2 R/W Time at which time interrupt 2 occurs 1DH 0-15 TINT3 R/W Time at which time interrupt 3 occurs 1EH 0-15 TDIVCLK R/W Time at which the first pulse of DIV_CLK occurs 1FH 0-15 DTDIVCLK R/W DIV_CLK pulse distance 20H 0-7 NDIVCLK R/W Number of DIV_CLK pulses within one communication cycle(reset value =0)
8 POLDIVCLK R/W 0
Pulses from DIV_CLK are 1-active Pulses from DIV_CLK are 0-active 9-15 (Not used) 21H 0-9 THTPT R Internal RAM address of telegram header of transmitted telegram 10-15 (Not used) 22H 0-15 THT R Control word 0 of telegram header of transmitted telegram 23H 0-9 THWPT R Internal RAM address of telegram header of a telegram which is expected 10-15 (Not used) 24H 0-15 THW R Control word 0 of telegram header of telegram which is expected 25H 0-9 THRPT R Internal RAM address of telegram header of received telegram
10 MSTTCHK R/W 0
MST receive time is not checked MST receive time is checked
11 PHAS12 R/W
Operating mode for SERCOS interface phase 1 and 2
12 FLMDTADR R/W
Address of receive telegram different from expected value Address of receive telegram equal to expected value 13-15 (Not used) 26H 0-15 THR R Control word 0 of telegram header of received telegram 27H 0-15 RFIFO R Receive FIFO 0-15 TFIFO W Transmit FIFO SERCON410B
4.2 DATA STRUCTURES WITHIN THE RAM
In this RAM the first eleven words have a fixed meaning. A10-1 Contents 0-1 COMPT0-1: Start of transmission blocks 0-1 2-9 SCPT0-7: Address service containers 0-7
10 NMSTERR: Error counter MST
4.2.1 Telegram Headers
A telegram header for receive telegram contains thefollowing five control words: INDEX Bit Name Function 0-7 ADR Telegram address
8 DMA Data storage in the internal RAM (DMA = 0) or DMA transfer
(DMA = 1)
9 DBUF Data in the RAM: single buffer (DBUF = 0) or double buffer (DBUF
=1 )
10 VAL
For single buffering (DMA = 0, DBUF = 0) or DMA transfer (DMA = 1): telegram data is invalid (VAL = 0) or valid (VAL = 1); for double buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0) or buffer 1 (VAL = 1) is valid. Modified by controller at beginning and end of receive telegrams.
11 ACHK
Telegrams are received if the address is valid (ACHK = 1) or independent on the received address (ACHK = 0). The received address is stored at ADR.
12 TCHK The time of receiving is checked (TCHK = 1) or not checked
(TCHK = 0).
13 RERR The last telegram was free of error (RERR = 0) or errored or not
received (RERR = 1). 14 0 Marker bit for telegram header of receive telegram. 15 0 Marker bit for telegram header. 1 0-15 TRT Time for the start of telegram in µs after end of MST. 2 0-15 TLEN Length of telegram in data words (not including address). 0-9 PT Word address within the RAM of the next telegram header or the end marker. 10-15 (Not used) 4 0-15 NERR Error counter The rest of the RAM can be divided into data structures as required. SERCON410B
A telegram header for transmit telegram comprises four control words: DATA STRUCTURES WITHIN THE RAM (Continued) Index Bit Name Function 0-7 ADR Telegram address 8 DMA Data storage in the RAM (DMA = 0) or DMA transfer (DMA = 1). 9 DBUF Data in RAM: single buffer (DBUF = 0) or double buffer (DBUF = 1).
10 VAL For double buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0)
or buffer 1 (VAL = 1) are valid. Set by processor. 11-12 EN Data telegram is not to be transmitted (EN = 0), transmitted once (EN = 1), continuously (EN = 2) or transmitted only if the previously received telegram contains the expected address (EN = 3) (PHAS12 =1 and FLMDTADR = 1). If EN is 1 the circuit sets EN to 0 after the transmit telegram has been started. 13 (Not used) 14 1 Marker bit for telegram header of transmit telegram. 15 0 Marker bit for telegram header. 1 0-15 TRT Time for the start of telegram in •s after the end of MST. 2 0-15 TLEN Length of the telegram in data words (not including address). 0-9 PT Word address of the next telegram header or the end marker. 10-15 (Not used) SERCON410B
4.2.2 Data Containers
0-9 LEN Number of 16-bit data words of the data block. 10 SVFL Flag, whether data block uses service container (SVFL = 1). 11-13 NSV Number of service container, which is used (0 - 7).
14 SCMASTER Processing of service container in slave mode (SCMASTER = 0)
or master mode (SCMASTER = 1).
15 LASTDC Last data container of the telegram (1) or further data containers
Position of the data block within the telegram in number of words. Figure 13. Structure of Data Containers
4.2.3 End Marker
14 1 Marker bit for the end marker. 15 1 Marker bit for the end marker. 1 0-15 TEND Time after end of MST at which the last telegram has ended (in µs). Figure 14. Structure of Service Container
4.2.4 Service Containers
DATA STRUCTURES WITHIN THE RAM (Continued) Index Bit Name Function
0 HS_MDT Handshake-bit in MDT
1 L/S_MDT Read/write in MDT
2 END_MDT End in MDT
3-5 ELEM_MDT Data element type in MDT
6 SETEND END_MDT is to be set
7 M_BUSY Service container waits for interaction of
microprocessor (M_BUSY = 1) 8-9 NINFO_WRITE Number of info words in write buffer (1 to 4) 10-11 (Not used)
12 INT_ERR Slave reports error
13 INT_END_WRBUF End of write buffer is reached
14 INT_END_RDBUF End of read buffer is reached
15 (Not used)
0 HS_AT Handshake bit in AT
1 BUSY_AT Busy bit in AT
2 ERR_AT Error bit in AT
3 CMD_AT Command modification bit in AT
4-6 (Not used)
7 RECERR Last transmission was correct (0) or errorneous (1)
8-9 NINFO_READ Number of info words in read buffer (1 to 4) 10-15 (Not used) 0-7 WRDATPT Pointer to present position in write buffer 8-15 WRDATLAST Pointer to last position in write buffer 0-7 RDDATPT Pointer to present position in read buffer 8-15 RDDATLAST Pointer to last position in read buffer 0-7 ERR_CNT Error counter
8 BUSY_CNT Error counts differences of handshake (0) or BUSY cycles (1)
9 INT_SC_ERR Interrupt due to protocol error
10 INT_HS_TIMEOUT Interrupt due to handshake timeout
11 IN T_BUSY_ TIMEOUT Interrupt BUSY timeout
12 INT_CMD Slave has set command modification bit
13-15 (Not used) For master mode (SCMASTER = 1) the control words are coded as follows: SERCON410B
DATA STRUCTURES WITHIN THE RAM (Continued) The coding of the five control words depends on the mode of the service channel. Using the slave mode (SCMASTER = 0) they have the following structure: Index Bit Name Function
1 BUSY_AT Busy bit in AT, also waiting for microprocessor interaction
3 Error bit in AT Command modification bit in AT
4-6 ELEM Data element of present transmission
7 L/S Read (0)/write (1) of present transmission
8-9 NINFO_WRITE Number of info words in write buffer (1 to 4) 10-11 (Not used)
12 INT_ELEM_CHANGE Master has modified data element or read/write
15 INT_END_MDT Master reports end via END_MDT-bit
0 HS_MDT Handshake bit in MDT
2 END_MDT End bit in MDT
3-5 ELEM_MDT Data element in MDT 6 (Not used) 8-9 NINFO_READ Number of info words in read buffer (1 to 4) 10-15 (Not used) 0-7 WRDATPT Pointer to present position in write buffer 8-15 WRDATLAST Pointer to last position in write buffer 0-7 RDDATPT Pointer to present position in read buffer 8-15 RDDATLAST Pointer to last position in read buffer 0-8 (Not used) 10-15 (Not used) SERCON410B
5 PACKAGE MECHANICAL DATA
Figure 15. SERCON410B 100 Pin Plastic Quad Flat Pack Package
6 ADDITIONAL SUPPORT AND TOOLS
6.1 SERCOS INTERFACE SPECIFICATION
Fördergemeinschaft SERCOS interface e.V.
6.2 SOFTWARE AND BOARDS FOR THE
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I 2C Components by SGS-THOMSON Microelectronics convey s a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided thatthe system conforms to the I2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. NOTES: SERCON410B