SERCON816 STMICROELECTRONICS | Alldatasheet
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Technical content
Figure 1. SERCON816 Block Diagram
6 Package Mechanical Data:
1 GENERAL DESCRIPTION
operation of distributed control or test equipment (e.g. connection between drives and numeric control). reliable high-speed data transmission with excellent noise immunity. control algorithms. The SERCON816 can be used both for SERCOS interface masters and slaves. Intel or Motorola standards. rial interface operates up to 16 Mbaud without external circuitry. – A dual port RAM (2048 * 16 bit) for control and communication data. The organization of the memory is flexible. transmission of service channel information over several communication cycles is executed automatically. (Fig. 4). The SERCON816 is therefore suitable for a wide range of applications. Remark: The SERCON816 is based on the former SERCON410B SERCOS interface controller. Figure 2. SERCON816 Pin Configuration
80 D12
75 BHEN
70 VSS
65 VDD
60 VSS
55 VDD
51 RDN
50 VSS
45 BUSYN
40 DMAACKRN
35 CON_CLK
31 TM1
2 PIN DESCRIPTION
Table 1. SERCON816 I/O Port Function Summary stored in the address latch with ALEL and ALEH is input via D15-0. 0, ALEL/ALEH have to be connected to VDD. the control registers PCSN0 must equal 0 and PCS1 must equal 1. location by the internal telegram processing. the receive FIFO, DMAREQR becomes inactive. FIFO is read, independent of the levels on A6-1 and the chip select signals. the last write access to the transmit FIFO. on A6-1 and the chip select signals. ADMUX is 1 A15-0 are the outputs of the address latch. (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1). BUSWIDTH 99 I Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). are addressed (high byte first). SERCON410B compatible mode is selected. SBAUD 29 I Baud rate. Can be overwritten by the microprocessor.
RxD 14 I Receive data for the serial interface. TxD1 16 O Transmit data. The pin can be switched to a high impedance state. switched to a high impedance state individually. IDLE 25 O Transmitter active, active low. When transmitting own data IDLE is 0. the last write access to the transmit FIFO. on A6-1 and the chip select signals. ADMUX is 1 A15-0 are the outputs of the address latch. (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1). BUSWIDTH 99 I Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). are addressed (high byte first). SERCON410B compatible mode is selected. SBAUD 29 I Baud rate. Can be overwritten by the microprocessor. RxD 14 I Receive data for the serial interface. TxD1 16 O Transmit data. The pin can be switched to a high impedance state. switched to a high impedance state individually. IDLE 25 O Transmitter active, active low. When transmitting own data IDLE is 0. Table 1. SERCON816 I/O Port Function Summary (continued)
3 ELECTRICAL (DC AND AC) CHARACTERISTICS
3.1 Absolute Maximum Ratings
cycles. The polarity is programmable. repetition rate and polarity are programmable, the pulse width is 1 µs. SCLK 2 I Serial clock for clock regeneration: the maximum frequency is 64 MHz. SCLKO2 6 O Clock output: outputs the SCLK clock divided by 2 or 1. SCLKO4 5 O Clock output: outputs the SCLK clock divided by 4 or 2. RSTN 10 I Reset, active low. Must be zero for at least 50 ns after power on. TEST 7 I Test, active high. Has to be tied to VSS. into a high impedance state. The clocks are turned off and the circuit is reset. For the in-circuit test and for turning on the power-down mode.
3.2 Recommended Operating Conditions
Notes: 1. Only if PLL is used (SBAUD16=0) 2. For normal operation, during testing fMCLK = 0 is possible Symbol Parameter Min. Max. Unit TA Operating temperature -40 85 °C TJ Chip junction temperature -40 125 °C VDD Operating supply voltage 4.75 5.25 V fSCLK Clock frequency SCLK 321 64 MHz fMCLK Clock frequency MCLK 122 64 MHz
3.3 ELECTRICAL CHARACTERISTCS
(VDD = 5V ± 5% Tamb = -40 °C to +85 °C, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit VIL Low level input voltage (TTL) All inputs 0.8 V VIH High level input voltage (TTL) All inputs 2.0 V Vhyst Schmitt trigger hysteresis L_ERRN, TXD6-1, MCLK, SCLK, RSTN, ADMUX, BUSMODE1-0, BUSWIDTH, BYTEDIR, TM1-0, SBAUD16, SBAUD, TEST, OUTZ, RXD, CYC_CLK 0.4 0.7 V I IL Low level input current with pull- up D15-0, A15-0, TXD6-1, ADMUX, BUSMODE1-0, BYTEDIR, TM1- 0, SBAUD16, SBAUD, TEST, OUTZ, RXD, CYC_CLK, BHEN, MCSN1-0, PCSN0, PCS1, DMAACKTN, DMAACKRN V I = VSS -40 -100 -240 µA IIH High level input current with pull- down MCLK, SCLK, RSTN, ALEH, ALEL V I = VDD 40 100 240 µA Rup Equivalent pull-up resistance V I = VSS 23 50 112.5 KOhm Rdn Equivalent pull-down resistance VI = VDD 23 50 112.5 KOhm VOL Low level output voltage, all O- and I/O-pins except TXD6-1, L_ERRN IOI = -4 mA 0.4 V VOH High level output voltage, all O- and I/O-pins except TXD6-1, L_ERRN IOH = +4 mA 2.4 V
Notes: 1. estimated
3.4.1 Power Dissipation Considerations
Most of the current consumed by CMOS devices is alternate current (AC) which is charging and discharg- ing the capacitances of the pins and internal nodes. The current consumption rises with the frequency at which the pins and internal nodes will toggle and with the capacitances connected to the pins of the device: P = f · C · V2 (C=capacitance, V=voltage, f=frequency) For applications which require low power consumption or exceeds the maximum allowed power consump- tion the following is required: – Connect unused pins to pull-up or pull-down resistors – Minimize the capacitive load on the pins – Reduce clock frequency of SCLK and MCLK – Minimize accesses to the internal RAM and control registers The maximum allowed power consumption is limited by the maximum allowed chip junction temperature and by the number of VCC/VDD pins. The chip junction temperature is influenced by the ambient temper- ature and the package thermal resistance. The ambient temperature could be influenced by the applica- tion through a good temperature management like heat sinks or ambient air cooling. VOL Low level output voltage, pins TXD6-1, L_ERRN IOI = -8 mA 0.4 V VOH High level output voltage, pins TXD6-1, L_ERRN IOH = +8 mA 2.4 IOZ Tri-state output leakage V O = 0 V or VDD 1 µA IKLU I/O latch-up current V<V SS V>VDD 200 mA VESD Electrostatic protection Leakage < 1 µA, human body model 2000 V C PIN Pin capacitance 10 pF
3.4 Power Dissipation
(VDD = 5V ± 5% Tamb = -40 °C to +85 °C, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit PD Power dissipation 16 Mbaud, MCLK=64 MHz 8501 mW PDA Maximum allowed power dissipation TA=+85°, no air flow 1000 mW
3.3 ELECTRICAL CHARACTERISTCS (continued)
(VDD = 5V ± 5% Tamb = -40 °C to +85 °C, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit
3.5 AC Electrical Characteristics
3.5.1 Clock Input MCLK
Figure 5. Timing of clock MCLK and related outputs
3.5.2 Clock Input SCLK
Figure 6. Timing of Clock SCLK
3.5.3 Address Latch
Figure 7. Address Latch
3.5.4 Read Access of Control Registers
Figure 8. Read Access of Control Registers
3.5.5 Read Access of Dual Port RAM
Figure 9. Read Access of Dual Port RAM
3.5.6 Write Access to Control Registers
Figure 10. Write Access to Control Registers
3.5.7 Write Access to DUAL Port RAM
Figure 11. Write Access to DUAL Port RAM
4 CONTROL REGISTERS AND RAM DATA STRUCTURES
4.1 Control Register Addresses
The following table is an overview of the control registers. The address is the word address which is input by A6-1. To calculate the byte address, the value has to be multiplied by two. All control registers can be written to and read (R/W), with the exception of the control bits that initiate an action (W). The status registers can only be read (R). When control registers which contain bits that are not used or can only be read, are written to, these bits can be set to 0 or 1; they are not evaluated internally. If control registers are read with bits that are not used, these bits are set to 0.
4.2 Data Structures within the RAM
In this RAM the first eleven words have a fixed meaning. The rest of the RAM can be divided into data structures as required.
4.2.1 Telegram Headers
A telegram header for receive telegram contains the following five control words: A6-1 Bits Name R/W Value Function 00H 0-15 VERSION R 0010H Circuit code ( 0010H ) 01H - 2AH 0-15 Please refer to SERCON816 Reference Guide for a detailed description of the control registers. A10-1 Contents 0-1 COMPT0-1: Start of transmission blocks 0-1 2-9 SCPT0-7: Address service containers 0-7
10 NMSTERR: Error counter MST
0 0-7 ADR Telegram address
8 DMA Data storage in the internal RAM (DMA = 0) or DMA transfer (DMA = 1)
9 DBUF Data in the RAM: single buffer (DBUF = 0) or double buffer (DBUF = 1)
10 VAL For single buffering (DMA = 0, DBUF = 0) or DMA transfer (DMA = 1): telegram data
is invalid (VAL = 0) or valid (VAL = 1); for double buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0) or buffer 1 (VAL = 1) is valid. Modified by controller at beginning and end of receive telegrams.
11 ACHK Telegrams are received if the address is valid (ACHK = 1) or independent on the
received address (ACHK = 0). The received address is stored at ADR. 12 TCHK The time of receiving is checked (TCHK = 1) or not checked (TCHK = 0).
13 RERR The last telegram was free of error (RERR = 0) or errored or not received (RERR =
1). 14 0 Marker bit for telegram header of receive telegram. 15 0 Marker bit for telegram header. 1 0-15 TRT Time for the start of telegram in µs after end of MST. 2 0-15 TLEN Length of telegram in data words (not including address). 3 0-10 PT Word address within the RAM of the next telegram header or the end marker. 9-15 (Not used) 4 0-15 NERR Error counter
4.2.2 Data Containers
Figure 12. Structure of Data Containers 0 0-9 LEN Number of 16-bit data words of the data block. 10 SVFL Flag, whether data block uses service container (SVFL = 1). 11-13 NSV Number of service container, which is used (0 - 7).
14 SCMASTER Processing of service container in slave mode (SCMASTER = 0) or master mode
15 LASTDC Last data container of the telegram (1) or further data containers follow (0). record of a telegram has POS = 0 (only in case of receive telegrams).
4.2.3 End Marker
4.2.4 Service Containers
Figure 13. Structure of Service Container 14 1 Marker bit for the end marker. 15 1 Marker bit for the end marker. 1 0-15 TEND Time after end of MST at which the last telegram has ended (in µs).
For master mode (SCMASTER = 1) the control words are coded as follows: Index Bit Name Function 0 0 HS_MDT Handshake-bit in MDT
1 L/S_MDT Read/write in MDT
2 END_MDT End in MDT
3-5 ELEM_MDT Data element type in MDT
6 SETEND END_MDT is to be set
7 M_BUSY Service container waits for interaction of microprocessor
(M_BUSY = 1) 8-9 NINFO_WRITE Number of info words in write buffer (1 to 4) 10-11 (Not used)
12 INT_ERR Slave reports error
13 INT_END_WRBUF End of write buffer is reached
14 INT_END_RDBUF End of read buffer is reached
15 (Not used) 1 0 HS_AT Handshake bit in AT
1 BUSY_AT Busy bit in AT
2 ERR_AT Error bit in AT
3 CMD_AT Command modification bit in AT
4-6 (Not used)
7 RECERR Last transmission was correct (0) or erroneous (1)
8-9 NINFO_READ Number of info words in read buffer (1 to 4) 10-15 (Not used) 2 0-7 WRDATPT Pointer to present position in write buffer 8-15 WRDATLAST Pointer to last position in write buffer 3 0-7 RDDATPT Pointer to present position in read buffer 8-15 RDDATLAST Pointer to last position in read buffer 4 0-7 ERR_CNT Error counter
8 BUSY_CNT Error counts differences of handshake (0) or BUSY cycles (1)
9 INT_SC_ERR Interrupt due to protocol error
10 INT_HS_TIMEOUT Interrupt due to handshake timeout
11 INT_BUSY_TIMEOUT Interrupt BUSY timeout
12 INT_CMD Slave has set command modification bit
13-15 (Not used)
The coding of the five control words depends on the mode of the service channel. Using the slave mode (SCMASTER = 0) they have the following structure: Index Bit Name Function 0 0 HS_AT Handshake bit in AT
1 BUSY_A T Busy bit in AT, also waiting for microprocessor interaction
4-6 ELEM Data element of present transmission
7 L/S Read (0)/write (1) of present transmission
8-9 NINFO_WRITE Number of info words in write buffer (1 to 4) 10-11 (Not used)
12 INT_ELEM_CHANGE Master has modified data element or read/write
15 INT_END_MDT Master reports end via END_MDT -bit
1 0 HS_MDT Handshake bit in MDT
2 END_MDT End bit in MDT
3-5 ELEM_MDT Data element in MDT 6 (Not used) 8-9 NINFO_READ Number of info words in read buffer (1 to 4) 10-15 (Not used) 2 0-7 WRDA TPT Pointer to present position in write buffer 8-15 WRDATLAST Pointer to last position in write buffer 3 0-7 RDDATPT Pointer to present position in read buffer 8-15 RDDATLAST Pointer to last position in read buffer 4 0-8 (Not used) 10-15 (Not used)
5 ADDITIONAL SPECIFICATIONS, TOOLS AND SUPPORT
5.1 Additional Specifications
Reference Manual SERCON816 The reference manual (160 pages) for the SERCON816 Asic contains a complete and very detailed spec- ification of the SERCON816 Asic, including a description of the pinning of the controller, microprocessor interface, serial interface, telegram processing, master and slave modes, additional modes, control and RAM data structures, programming examples, electrical and mechanical characteristics of the chip, differ- ences between SERCON816 and SERCON410B controller. SERCOS interface specification The SERCOS interface specification (IEC/EN 61491) contains a detailed description of the transfer medi- um and physical layer, data transfer and data link layer, protocol structure and data contents, communi- cation phases, functional handling and error handling, list and description of identifier numbers. I/O functions are described in a separate document.
5.2 Hardware and Software Components
Master and slave routines (driver software) for the SERCON816 controller are available from several sup- pliers world-wide. Furthermore different boards for a wide range of computer interfaces are offered, includ- ing ISA-, VME-, PCI- and PC/104 bus systems.
5.3 Tools
Different development and testing tools are available for SERCOS interface. These tools include bus monitors, configuration and simulation tools, as well as tools for conformance test- ing. For all specification and additional application notes please contact: Interests Group SERCOS interface e. V.
SERCON816 100 PIN PLASTIC QUAD FLAT PACK PACKAGE (PQFP100) PQFP100 DIM. mm inch A 3.40 0.134 A1 0.25 0.010 B 0.22 0.38 0.0087 0.015 C 0.13 0.23 0.005 0.009 D3 18.85 0.742 e 0.65 0.026 E3 12.35 0.486 L1 1.60 0.063 K 0°(min.), 7°(max.) OUTLINE AND MECHANICAL DATA
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