SED1565D2B

SED1565 EPSON | Alldatasheet

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Technical content

Datasheet sections

1. SED1565 Series (Rev. 1.2)

EPSON 8–1 SED1565 Series GENERAL DESCRIPTION The SED1565 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the SED1565 Series contain 65 × 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The SED1565 Series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 × 132 dot display (capable of displaying 8 columns × 4 rows of a 16 × 16 dot kanji font). The SED1567 Series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 × 132 dot display (capable of displaying 8 columns × 2 rows of 16 × 16 dot kanji fonts). Thanks to the built-in 55 common output circuits and 132 segment output circuits, the SED1568* ** is capable of displaying 55 × 132 dots (11 columns × 4 lines using 11 × 12 dots Kanji font) with a single chip. The SED1569 Series chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 × 132 dot display (capable of displaying 11 columns × 4 rows of 11 × 12 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low- power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the SED1565 Series chips can be used to create the lowest power display system with the fewest components for high- performance portable devices.

FEATURES

• Direct display of RAM data through the display data RAM. RAM bit data: “1” Non-illuminated “0” Illuminated (during normal display)
• RAM capacity 65 × 132 = 8580 bits
• Display driver circuits SED1565* **:65 common output and 132 segment outputs SED1566* **:49 common output and 132 segment outputs SED1567* **: 33 common outputs and 132 segment outputs SED1568* **: 55 common outputs and 132 segment outputs SED1569* **: 53 common outputs and 132 segment outputs
• High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported.
• Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set.
• Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.)
• Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power supply can be input externally) High-accuracy voltage adjustment circuit (Thermal gradient –0.05%/°C or –0.2%/°C or external input) V 5 voltage regulator resistors equipped internally, V 1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower.
• CR oscillator circuit equipped internally (external clock can also be input)
• Extremely low power consumption Operating power when the built-in power supply is used (an example) SED1565D 0B 81 µA (VDD – VSS = VDD – VSS2 = /SED1565D BB 3.0 V, Quad voltage, V5 – VDD = – 11.0 V) SED1566D 0B 43 µA (VDD – VSS = VDD – VSS2 = /SED1566D BB 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) SED1567D 0B 29 µA (VDD – VSS = VDD – VSS2 = /SED1567D BB 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) SED1568D 0B /SED1568D BB /SED1569D 0B /SED1569D BB 46µA (VDD – VSS = VDD – VSS2 =

3.0 V, Triple voltage, V5 – VDD = –

8.0 V) Conditions: When all displays are in white and the normal mode is selected (see page 60 *12 for details of the conditions).

• Power supply Operable on the low 1.8 voltage Logic power supply VDD – VSS = 1.8 V to –5.5 V Boost reference voltage: VDD – VSS2 = 1.8 V to –6.0 V Liquid crystal drive power supply: VDD – V5 = –4.5 V to –16.0 V
• Wide range of operating temperatures: –40 to 85°C
• CMOS process
• Shipping forms include bare chip and TCP.
• These chips not designed for resistance to light or resistance to radiation.

8–2 EPSON Series Specifications Product Duty Bias SED Dr COM Dr V REG Temperature Shipping Name Gradient Forms SED1565D 0B 1/65 1/9, 1/7 132 65 –0.05%/ °C Bare Chip/SED1565D BB SED1565T 0* 1/65 1/9, 1/7 132 65 –0.05%/ °C TCP SED1565D 1B 1/65 1/9, 1/7 132 65 –0.2%/ °C Bare Chip * SED1565T1* 1/65 1/9, 1/7 132 65 –0.2%/ °C TCP SED1565D 2B 1/65 1/9, 1/7 132 65 External Input Bare Chip * SED1565T2* 1/65 1/9, 1/7 132 65 External Input TCP SED1566D 0B 1/49 1/8, 1/6 132 49 –0.05%/ °C Bare Chip/SED1566D BB SED1566T 0* 1/49 1/8, 1/6 132 49 –0.05%/ °C TCP SED1566D 1B 1/49 1/8, 1/6 132 49 –0.2%/ °C Bare Chip * SED1566T1* 1/49 1/8, 1/6 132 49 –0.2%/ °C TCP SED1566D 2B 1/49 1/8, 1/6 132 49 External Input Bare Chip * SED1566T2* 1/49 1/8, 1/6 132 49 External Input TCP SED1567D 0B 1/33 1/6, 1/5 132 33 –0.05%/ °C Bare Chip/SED1567D BB SED1567T 0* 1/33 1/6, 1/5 132 33 –0.05%/ °C TCP SED1567D 1B 1/33 1/6, 1/5 132 33 –0.2%/ °C Bare Chip * SED1567T1* 1/33 1/6, 1/5 132 33 –0.2%/ °C TCP SED1567D 2B 1/33 1/6, 1/5 132 33 External Input Bare Chip * SED1567T2* 1/33 1/6, 1/5 132 33 External Input TCP SED1568D 0B 1/55 1/8, 1/6 132 55 –0.05%/ °C Bare Chip/SED1568D BB SED1569D 0B 1/53 1/8, 1/6 132 53 –0.05%/ °C Bare Chip/SED1569D BB * SED1569T0* 1/53 1/8, 1/6 132 53 –0.05%/ °C TCP * : Under development

EPSON 8–3 SED1565 Series VSS VDD VOUT VSS2 VR VRS IRS HPM CAP1+ CAP1– CAP2– CAP2+ CAP3+ FRS CLS Oscillator circuit Display timing generation circuit Line address circuit I/O buffer Page address circuit FR CL DOF M/S CS1 CS2 RD (E) WR (R/W) P/S RES D7 (SI) D6 (SCL) SEG0 SEG131 COM0 COM63 COMS COMS COM DriversSEG Drivers Display data latch circuit Display data RAM 132 x 65 Column address circuit StatusCommand decoder MPU interface Bus holder COM output status select circuit Power supply circuit BLOCK DIAGRAM Example: SED1565***

8–4 EPSON Chip Size 10.82 mm × 2.81 mm Bump Pitch 71 µm (Min.) Bump Size PAD No. 1~24 85 µm × 85 µm PAD No. 25~82 64 µm × 85 µm PAD No. 83~99 85 µm × 85 µm PAD No. 100 85 µm × 73 µm PAD No. 101~133 85 µm × 47 µm PAD No. 134 85 µm × 73 µm PAD No. 135 73 µm × 85 µm PAD No. 136~273 47 µm × 85 µm PAD No. 274 73 µm × 85 µm PAD No. 275 85 µm × 73 µm PAD No. 276~308 85 µm × 47 µm PAD No. 309 85 µm × 73 µm Bump Height 17 µm (Typ.) Chip Thickness 625 µm SED1565 Series (0, 0) 100 99 1 135 274 134 309 275 Die No. D1565D0B PIN DIMENSIONS

EPSON 8–5 SED1565 Series SED1565* ** Pad Center Coordinates PAD PIN XYNo. Name 1 (NC) 4973 1246

2 FRS 4853

3 FR 4734

4 CL 4614

5 DOF 4494

6 TEST0 4375

8 CS1 4136

9 CS2 4016

11 RES 3777

12 A0 3657

14 WR, R/W 3418

15 RD, E 3298

17 D0 3059

18 D1 2940

19 D2 2820

20 D3 2700

21 D4 2581

22 D5 2461

23 D6, SCL 2342

24 D7, SI 2222

25 (NC) 2119 26 V DD 2030

27 V DD 1941

28 V DD 1852

29 V DD 1763

30 V SS 1674

31 V SS 1585

32 V SS 1496

33 V SS2 1407

34 V SS2 1318

35 V SS2 1229

36 V SS2 1140

37 (NC) 1051 38 V OUT 962

39 V OUT 873

40 CAP3– 784

PAD PIN XYNo. Name

41 CAP3– 695 1246

42 (NC) 605

43 CAP1+ 516

44 CAP1+ 427

45 CAP1– 338

46 CAP1– 249

47 CAP2– 160

48 CAP2– 71

49 CAP2+ –18

50 CAP2+ –107

SS –196

52 V SS –285

53 V RS –374

54 V RS –463

55 V DD –552

56 V DD –641

57 V 1 –730

58 V 1 –819

59 V 2 –908

60 V 2 –997

61 (NC) –1086 62 V 3 –1176

63 V 3 –1265

64 V 4 –1354

65 V 4 –1443

66 V 5 –1532

67 V 5 –1621

68 (NC) –1710 69 V R –1799

70 V R –1888

71 V DD –1977

72 V DD –2066

73 TEST1 –2155

74 TEST1 –2244

75 TEST2 –2333

76 TEST2 –2422

77 (NC) –2511

78 TEST3 –2600

79 TEST3 –2689

80 TEST4 –2778

PAD PIN XYNo. Name

81 TEST4 –2867 1246

82 (NC) –2957 83 V DD –3059

84 M/S –3179

85 CLS –3298

SS –3418

87 C86 –3538

88 P/S –3657

DD –3777

90 HPM –3896

91 V SS –4016

92 IRS –4136

DD –4255

94 TEST5 –4375

95 TEST6 –4494

96 TEST7 –4614

97 TEST8 –4734

98 TEST9 –4853

99 (NC) –4973 100 (NC) –5252 1248

101 COM31 1163

102 COM30 1090

103 COM29 1017

104 COM28 945

105 COM27 872

106 COM26 799

107 COM25 727

108 COM24 654

109 COM23 581

110 COM22 509

111 COM21 436

112 COM20 363

113 COM19 291

114 COM18 218

115 COM17 145

116 COM16 73

117 COM15 0

118 COM14 –73

119 COM13 –145

120 COM12 –218

Units: µm

8–6 EPSON PAD PIN XYNo. Name

121 COM11 –5252 –291

122 COM10 –363

123 COM9 –436

124 COM8 –509

125 COM7 –581

126 COM6 –654

127 COM5 –727

128 COM4 –800

129 COM3 –872

130 COM2 –945

131 COM1 –1018

132 COM0 –1090

133 COMS –1163

134 (NC) –1248 135 (NC) –5009 –1246 136 (NC) –4924 137 (NC) –4853 138 (NC) –4781

139 SEG0 –4709

140 SEG1 –4637

141 SEG2 –4565

142 SEG3 –4493

143 SEG4 –4421

144 SEG5 –4349

145 SEG6 –4277

146 SEG7 –4206

147 SEG8 –4134

148 SEG9 –4062

149 SEG10 –3990

150 SEG11 –3918

151 SEG12 –3846

152 SEG13 –3774

153 SEG14 –3702

154 SEG15 –3630

155 SEG16 –3559

156 SEG17 –3487

157 SEG18 –3415

158 SEG19 –3343

159 SEG20 –3271

160 SEG21 –3199

PAD PIN XYNo. Name

161 SEG22 –3127 –1246

162 SEG23 –3055

163 SEG24 –2983

164 SEG25 –2912

165 SEG26 –2840

166 SEG27 –2768

167 SEG28 –2696

168 SEG29 –2624

169 SEG30 –2552

170 SEG31 –2480

171 SEG32 –2408

172 SEG33 –2336

173 SEG34 –2265

174 SEG35 –2193

175 SEG36 –2121

176 SEG37 –2049

177 SEG38 –1977

178 SEG39 –1905

179 SEG40 –1833

180 SEG41 –1761

181 SEG42 –1689

182 SEG43 –1618

183 SEG44 –1546

184 SEG45 –1474

185 SEG46 –1402

186 SEG47 –1330

187 SEG48 –1258

188 SEG49 –1186

189 SEG50 –1114

190 SEG51 –1042

191 SEG52 –971

192 SEG53 –899

193 SEG54 –827

194 SEG55 –755

195 SEG56 –683

196 SEG57 –611

197 SEG58 –539

198 SEG59 –467

199 SEG60 –395

200 SEG61 –324

PAD PIN XYNo. Name

201 SEG62 –252 –1246

202 SEG63 –180

203 SEG64 –108

204 SEG65 –36

205 SEG66 36

206 SEG67 108

207 SEG68 180

208 SEG69 252

209 SEG70 324

210 SEG71 395

211 SEG72 467

212 SEG73 539

213 SEG74 611

214 SEG75 683

215 SEG76 755

216 SEG77 827

217 SEG78 899

218 SEG79 971

219 SEG80 1042

220 SEG81 1114

221 SEG82 1186

222 SEG83 1258

223 SEG84 1330

224 SEG85 1402

225 SEG86 1474

226 SEG87 1546

227 SEG88 1618

228 SEG89 1689

229 SEG90 1761

230 SEG91 1833

231 SEG92 1905

232 SEG93 1977

233 SEG94 2049

234 SEG95 2121

235 SEG96 2193

236 SEG97 2265

237 SEG98 2336

238 SEG99 2408

239 SEG100 2480

240 SEG101 2552

Units: µm

EPSON 8–7 SED1565 Series Units: µm PAD PIN XYNo. Name

241 SEG102 2624 –1246

242 SEG103 2696

243 SEG104 2768

244 SEG105 2840

245 SEG106 2912

246 SEG107 2983

247 SEG108 3055

248 SEG109 3127

249 SEG110 3199

250 SEG111 3271

251 SEG112 3343

252 SEG113 3415

253 SEG114 3487

254 SEG115 3558

255 SEG116 3630

256 SEG117 3702

257 SEG118 3774

258 SEG119 3846

259 SEG120 3918

260 SEG121 3990

261 SEG122 4062

262 SEG123 4134

263 SEG124 4206

264 SEG125 4277

265 SEG126 4349

266 SEG127 4421

267 SEG128 4493

268 SEG129 4565

269 SEG130 4637

270 SEG131 4709

271 (NC) 4781 272 (NC) 4853 273 (NC) 4924 274 (NC) 5009 275 (NC) 5252 –1248

276 COM32 –1163

277 COM33 –1090

278 COM34 –1018

279 COM35 –945

280 COM36 –872

PAD PIN XYNo. Name

281 COM37 5252 –800

282 COM38 –727

283 COM39 –654

284 COM40 –581

285 COM41 –509

286 COM42 –436

287 COM43 –363

288 COM44 –291

289 COM45 –218

290 COM46 –145

291 COM47 –73

292 COM48 0

293 COM49 73

294 COM50 145

295 COM51 218

296 COM52 291

297 COM53 363

298 COM54 436

299 COM55 509

300 COM56 581

301 COM57 654

302 COM58 727

303 COM59 799

304 COM60 872

305 COM61 945

306 COM62 1017

307 COM63 1090

308 COMS 1163

309 (NC) 1248

8–8 EPSON SED1566* ** Pad Center Coordinates PAD PIN XYNo. Name 1 (NC) 4973 1246 25 (NC) 2119 26 V DD 2030 37 (NC) 1051 38 V OUT 962 PAD PIN XYNo. Name 42 (NC) 605 SS –196 61 (NC) –1086 62 V 3 –1176 68 (NC) –1710 69 V R –1799 77 (NC) –2511 PAD PIN XYNo. Name 82 (NC) –2957 83 V DD –3059 SS –3418 DD –3777 DD –4255 99 (NC) –4973 100 (NC) –5252 1248 101 (NC) 1163 102 (NC) 1090

103 COM23 1017

104 (NC) 945

105 COM22 872

106 (NC) 799

107 COM21 727

108 COM20 654

109 COM19 581

110 COM18 509

111 COM17 436

112 COM16 363

113 COM15 291

114 COM14 218

115 COM13 145

116 COM12 73

117 COM11 0

118 COM10 –73

119 COM9 –145

120 COM8 –218

Units: µm

EPSON 8–9 SED1565 Series PAD PIN XYNo. Name

121 COM7 –5252 –291

122 COM6 –363

123 COM5 –436

124 COM4 –509

125 COM3 –581

126 COM2 –654

127 COM1 –727

128 (NC) –800

129 COM0 –872

130 (NC) –945

131 COMS –1018

132 (NC) –1090 133 (NC) –1163 134 (NC) –1248 135 (NC) –5009 –1246 136 (NC) –4924 137 (NC) –4853 138 (NC) –4781 PAD PIN XYNo. Name PAD PIN XYNo. Name Units: µm

8–10 EPSON Units: µm PAD PIN XYNo. Name 271 (NC) 4781 272 (NC) 4853 273 (NC) 4924 274 (NC) 5009 275 (NC) 5252 –1248 276 (NC) –1163 277 (NC) –1090

278 COM24 –1018

279 (NC) –945

280 COM25 –872

PAD PIN XYNo. Name 281 (NC) 5252 –800

282 COM26 –727

283 COM27 –654

284 COM28 –581

285 COM29 –509

286 COM30 –436

287 COM31 –363

288 COM32 –291

289 COM33 –218

290 COM34 –145

291 COM35 –73

292 COM36 0

293 COM37 73

294 COM38 145

295 COM39 218

296 COM40 291

297 COM41 363

298 COM42 436

299 COM43 509

300 COM44 581

301 COM45 654

302 COM46 727

303 (NC) 799

304 COM47 872

305 (NC) 945

306 COMS 1017

307 (NC) 1090 308 (NC) 1163 309 (NC) 1248

EPSON 8–11 SED1565 Series PAD PIN XYNo. Name 1 (NC) 4973 1246 25 (NC) 2119 26 V DD 2030 37 (NC) 1051 38 V OUT 962 PAD PIN XYNo. Name 42 (NC) 605 SS –196 61 (NC) –1086

62 V 3 –1176

68 (NC) –1710

69 V R –1799

77 (NC) –2511 PAD PIN XYNo. Name 82 (NC) –2957 83 V DD –3059 SS –3418 DD –3777 DD –4255 99 (NC) –4973 100 (NC) –5252 1248

101 COM15 1163

102 COM15 1090

103 COM14 1017

104 COM14 945

105 COM13 872

106 COM13 799

107 COM12 727

108 COM12 654

109 COM11 581

110 COM11 509

111 COM10 436

112 COM10 363

113 COM9 291

114 COM9 218

115 COM8 145

116 COM8 73

117 COM7 0

118 COM7 –73

119 COM6 –145

120 COM6 –218

SED1567* ** Pad Center Coordinates Units: µm

8–12 EPSON PAD PIN XYNo. Name

121 COM5 –5252 –291

122 COM5 –363

123 COM4 –436

126 COM3 –654

127 COM2 –727

128 COM2 –800

129 COM1 –872

130 COM1 –945

131 COM0 –1018

134 (NC) –1248 135 (NC) –5009 –1246 136 (NC) –4924 137 (NC) –4853 138 (NC) –4781 PAD PIN XYNo. Name PAD PIN XYNo. Name Units: µm

EPSON 8–13 SED1565 Series PAD PIN XYNo. Name 271 (NC) 4781 272 (NC) 4853 273 (NC) 4924 274 (NC) 5009 275 (NC) 5252 –1248

276 COM16 –1163

277 COM16 –1090

278 COM17 –1018

279 COM17 –945

280 COM18 –872

PAD PIN XYNo. Name

281 COM18 5252 –800

282 COM19 –727

283 COM19 –654

284 COM20 –581

285 COM20 –509

286 COM21 –436

287 COM21 –363

288 COM22 –291

289 COM22 –218

290 COM23 –145

291 COM23 –73

292 COM24 0

293 COM24 73

294 COM25 145

295 COM25 218

296 COM26 291

297 COM26 363

298 COM27 436

299 COM27 509

300 COM28 581

301 COM28 654

302 COM29 727

303 COM29 799

304 COM30 872

305 COM30 945

306 COM31 1017

307 COM31 1090

309 (NC) 1248 Units: µm

8–14 EPSON SED1568* ** Pad Center Coordinates Units: µm PAD PIN XYNo. Name 1 (NC) 4973 1246 25 (NC) 2119 26 V DD 2030 37 (NC) 1051 38 V OUT 962 PAD PIN XYNo. Name 42 (NC) 605 SS –196 61 (NC) –1086 62 V 3 –1176 68 (NC) –1710 69 V R –1799 77 (NC) –2511 PAD PIN XYNo. Name 82 (NC) –2957 83 V DD –3059 SS –3418 DD –3777 SS –4016

93 V DD –4255

99 (NC) –4973 100 (NC) –5252 1248 101 (NC) 1163

102 COM26 1090

103 (NC) 1017

104 COM25 945

105 COM25 872

106 COM23 799

107 COM22 727

108 COM21 654

109 COM20 581

110 COM19 509

111 COM18 436

112 COM17 363

113 COM16 291

114 COM15 218

115 COM14 145

116 COM13 73

117 COM12 0

118 COM11 –73

119 COM10 –145

120 COM9 –218

EPSON 8–15 SED1565 Series PAD PIN XYNo. Name

121 COM8 –5252 –291

122 COM7 –363

123 COM6 –436

124 COM5 –509

125 COM4 –581

128 COM1 –800

129 (NC) –872

130 COM0 –945

131 (NC) –1018

132 COMS –1090

133 (NC) –1163 134 (NC) –1248 135 (NC) –5009 –1246 136 (NC) –4924 137 (NC) –4853 138 (NC) –4781 PAD PIN XYNo. Name PAD PIN XYNo. Name Units: µm

8–16 EPSON PAD PIN XYNo. Name 271 (NC) 4781 272 (NC) 4853 273 (NC) 4924 274 (NC) 5009 275 (NC) 5252 –1248 276 (NC) –1163

277 COM27 –1090

278 (NC) –1018

279 COM28 –945

280 (NC) –872 PAD PIN XYNo. Name

281 COM29 5252 –800

282 COM30 –727

283 COM31 –654

284 COM32 –581

285 COM33 –509

286 COM34 –436

287 COM35 –363

288 COM36 –291

289 COM37 –218

290 COM38 –145

291 COM39 –73

292 COM40 0

293 COM41 73

294 COM42 145

295 COM43 218

296 COM44 291

297 COM45 363

298 COM46 436

299 COM47 509

300 COM48 581

301 COM48 654

302 COM50 727

303 COM51 799

304 COM52 872

305 COM53 945

306 (NC) 1017

307 COMS 1090

308 (NC) 1163 309 (NC) 1248 Units: µm

EPSON 8–17 SED1565 Series PAD PIN XYNo. Name 1 (NC) 4973 1246 25 (NC) 2119 26 V DD 2030 37 (NC) 1051 38 V OUT 962 PAD PIN XYNo. Name 42 (NC) 605 SS –196 61 (NC) –1086 68 (NC) –1710 77 (NC) –2511 PAD PIN XYNo. Name 82 (NC) –2957 83 V DD –3059 SS –3418 DD –3777 DD –4255 99 (NC) –4973 100 (NC) –5252 1248 101 (NC) 1163

102 COM25 1090

103 (NC) 1017

104 COM24 945

105 (NC) 872 SED1569* ** Pad Center Coordinates Units: µm

8–18 EPSON PAD PIN XYNo. Name 129 (NC) –872 131 (NC) –1018 133 (NC) –1163 134 (NC) –1248 135 (NC) –5009 –1246 136 (NC) –4924 137 (NC) –4853 138 (NC) –4781 PAD PIN XYNo. Name PAD PIN XYNo. Name Units: µm

EPSON 8–19 SED1565 Series PAD PIN XYNo. Name 271 (NC) 4781 272 (NC) 4853 273 (NC) 4924 274 (NC) 5009 275 (NC) 5252 –1248 276 (NC) –1163

277 COM26 –1090

278 (NC) –1018

279 COM27 –945

280 (NC) –872 PAD PIN XYNo. Name

281 COM28 5252 –800

282 COM29 –727

283 COM30 –654

284 COM31 –581

285 COM32 –509

286 COM33 –436

287 COM34 –363

288 COM35 –291

289 COM36 –218

290 COM37 –145

291 COM38 –73

292 COM39 0

293 COM40 73

294 COM41 145

295 COM42 218

296 COM43 291

297 COM44 363

298 COM45 436

299 COM46 509

300 COM47 581

302 COM49 727

303 COM50 799

304 (NC) 872

305 COM51 945

306 (NC) 1017 308 (NC) 1163 309 (NC) 1248 Units: µm

8–20 EPSON PIN DESCRIPTIONS Power Supply Pins Pin Name I/O Function No. of Pins VDD Power Shared with the MPU power supply terminal VCC .1 3 Supply VSS Power This is a 0V terminal connected to the system GND. 9 Supply VSS2 Power This is the reference power supply for the step-up voltage circuit for the 4 Supply liquid crystal drive. VRS Power This is the externally-input VREG power supply for the LCD power supply 2 Supply voltage regulator. These are only enabled for the models with the VREG external input option. V1, V2, Power This is a multi-level power supply for the liquid crystal drive. The voltage 10 V3, V4, Supply applied is determined by the liquid crystal cell, and is changed through the V5 use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. V DD (= V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 Master operation: When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. LCD Power Supply Circuit Terminals Pin Name I/O Function No. of Pins CAP1+ O DC/DC voltage converter. Connect a capacitor between this terminal and 2 the CAP1- terminal. CAP1– O DC/DC voltage converter. Connect a capacitor between this terminal and 2 the CAP1+ terminal. CAP2+ O DC/DC voltage converter. Connect a capacitor between this terminal and 2 the CAP2- terminal. CAP2– O DC/DC voltage converter. Connect a capacitor between this terminal and 2 the CAP2+ terminal. CAP3– O DC/DC voltage converter. Connect a capacitor between this terminal and 2 the CAP1+ terminal. VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and 2 VSS . VR I Output voltage regulator terminal. Provides the voltage between VDD and 2 V5 through a resistive voltage divider. These are only enabled when the V5 voltage regulator internal resistors are not used (IRS = “L”). These cannot be used when the V 5 voltage regulator internal resistors are used (IRS = “H”).

EPSON 8–21 SED1565 Series System Bus Connection Terminals Pin Name I/O Function No. of Pins D7 to D0 I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit 8 standard MPU data bus. (SI) When the serial interface is selected (P/S = “L”), then D7 serves as the (SCL) serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. A0 I This is connect to the least significant bit of the normal MPU address bus, 1 and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data. RES I When RES is set to “L,” the settings are initialized. 1 The reset operation is performed by the RES signal level. CS1 I This is the chip select signal. When CS1 = “L” and CS2 = “H,” then the 2 CS2 chip select becomes active, and data/command I/O is enabled. RD I • When connected to an 8080 MPU, this is active LOW. 1 (E) This pin is connected to the RD signal of the 8080 MPU, and the SED1565 series data bus is in an output status when this signal is “L”.

• When connected to a 6800 Series MPU, this is active HIGH. This is the 68000 Series MPU enable clock input terminal. WR I • When connected to an 8080 MPU, this is active LOW. 1 (R/W) This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal.
• When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. C86 I This is the MPU interface switch terminal. 1 C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface. P/S I This is the parallel data input/serial data input switch terminal. 1 P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status: When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open. RD (E) and WR (P/W) are fixed to either “H” or “L”. With serial data input, RAM display data reading is not supported. P/S Data/Command Data Read/Write Serial Clock “H” A0 D0 to D7 RD, WR “L” A0 SI (D7) Write only SCL (D6)

8–22 EPSON Pin Name I/O Function No. of Pins CLS I Terminal to select whether or enable or disable the display clock internal 1 oscillator circuit. CLS = “H”: Internal oscillator circuit is enabled CLS = “L”: Internal oscillator circuit is disabled (requires external input) When CLS = “L”, input the display clock through the CL terminal. M/S I This terminal selects the master/slave operation for the SED1565 Series 1 chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. M/S = “H”: Master operation M/S = “L”: Slave operation The following is true depending on the M/S and CLS status: CL I/O This is the display clock input terminal 1 The following is true depending on the M/S and CLS status. When the SED1565 Series chips are used in master/slave mode, the various CL terminals must be connected. FR I/O This is the liquid crystal alternating current signal I/O terminal. 1 M/S = “H”: Output M/S = “L”: Input When the SED1565 Series chip is used in master/slave mode, the various FR terminals must be connected. DOF I/O This is the liquid crystal display blanking control terminal. 1 M/S = “H”: Output M/S = “L”: Input When the SED1565 Series chip is used in master/slave mode, the various DOF terminals must be connected. FRS O This is the output terminal for the static drive. 1 This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. IRS I This terminal selects the resistors for the V5 voltage level adjustment. 1 IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either “H” or “L” when the slave operation mode is selected. HPM I This is the power control terminal for the power supply circuit for liquid 1 crystal drive. HPM = “H”: Normal mode HPM = “L”: High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either “H” or “L” when the slave operation mode is selected. Oscillator Power M/S CLS Circuit Supply CL FR FRS DOF Circuit “H” “H” Enabled Enabled Output Output Output Output “L” Disabled Enabled Input Output Output Output “L” “H” Disabled Disabled Input Input Output Input “L” Disabled Disabled Input Input Output Input M/S CLS CL “H” “H” Output “L” Input “L” “H” Input “L” Input

EPSON 8–23 SED1565 Series Pin Name I/O Function No. of Pins SEG0 O These are the liquid crystal segment drive outputs. Through a combination 132 to of the contents of the display RAM and with the FR signal, a single level is SEG131 selected from V DD , V2, V3, and V5. COM0 O These are the liquid crystal common drive outputs. to COMn Through a combination of the contents of the scan data and with the FR signal, a single level is selected from V DD , V1, V4, and V5. COMS O These are the COM output terminals for the indicator. Both terminals 2 output the same signal. Leave these open if they are not used. When in master/slave mode, the same signal is output by both master and slave. Liquid Crystal Drive Terminals RAM DATA FR Output Voltage Normal Display Reverse Display HH V DD V2 HL V 5 V3 LH V 2 VDD LL V 3 V5 Power save — V DD Scan Data FR Output Voltage HH V 5 HL V DD LH V 1 LL V 4 Power Save — V DD Test Terminals Pin Name I/O Function No. of Pins TEST0 to 4 I/O These are terminals for IC chip testing. 12 TEST7 to 9 They are set to OPEN. TEST5, 6 I These are terminals for IC chip testing. 2 They are set to VDD . Total: 288 pins for the SED1565*. 272 pins for the SED1566*. 256 pins for the SED1567***. Part No. COM SED1565* ** COM 0 ~ COM 63 SED1566* ** COM 0 ~ COM 47 SED1567* ** COM 0 ~ COM 31 SED1568* ** COM 0 ~ COM 53 SED1569* ** COM 0 ~ COM 51 Part No. SED1565* ** 64 SED1566* ** 48 SED1567* ** 32 SED1568* ** 54 SED1569* ** 52

8–24 EPSON DESCRIPTION OF FUNCTIONS The MPU Interface Selecting the Interface Type With the SED1565 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. The Parallel Interface When the parallel interface has been selected (P/S = “H”), then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Moreover, data bus signals are recognized by a combination of A0, RD (E), WR (R/W) signals, as shown in Table 3. Table 3 Shared 6800 Series 8080 Series FunctionA0 R/W RD WR 1 1 0 1 Reads the display data 1 0 1 0 Writes the display data 0 1 0 1 Status read 0 0 1 0 Write control data (command) Table 2 P/S CS1 CS2 A0 RD WR D7~D0 H: 6800 Series MPU Bus CS1 CS2 A0 E R/W D7~D0 L: 8080 MPU Bus CS1 CS2 A0 RD WR D7~D0 Table 1 P/S CS1 CS2 A0 RD WR C86 D7 D6 D5~D0 H: Parallel Input CS1 CS2 A0 RD WR C86 D7 D6 D5~D0 L: Serial Input CS1 CS2 A0 — — — SI SCL (HZ) “—” indicates fixed to either “H” or to “L”

8–26 EPSON The Busy Flag When the busy flag is “1” it indicates that the SED1565 Series chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the N N N+1 N+2 N+3 N+1 N+2 N+3 WR MPUInternal Timing DATA Latch BUS Holder Write Signal N N n n+1 N+2Increment N+1Preset N N n n+1 n+2 Data Read #n+1 Data Read Dummy Read Address Set Internal Timing WR RD DATA Address Preset Read Signal Column Address Bus Holder MPU Writing Reading read instruction. If the cycle time (tCYC ) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Figure 2

EPSON 8–27 SED1565 Series Display data RAM COM0 COM1 COM2 COM3 COM4 Liquid crystal display Display Data RAM Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page x 8 bit +1) x 132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple SED1565 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). Table 4 SEG SEG0 SEG 131 Output ADC “0” 0 (H) → Column Address → 83 (H) (D0) “1” 83 (H) ← Column Address ← 0 (H) Figure 3 The Page Address Circuit As shown in Figure 6-4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used. The Column Addresses As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementation of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for SED1565 Series, COM47 output for SED1566 Series and COM31 output for the SED1567 Series when the common output mode is reversed. The display area is a 65 line area for the SED1565 Series, a 49 line are for the SED1566 and a 33 line area for the SED1567 Series from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.

8–28 EPSON 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 11H 12H 13H 14H 15H 16H 17H 18H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7

1000 Page 8

D0Regardless of the display start line address, the SED1565 Series accesses 65th line, the SED1566 Series accesses 49th line and the SED1567 Series accesses 33th line and the SED1568 Series accesses 55th line, the SED1569 Series accesses 53 lines. Start 63 lines 52 lines 48 lines Page Address D3 D2 D1 D0 Data Line Address COM Output When the common output mode is normal 32 lines 54 lines Figure 4

EPSON 8–29 SED1565 Series The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/ OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = “H” and CLS = “H”. When CLS = “L” the oscillation stops, and the display clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Figure 5 CL FR COM0 VDD VDD VDD COM1 RAM DATA SEGn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 Two-frame alternating current drive wave form (SED1565***)

8–30 EPSON When multiple SED1565 Series chips are used, the slave chips must be supplied the display timing signals (FR, CL, DOF) from the master chip[s]. Table 5 shows the status of the FR, CL, and DOF signals. Table 5 Operating Mode FR CL DOF Master (M/S = “H”) The internal oscillator circuit is enabled (CLS = “H”) Output Output Output The internal oscillator circuit is disabled (CLS = “L”) Output Input Output Slave (M/S = “L”) The internal oscillator circuit is enabled (CLS = “H”) Input Input Input The internal oscillator circuit is disabled (CLS = “L”) Input Input Input The Common Output Status Select Circuit In the SED1565 Series chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. The Liquid Crystal Driver Circuits These are a 197-channel (SED1565 Series), a 181- channel (SED1566 Series) multiplexers 165-channel (SED1567 Series) and a 185-channel (SED1569 Series) that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form. Table 6 Status COM Scan Direction Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51 Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0

EPSON 8–31 SED1565 Series Figure 6 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 FR COM0 COM1 COM2 SEG0 SEG1 SEG2 COM0–SEG0 COM0–SEG1 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 VDD VDD VDD VDD –V3 –V4 –V5 –V1 –V2 –V3 –V4 –V5 –V1 –V2 VDD VDD VDD VSS

8–32 EPSON The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON of OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 The Control Details of Each Bit of the Power Control Set Command Item Status “1” “0” D2 Booster circuit control bit ON OFF D1 Voltage regulator circuit (V regulator circuit) control bit ON OFF D0 Voltage follower circuit (V/F circuit) control bit ON OFF Table 8 Reference Combinations V External Step-up Use Settings D2 D1 D0 Step-up regulatorV/F voltage voltage circuit circuit circuit input system terminal

1 Only the internal power supply is 1 1 1 O O O V SS2 Used

2 Only the V regulator circuit and 0 1 1 X O O V OUT , VSS2 Open

3 Only the V/F circuit is used 0 0 1 X X O V 5, VSS2 Open

4 Only the external power supply is 0 0 0 X X X V 1 to V5 Open

• The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the SED1565 Series chips it is possible to product a Quad step-up, a Triple step-up, and a Double step-up of the V DD – VSS2 voltage levels. Quad step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between V SS2 and VOUT , to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between V DD and VSS2 . Triple step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and between VSS2 and VOUT , and short between CAP3– and V OUT to produce a voltage level in the negative direction at the V OUT terminal that is 3 times the voltage difference between VDD and VSS2 . Double step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and V OUT , leave CAP2+ open, and short between CAP2–, CAP3– and V OUT to produce a voltage in the negative direction at the VOUT terminal that is twice the voltage between VDD and VSS2 . The step-up voltage relationships are shown in Figure 7.

EPSON 8–33 SED1565 Series VSS2 VOUT CAP3– CAP1+ CAP1– CAP2– CAP2+ SED1565 Series 4 x step-up voltage circuit 3 x step-up voltage circuit 2 x step-up voltage circuit VSS2 VOUT CAP3– CAP1+ CAP1– CAP2– CAP2+ SED1565 Series VSS2 VOUT CAP3– CAP1+ CAP1– CAP2– CAP2+OPEN SED1565 Series VDD = 0V VSS2 = –3V VOUT = 4 x VSS2 = –12V 4x step-up voltage relationships VDD = 0V VSS2 = –3V VOUT = 3 x VSS2 = –9V 3x step-up voltage relationships VDD = 0V VSS2 = –5V VOUT = 2 x VSS2 = –10V 2x step-up voltage relationships (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V 5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V 5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |. The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the liquid crystal driver voltage V5 through the voltage regulator circuit. Because the SED1565 Series chips have an internal high-accuracy fixed voltage power supply with a 64- level electronic volume function and internal resistors for the V 5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the SED1565 Series, three types of thermal gradients have been prepared as V REG options: (1) approximately -0.05%/°C (2) approximately -0.2%/°C, and (3) external input (supplied to the VRS terminal). Figure 7 * The V SS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value.

8–34 EPSON Figure 8 Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V voltage regulator internal resistor ratio register. α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Table 9 Equipment Type Thermal Gradient Units V REG Units (1) Internal Power Supply –0.05 [%/ °C ] –2.1 [V] (2) Internal Power Supply –0.2 [%/ °C ] –4.9 [V] (3) External Input — — V RS [V] Table 10 D5 D4 D3 D2 D1 D0 α 000000 6 3 000001 6 2 000010 6 1.... 111101 2 111110 1 111111 0 VEV (constant voltage supply + electronic volume) Internal Ra Internal Rb VDD (Equation A-1) V REG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9. V Rb Ra V Rb Ra V VV EV REG EV REG 5 1 11 162 1 162 =+  ⋅ =+  ⋅  ⋅ =−() ⋅[] ± α αQ∴

EPSON 8–35 SED1565 Series Table 11 Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input (1) –0.05 (2) –0.2 (3) VREG External Input V 5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Figs. 9, 10, 11 (for SED1565 Series), 12, 13, 14 (for SED1566 Series) and Figs. 15, 16, 17 show V 5 voltage measured by values of the internal resistance ratio resistor for V 5 voltage adjustment and electric volume resister for each temperature grade model, when Ta = 25 °C. Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input –0.05 0 0 0 3.0 1.3 1.5 3 0 0 1 3.5 1.5 2.0 3.5 0 1 0 4.0 1.8 2.5 4 0 1 1 4.5 2.0 3.0 4.5 1 0 0 5.0 2.3 3.5 5 1 0 1 5.4 2.5 4.0 5.4 1 1 0 5.9 2.8 4.5 5.9 1 1 1 6.4 3.0 5.0 6.4

EPSON 8–41 SED1565 Series SED1569D 0B /SED1569D BB Figure 19: SED1569D0B /SED1569D BB (Temperature Gradient = –0.05%/°C Model The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 –12 –11 –10 V5 [v] 00H 18H 30H 3FH Electric Volume Resister The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Setup example: When selecting Ta = 25°C and V5 = 7 V for an SED1567 model on which Temperature gradient = –0.05%/°C. Using Figure 15 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V 5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 Contents Register D5 D4 D3 D2 D1 D0 For V5 voltage — — — 0 1 0 regulator Electronic Volume 1 0 0101 Table 13 V5 Min Typ Max Units Variable Range –8.4 (63 levels) –6.8 (central value) –5.1 (0 level) [V] Notch width 51 [mV]

8–42 EPSON V Rb Ra V Rb Ra V VV EV REG EV REG 5 1 11 162 1 162 =+  ⋅ =+  ⋅  ⋅ =−() ⋅[] © ± α αQ ( Equation B-1) Figure 20 VEV (fixed voltage power supply + electronic volume) External resistor Ra' + External resistor Rb' VDD (B) When an External Resistance is Used (i.e., The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V 5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between VDD and VR , and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V 5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. Setup example: When selecting Ta = 25°C and V 5 = –

7 V for an SED1567 Series model where the temperature

gradient = –0.05%/°C. When the central value of the electron volume register = 31 and V REG = –2.1 V so, according to equation B-1, V Rb Ra V V Rb Ra REG5 11 162 11 1 1 31 162 21 =+ ⋅− −= +  ⋅− ⋅−() © . α (Equation B-2) Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 µA, Ra Rb M©© .+= 14 Ω (Equation B-3) Consequently, by equations B-2 and B-3, Rb Ra Ra k Rb k © . 31 2 340 1060 At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Table 14 V5 Min Typ Max Units Variable Range –8.6 (63 levels) –7.0 (central value) –5.3 (0 level) [V] Notch width 52 [mV]

EPSON 8–43 SED1565 Series V RR R RR V RR R RR V VV EV REG EV REG 32 2 32 2 11 162 1 162 =+ +−  ⋅ =+ +− Δ  ⋅  ⋅ =−() ⋅[] Δ ± α αQ (Equation C-1) Figure 21 VEV (fixed voltage supply + electronic volume) External resistor R1 ΔR 2External resistor R2 VR External resistor R VDD Rb' Ra' (C) When External Resistors are Used (i.e. The V5 Voltage Regulator Internal Resistors Are Not Used). (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V 5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments (Δ R2). Setup example: When selecting Ta = 25°C and V5 = – 5 to –9 V (using R2) for an SED1567 model where the temperature gradient = –0.05%/°C. When the central value for the electronic volume register α = 21VVREG . so, according to equation C-1, when Δ R2 = 0 Ω , in order to make V5 = –9 V, −=+ +  ⋅−()91 1 31 162 2132 V RR R . (Equation C-2) When Δ R2 = R2, in order to make V = –5 V, −=+ +  ⋅−()51 1 31 162 213 V R RR . (Equation C-3) Moreover, when the current flowing VDD and V5 is set to 5 µA, RR R M123 14++= Ω . (Equation C-4) With this, according to equation C-2, C-3 and C-4, Rk Rk Rk 264 211 925 At this time, the V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Table 15 V5 Min Typ Max Units Variable Range –8.7 (63 levels) –7.0 (central value) –5.3 (0 level) [V] Notch width 53 [mV]

8–44 EPSON Sequence Step1 Step2 End Details (Command, status) Display OFF Display all points ON Internal power supply OFF Command address Power saver commands (compound) High Power Mode The power supply circuit equipped in the SED1565 Series chips has very low power consumption (normal mode: HPM = “H”). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to “L” (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure 22 is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply OFF. * When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from V OUT when the Booster circuit is OFF. * The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”). When the V 5 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. The Liquid Crystal Voltage Generator Circuit The V 5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V 3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for SED1565 Series, 1/8 bias or 1/6 bias for SED1566 Series and 1/6 bias or 1/5 bias for the SED1567 Series can be selected. Figure 22

EPSON 8–45 SED1565 Series VDD VDD VDD VSS C 1 VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S C 1 C 1 C 1 C 2 C 2 C 2 C 2 C 2 SED1565 Series VDD VSS C 1 VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S C 1 C 1 C 1 R 3 R 2 R 1 C 2 C 2 C 2 C 2 C 2 SED1565 Series (1) When the voltage regulator internal resistor is used. (Example where V SS2 = VSS , with 4x step-up) (2) When the voltage regulator internal resistor is not used. (Example where V SS2 = VSS , with 4x step-up) À When used all of the step-up circuit, voltage regulating circuit and V/F circuit VDD VDD VSS External power supply VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S C 2 C 2 C 2 C 2 C 2 SED1565 Series VDD VDD VSS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S R 3 R 2 R 1 C 2 C 2 C 2 C 2 C 2 SED1565 Series \` When the voltage regulator circuit and V/F circuit alone are used (1) When the V 5 voltage regulator internal resistor is not used. (2) When the V5 voltage regulator internal resistor is used. External power supply Reference Circuit Examples Figure 22 shows reference circuit examples.

8–46 EPSON Figure 23 * 1 Because the VR terminal input impedance is high, use short leads and shielded lines. * 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings:

• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1. VDD VDD External power supply VSS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S SED1565 Series ˆ When the built-in power is not used VDD VDD VSS External power supply VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V VR VDD IRS M/S C 2 C 2 C 2 C 2 C 2 SED1565 Series ´ When the V/F circuit alone is used Examples of shared reference settings When V 5 can vary between –8 and 12 V Item Set value Units C 1 1.0 to 4.7 µF C 2 0.01 to 1.0 µF VDD , V0 R 4 R 4 R 4 R 4 C 2 SED1565 Series Reference set value R4: 100KΩ ~ 1MΩ It is recommended to set an optimum resistance value R 4 taking the liquid crystal display and the drive waveform.

5 When the built-in power circuit is used to drive a

liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V 1, V2, V3 and V4 which are output from the built-in voltage follower.

EPSON 8–47 SED1565 Series The Reset Circuit When the RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: SED1565* 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”) 8. Power saving clear 9. V 5 voltage regulator internal resistors Ra and Rb separation (In case of SED1565D BB , SED1566D BB , SED1567D BB , SED1568D BB and SED1569D BB , internal resistors are connected while RES is “L.”) 10. Output conditions of SEG and COM terminals SEG : V2/V3, COM : V1/V4 (In case of SED1565D BB , SED1566D BB , SED1567D BB , SED1568D BB and SED1569D BB , both the SEG terminal and the COM terminal output the VDA level while RES is “L.” In case of other models, the SEG terminal outputs V 2 and the COM terminal outputs V1 while RES is “L.”) 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V 5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an overcurrent may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on SED1565D BB , SED1566D BB , SED1567D BB , SED1568D BB and SED1569D BB , it is necessary that RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when RES is “L,” and the external power supply short-circuits to VDD when RES is “L.” While RES is “L,” the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The V DD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between V DD and V5. When the internal liquid crystal power supply circuit is not used on other models of SED1565 series, it is necessary that RE is “L” when the external liquid crystal power supply is turned on. While RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected.

8–48 EPSON COMMANDS The SED1565 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/ W terminal and then the command is launched by inputting a high pulse to the E terminal. (See “10. Timing Characteristics” regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands> Display ON/OFF This command turns the display ON and OFF. When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. See the page address circuit in the Function Description (page 1–20) for the detail. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Line address 0 1 0 01000000 0 000001 1 000010 2 111110 6 2 111111 6 3 E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Page address 0 1 0 10110000 0 0001 1 0010 2 0111 7 1000 8 E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 10101111 Display ON

0 Display OFF

EPSON 8–49 SED1565 Series Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. Status Read Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. BUSY When BUSY = 1, it indicates that either processing is occurring internally or a reset condition is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can be satisfied, there is no need to check for BUSY conditions. ADC This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) RESET This indicates that the chip is in the process of initialization either because of a RES signal or because of a reset command. 0: Operating state 1: Reset in progress E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read Data E R/W Column A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 address 0 1 0 0001 A 7 A 6 A 5 A 4 00000000 0

0 A 3 A 2 A 1 A 0 00000001 1

High bits → Low bits → E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0

8–50 EPSON ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the (20) Power Save section. LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 0 0 0 Normal

1 Reverse

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 1 0 RAM Data “H” LCD ON voltage (normal)

1 RAM Data “L”

LCD ON voltage (reverse) E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 0 0 Normal display mode

1 Display all points ON

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 SED1565* **SED1566* **SED1567* **SED1568* **SED1569* ** 0 1 0 1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11100000

8–52 EPSON Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Power Supply Circuits.” The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other.

• The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 1 0 0 0 1 0 1 0 Booster circuit: OFF

1 Booster circuit: ON

0 Voltage regulator circuit: OFF

1 Voltage regulator circuit: ON

0 Voltage follower circuit: OFF

1 Voltage follower circuit: ON

[Translator’s Note: the abbreviations explained within these parentheses for V and V/F have been written out in the English translation and are therefore no longer necessary.] E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Rb/Ra Ratio 0 1 0 0 0 1 0 0 0 0 0 Small 001 010 110 1 1 1 Large E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10000001 E R/W Selected Mode A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 SED1565* ** SED1566* ** SED1567* ** SED1568* ** SED1569* ** 0 1 0 11000* * * Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51

1 Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0

• Disabled bit

EPSON 8–53 SED1565 Series

• Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
• The Electronic Volume Register Set Sequence Figure 26 Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.)
• Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 | V 5 | 0 1 0 * * 0 0 0 0 0 1 Small 0 1 0 * *000010 0 1 0 * *000011 0 1 0 * *111110 0 1 0 * * 1 1 1 1 1 1 Large * Inactive bit E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Static Indicator 0 1 0 10101100 O F F 1O N Electronic volume mode set Electronic volume register set Electronic volume mode clear Yes No Changes complete?

EPSON 8–55 SED1565 Series

• Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1 The oscillator circuit and the LCD power supply circuit are halted. 2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level.
• Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a V DD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The SED1565 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an “L” state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external power supply circuit. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. NOP Non-OPeration Command Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the RES input by the reset command or by using an NOP. Note: The SED1565 Series chips maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the SED1565 Series chip. Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0101 1 1 1 * * * * * Inactive bit E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11100011

8–56 EPSON Command Code Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function (1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 LCD display ON/OFF 1 0: OFF, 1: ON (2) Display start line set 0 1 0 0 1 Display start address Sets the display RAM display start line address (3) Page address set 0 1 0 1 0 1 1 Page address Sets the display RAM page address (4) Column address 0 1 0 0 0 0 1 Most significant Sets the most significant 4 bits set upper bit column address of the display RAM column address. Column address 0 1 0 0 0 0 0 Least significant Sets the least significant 4 bits of set lower bit column address the display RAM column address. (5) Status read 0 0 1 Status 0 0 0 0 Reads the status data (6) Display data write 1 1 0 Write data Writes to the display RAM (7) Display data read 1 0 1 Read data Reads from the display RAM (8) ADC select 0 1 0 1 0 1 0 0 0 0 0 Sets the display RAM address

1 SEG output correspondence

0: normal, 1: reverse (9) Display normal/ 0 1 0 1 0 1 0 0 1 1 0 Sets the LCD display normal/ reverse 1 reverse 0: normal, 1: reverse (10) Display all points 0 1 0 1 0 1 0 0 1 0 0 Display all points ON/OFF 1 0: normal display 1: all points ON (11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 Sets the LCD drive voltage 1 bias ratio SED1566* /SED1568* (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 Column address increment At write: +1 At read: 0 (13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write (14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset (15) Common output 0 1 0 1 1 0 0 0 * * * Select COM output scan mode select 1 direction 0: normal direction, 1: reverse direction (16) Power control set 0 1 0 0 0 1 0 1 Operating Select internal power mode supply operating mode (17) V5 voltage 0 1 0 0 0 1 0 0 Resistor ratio Select internal resistor ratio regulator internal (Rb/Ra) mode resistor ratio set (18) Electronic volume 0 1 0 1 0 0 0 0 0 0 1 mode set Electronic volume 0 1 0 * * Electronic volume value Set the V 5 output voltage register set electronic volume register (19) Static indicator 0 1 0 1 0 1 0 1 1 0 0 0: OFF, 1: ON ON/OFF 1 Static indicator 0 1 0 * * * * * * Mode Set the flashing mode register set (20) Power saver Display OFF and display all points ON compound command (21) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation (22) Test 0 1 0 1 1 1 1 * * * * Command for IC test. Do not use this command (Note) *: disabled data Table 16 Table of SED1565 Series Commands

EPSON 8–57 SED1565 Series COMMAND DESCRIPTION Instruction Setup: Reference (reference) (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the V DD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power.

1 When the built-in power is being used immediately after turning on the power:

Turn ON the VDD -VSS power keeping the RES pin = “L”. When the power is stabilized Initialized state (Default) *1 This concludes the initialization Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V 5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (16) Power control setting *7 Release the reset state. (RES pin = “H”) (In case of SED1565DBB , SED1566D BB , SED1567DBB , SED1568D BB and SED1569DBB ) Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V 5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting

8–58 EPSON COMMAND DESCRIPTION Instruction Setup: Reference (reference)

2 When the built-in power is not being used immediately after turning on the power:

• The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V 5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state. Command description; Power saver START (multiple commands) Turn ON the VDD -VSS power keeping the RES pin = “L”. When the power is stabilized Power saver START (multiple commands) *8 Power saver OFF *8 Initialized state (Default) *1 This concludes the initialization Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V 5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (16) Power control setting *7 Release the reset state. (RES pin = “H”)(In case of SED1565DBB , SED1566D BB , SED1567DBB , SED1568D BB and SED1569DBB ) Arrange to start the power saver within 5ms after releasing the reset state. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Arrange to start power control setting within 5ms after turning OFF the power saver.

EPSON 8–59 SED1565 Series (2) Data Display (3) Power OFF *14

• In case of SED1565DBB , SED1566D BB , SED1567D BB , SED1568D BB and SED1569D BB ,
• In case of other models, Notes: Reference items *14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply V DD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures:
• After turning off the internal power supply, make sure that the potential V 5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS ). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save End of data display End of initialization Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11Function setup by command input (User setup) (1) Display ON/OFF *13 Function setup by command input (User setup) (6) Display data write *12 Reset active (RES pin = “L”) Optional status Function setup by command input (User setup) (20) Power save *15 VDD – VSS power OFF Set the time (tL) from reset active to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH ) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1 V) of the LCD panel. For tH , refer to the <Reference Data> of this event. When tH is too long, insert a resistor between V5 and VDD to reduce it. VDD – VSS power OFF Optional status Function setup by command input (User setup) (20) Power save *15 Set the time (tL) from power save to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH ) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1V) of the LCD panel. tH is determined depending on the voltage regulator external resistors Ra and Rb and the time constant of V 5 ~ V1 smoothing capacity C2.
• When an internal resistor is used, it is recommended to insert a resistor R between V DD and V5 to reduce tH . Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white.

8–60 EPSON Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Reset command or NOP command Refresh sequence Refreshing of DRAM Set all commands to the ready state Precautions on Turning off the power

• In case of SED1565DBB , SED1566D BB , SED1567D BB , SED1568D BB and SED1569D BB , Observe Paragraph 1) as the basic rule. <Turning the power (VDD - VSS ) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS ) OFF
• Observe tL > tH .
• When tL < tH , an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity. tL 1.8 V Since the power (VDD -VSS ) is cut off, the output comes not to be fixed. About 1 V: Below Vth of the LCD panel tH For tH , see Figure 29. COM SEG Power save Power OffReset VDD VDD VDD RES

EPSON 8–61 SED1565 Series <Turning the power (VDD - VSS ) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS ) are off.) → Power (VDD - VSS ) OFF

• Observe tL > tH .
• When tL < tH , an irregular display may occur. For tL , make the power (VDD - VSS ) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging capacity. <Reference Data> V 5 voltage falling (discharge) time (tH ) after the process of operation → power save → reset. V 5 voltage falling (discharge) time (tH ) after the process of operation → reset. Figure 29 tL 1.8 V Since the power (VDD -VSS ) is cut off, the output comes not be fixed. About 1 V: Below Vth of the LCD panel tH For tH , see Figure 29. COM SEG Power OffReset VDD VDD VDD RES 100 0 0.5 C2: V1 to V5 capacity (uF) 1.0 1.8 VDD -VSS (V) V5 voltage falling time (mSec) 2.4 3.0 4.0 5.0

8–62 EPSON

• In case of other models than the above <Turning the power (VDD - VSS ) off> Power save (The LCD powers (VDD - VSS ) are off.) -> Power (VDD - VSS ) OFF
• Observe tL > tH .
• When tL < tH , an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C (smoothing capacity of V5 to V1) and the external resisters Ra + Rb (for V5 voltage regulation) tL 1.8 V Since the power (VDD -VSS ) is cut off, the output comes not be fixed. About 1 V: Below Vth of the LCD panel tH tH is determined depending on the time constant of (Ra + Rb) C. COM SEG Power save Power Off VDD

EPSON 8–63 SED1565 Series VDD VDD VSS2 , V1 to V4 V5, VOUT VCC GND VSS SED1565 Series chip sideSystem (MPU) side ABSOLUTE MAXIMUM RATINGS Unless otherwise noted, VSS = 0 V Parameter Symbol Conditions Unit Power Supply Voltage V DD –0.3 to +7.0 V Power supply voltage (2) V SS2 –7.0 to +0.3 V (VDD standard) With Triple step-up –6.0 to +0.3 With Quad step-up –4.5 to +0.3 Power supply voltage (3) (VDD standard) V 5, VOUT –18.0 to +0.3 V Power supply voltage (4) (VDD standard) V 1, V2, V3, V4 V5 to +0.3 V Input voltage V IN –0.3 to VDD + 0.3 V Output voltage V O –0.3 to VDD + 0.3 V Operating temperature T OPR –40 to +85 °C Storage temperature TCP T STR –55 to +100 Bare chip –55 to +125 °C Figure 30 Notes and Cautions 1. The VSS2 , V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well. Table 17

8–64 EPSON DC CHARACTERISTICS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C Item Symbol Condition Rating Units Applicable Min. Typ. Max. Pin Operating Recom- VDD 2.7 — 3.3 V V DD *1 Voltage (1)mended Voltage Possible 1.8 — 5.5 V V DD *1 Operating Voltage Operating Recom- VSS2 (Relative to VDD ) –3.3 — –2.7 V V SS2 Voltage (2)mended Voltage Possible VSS2 (Relative to VDD ) –6.0 — –1.8 V V SS2 Operating Voltage Operating Possible V5 (Relative to VDD ) –16.0 — –4.5 V V 5 *2 Voltage (3)Operating Voltage Possible V1, V2 (Relative to VDD ) 0.4 × V5 —V DD VV 1, V2 Operating Voltage Possible V3, V4 (Relative to VDD )V 5 — 0.6 × V5 VV 3, V4 Operating Voltage High-level Input V IHC 0.8 × VDD —V DD V* 3 Voltage Low-level Input V ILC VSS — 0.2 × VDD V* 3 Voltage High-level Output V OHC IOH = –0.5 mA 0.8 × VDD —V DD V* 4 Voltage Low-level Output V OLC IOL = 0.5 mA V SS — 0.2 × VDD V* 4 Voltage Input leakage I LI VIN = VDD or VSS –1.0 — 1.0 µA* 5 current Output leakage I current Liquid Crystal Driver RON Ta = 25°CV 5 = –14.0 V — 2.0 3.5 K Ω SEGn ON Resistance (Relative To V DD )V 5 = –8.0 V — 3.2 5.4 K Ω COMn *7 Static Consumption ISSQ — 0.01 5 µAV SS , VSS2 Current Output Leakage I 5Q V5 = –18.0 V — 0.01 15 µAV 5 Current (Relative To V DD ) Input Terminal C IN Ta = 25°C f = 1 MHz — 5.0 8.0 pF Capacitance OscillatorInternal fOSC Ta = 25°C 18 22 26 kHz *8 Frequency Oscillator External fCL SED1565*/1567* 18 22 26 kHz CL Input Internal fOSC Ta = 25°C 27 33 39 kHz *8 Oscillator External fCL SED1566*/1568*/ 14 17 20 kHz CL Input 1569*** Table 18

EPSON 8–65 SED1565 Series Item Symbol Condition Rating Units Applicable Min. Typ. Max. Pin Input voltage VSS2 With Triple –6.0 — –1.8 V V SS2 (Relative To VDD ) VSS2 With Quad –4.5 — –1.8 V V SS2 (Relative To VDD ) Supply Step-up VOUT (Relative to VDD ) –18.0 — — V V OUT output voltage Circuit Voltage regulatorVOUT (Relative to VDD ) –18.0 — –6.0 V V OUT Circuit Operating Voltage Voltage Follower V5 (Relative to VDD ) –16.0 — –4.5 V V 5 *9 Circuit Operating Voltage Base Voltage V REG0 Ta = 25°C –0.05%/°C –2.04 –2.10 –2.16 V *10 VREG1 (Relative to VDD ) –0.2%/°C –4.65 –4.9 –5.15 V *10 Internal Power Table 19

8–66 EPSON

• Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used.
• Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON Ta = 25°C Item Symbol Condition Rating Units NotesMin. Typ. Max. SED1565 *** IDD (1) V DD = 5.0 V, V5 – VDD = –11.0 V — 23 38 µA *11 VDD = 3.0 V, V5 – VDD = –11.0 V — 21 35 SED1566 * VDD = 3.0 V, V5 – VDD = –11.0 V — 17 29 VDD = 5.0 V, V5 – VDD = –8.0 V — 14 24 VDD = 3.0 V, V5 – VDD = –8.0 V — 12 20 SED1567 * VDD = 5.0 V, V5 – VDD = –8.0 V — 11 18 VDD = 3.0 V, V5 – VDD = –8.0 V — 10 17 SED1568 */V DD = 5.0 V, V5 – VDD = –8.0 V — 15 25 SED1569 * VDD = 3.0 V, V5 – VDD = –8.0 V — 13 22 Table 21 Display Pattern Checker Ta = 25°C Item Symbol Condition Rating Units NotesMin. Typ. Max. SED1565 *** IDD (1) V DD = 5.0 V, V5 – VDD = –11.0 V — 18 30 µA *11 VDD = 3.0 V, V5 – VDD = –11.0 V — 16 27 SED1566 * VDD = 3.0 V, V5 – VDD = –11.0 V — 13 22 VDD = 5.0 V, V5 – VDD = –8.0 V — 11 19 VDD = 3.0 V, V5 – VDD = –8.0 V — 9 15 SED1567 * VDD = 5.0 V, V5 – VDD = –8.0 V — 8 13 VDD = 3.0 V, V5 – VDD = –8.0 V — 7 12 SED1568 */V DD = 5.0 V, V5 – VDD = –8.0 V — 12 20 SED1569 * VDD = 3.0 V, V5 – VDD = –8.0 V — 10 17 Table 20 Display Pattern OFF Ta = 25°C Item Symbol Condition Rating Units NotesMin. Typ. Max. SED1565 *** IDD (2)VDD = 5.0 V, Triple step-up voltage.Normal Mode — 67 112 µA *12 V5 – VDD = –11.0 V High-Power Mode — 114 190 VDD = 3.0 V, Quad step-up voltage.Normal Mode — 81 135 V5 – VDD = –11.0 V High-Power Mode — 138 230 SED1566 * VDD = 5.0 V, Double step-up voltage.Normal Mode —3 55 9 V5 – VDD = –8.0 V High-Power Mode — 64 107 VDD = 3.0 V, Triple step-up voltage.Normal Mode —4 37 2 V5 – VDD = –8.0 V High-Power Mode — 84 140 VDD = 3.0 V, Quad step-up voltage.Normal Mode — 72 121 V5 – VDD = –11.0 V High-Power Mode — 128 214 SED1567 * VDD = 5.0 V, Double step-up voltage.Normal Mode —2 64 4 V5 – VDD = –8.0 V High-Power Mode — 60 100 VDD = 3.0 V, Triple step-up voltage.Normal Mode —2 94 9 V5 – VDD = –8.0 V High-Power Mode — 73 122 SED1568 */ VDD = 5.0 V, Double step-up voltage.Normal Mode —3 76 2 SED1569 * V5 – VDD = –8.0 V High-Power Mode — 67 112 VDD = 3.0 V, Triple step-up voltage.Normal Mode —4 67 7 V5 – VDD = –8.0 V High-Power Mode — 87 145 Table 22 Display Pattern OFF

EPSON 8–67 SED1565 Series

• Consumption Current at Time of Power Saver Mode, VSS = 0 V, VDD = 3.0 V ± 10% Ta = 25°C Item Symbol Condition Rating Units NotesMin. Typ. Max. SED1565 *** IDD (2)VDD = 5.0 V, Triple step-up voltage.Normal Mode — 81 135 µA *12 V5 – VDD = –11.0 V High-Power Mode — 127 212 VDD = 3.0 V, Quad step-up voltage.Normal Mode — 96 160 V5 – VDD = –11.0 V High-Power Mode — 153 255 SED1566 * VDD = 5.0 V, Double step-up voltage.Normal Mode —4 16 9 V5 – VDD = –8.0 V High-Power Mode — 71 119 VDD = 3.0 V, Triple step-up voltage.Normal Mode —5 18 5 V5 – VDD = –8.0 V High-Power Mode — 92 154 VDD = 3.0 V, Quad step-up voltage.Normal Mode — 85 142 V5 – VDD = –11.0 V High-Power Mode — 142 237 SED1567 * VDD = 5.0 V, Double step-up voltage.Normal Mode —3 25 3 V5 – VDD = –8.0 V High-Power Mode — 62 103 VDD = 3.0 V, Triple step-up voltage.Normal Mode —4 47 3 V5 – VDD = –8.0 V High-Power Mode — 89 148 SED1568 */ VDD = 5.0 V, Double step-up voltage.Normal Mode —4 47 4 SED1569 * V5 – VDD = –8.0 V High-Power Mode — 74 127 VDD = 3.0 V, Triple step-up voltage.Normal Mode —5 49 0 V5 – VDD = –8.0 V High-Power Mode — 95 159 Table 23 Display Pattern Checker Ta = 25°C Item Symbol Condition Rating Units NotesMin. Typ. Max. Sleep mode SED1565 * IDDS1 — 0.01 5 µA Standby Mode SED1565* IDDS2 —4 8 µA Sleep mode SED1566 * IDDS1 — 0.01 5 µA Standby Mode SED1566* IDDS2 —4 8 µA Sleep mode SED1567 * IDDS1 — 0.01 5 µA Standby Mode SED1567* IDDS2 —3 6 µA Sleep mode SED1568 */I DDS1 — 0.01 5 µA SED1569 * Standby Mode SED1568*/I DDS2 —4 8 µA SED1569 * Table 24 TBD: To Be Determined

EPSON 8–71 SED1565 Series

• The Relationship Between Oscillator Frequency fOSC , Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is as shown in Figure 33. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF, RES, IRS, and HPM terminals. *4 The D0 to D7, FR, FRS, DOF, and CL terminals. *5 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, and HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V 1, V2, V3, and V4). These are specified for the operating voltage (3) range. R ON = 0.1 V/Δ I (Where Δ I is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 9-7 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V 5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the SED1565 Series chips, the temperature range can come in three types as VREG options: (1) approximately –0.05%/°C, (2) – 0.2%/°C, and (3) external input. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The SED1565 is 1/9 biased, SED1566 is 1/8 biased and SED1567 is 1/6 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a model having the V REG option temperature gradient is –0.05%/°C when the V5 voltage regulator internal resistor is used. Table 25 Item f CL fFR SED1565 * When the internal oscillator circuit is used fOSC fOSC____ _____ 44 × 65 When the internal oscillator circuit is not used External input (fCL )f CL____ 260 SED1566 * When the internal oscillator circuit is used fOSC fOSC____ _____ 88 × 49 When the internal oscillator circuit is not used External input (fCL )f CL____ 196 SED1567 * When the internal oscillator circuit is used fOSC fOSC____ _____ 88 × 33 When the internal oscillator circuit is not used External input (fCL )f CL____ 264 SED1568 * When the internal oscillator circuit is used fOSC fOSC____ _____ 88 × 55 When the internal oscillator circuit is not used External input (fCL )f CL____ 220 SED1569 *** When the internal oscillator circuit is used fOSC fOSC____ _____ 88 × 53 When the internal oscillator circuit is not used External input (fCL )f CL____ 212 (fFR is the liquid crystal alternating current period, and not the FR signal period.)

8–72 EPSON TIMING CHARACTERISTICS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) Figure 37 (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH8 0— n s Address setup time tAW8 0— n s System cycle time A0 tCYC8 166 — ns Control L pulse width (WR) WR tCCLW 30 — ns Control L pulse width (RD) RD tCCLR 70 — ns Control H pulse width (WR) WR tCCHW 30 — ns Control H pulse width (RD) RD tCCHR 30 — ns Data setup time D0 to D7 tDS8 30 — ns Address hold time tDH8 10 — ns RD access time tACC8 C L = 100 pF — 70 ns Output disable time tOH8 55 0 n s Table 26 CS1 (CS2="1") WR, RD D0 to D7 (Write) D0 to D7 (Read) tACC8 tOH8 tDS8 tCYC8 tAH8tAW8 tCCLR , tCCLW tCCHR , tCCHW tDS8

EPSON 8–73 SED1565 Series (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH8 0— n s Address setup time tAW8 0— n s System cycle time A0 tCYC8 300 — ns Control L pulse width (WR) WR tCCLW 60 — ns Control L pulse width (RD) RD tCCLR 120 — ns Control H pulse width (WR) WR tCCHW 60 — ns Control H pulse width (RD) RD tCCHR 60 — ns Data setup time D0 to D7 tDS8 40 — ns Address hold time tDH8 15 — ns RD access time tACC8 C L = 100 pF — 140 ns Output disable time tOH8 10 100 ns Table 27 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH8 0— n s Address setup time tAW8 0— n s System cycle time A0 tCYC8 1000 — ns Control L pulse width (WR) WR tCCLW 120 — ns Control L pulse width (RD) RD tCCLR 240 — ns Control H pulse width (WR) WR tCCHW 120 — ns Control H pulse width (RD) RD tCCHR 120 — ns Data setup time D0 to D7 tDS8 80 — ns Address hold time tDH8 30 — ns RD access time tACC8 C L = 100 pF — 280 ns Output disable time tOH8 10 200 ns Table 28 *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW ) for (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR ) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being at the “L” level.

8–74 EPSON (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH6 0— n s Address setup time tAW6 0— n s System cycle time A0 tCYC6 166 — ns Data setup time D0 to D7 tDS6 30 — ns Data hold time tDH6 10 — ns Access time tACC6 C L = 100 pF — 70 ns Output disable time tOH6 10 50 ns Enable H pulse Read E tEWHR 70 — ns time Write tEWHW 30 — ns Enable L pulse Read E tEWLR 30 — ns time Write tEWLW 30 — ns Table 29 System Bus Read/Write Characteristics 2 (6800 Series MPU) Figure 38 R/W CS1 (CS2="1") E D0 to D7 (Write) D0 to D7 (Read) tACC6 tOH6 tDS6 tCYC6 tAH6tAW6 tEWHR , tEWHW tEWLR , tEWLW tDH6

EPSON 8–75 SED1565 Series (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH6 0— n s Address setup time tAW6 0— n s System cycle time A0 tCYC6 300 — ns Data setup time D0 to D7 tDS6 40 — ns Data hold time tDH6 15 — ns Access time tACC6 C L = 100 pF — 140 ns Output disable time tOH6 10 100 ns Enable H pulse Read E tEWHR 120 — ns time Write tEWHW 60 — ns Enable L pulse Read E tEWLR 60 — ns time Write tEWLW 60 — ns Table 30 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Address hold time A0 tAH6 0— n s Address setup time tAW6 0— n s System cycle time A0 tCYC6 1000 — ns Data setup time D0 to D7 tDS6 80 — ns Data hold time tDH6 30 — ns Access time tACC6 C L = 100 pF — 280 ns Output disable time tOH6 10 200 ns Enable H pulse Read E tEWHR 240 — ns time Write tEWHW 120 — ns Enable L pulse Read E tEWLR 120 — ns time Write tEWLW 120 — ns Table 31 *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≤ (tCYC6 – tEWLW – tEWHW ) for (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR ) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

8–76 EPSON (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Serial Clock Period SCL tSCYC 200 — ns SCL “H” pulse width tSHW 75 — ns SCL “L” pulse width tSLW 75 — ns Address setup time A0 tSAS 50 — ns Address hold time tSAH 100 — ns Data setup time SI tSDS 50 — ns Data hold time tSDH 50 — ns CS-SCL time CS tCSS 100 — ns tCSH 100 — ns Table 32 The Serial Interface Figure 39 tCSS tCSH tSAH tSHW tSDHtSDS tSLW tf tr tSCYC tSAS CS1 (CS2="1") SCL SI

EPSON 8–77 SED1565 Series (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Serial Clock Period SCL tSCYC 250 — ns SCL “H” pulse width tSHW 100 — ns SCL “L” pulse width tSLW 100 — ns Address setup time A0 tSAS 150 — ns Address hold time tSAH 150 — ns Data setup time SI tSDS 100 — ns Data hold time tSDH 100 — ns CS-SCL time CS tCSS 150 — ns tCSH 150 — ns Table 33 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Item Signal Symbol Condition Rating UnitsMin Max Serial Clock Period SCL tSCYC 400 — ns SCL “H” pulse width tSHW 150 — ns SCL “L” pulse width tSLW 150 — ns Address setup time A0 tSAS 250 — ns Address hold time tSAH 250 — ns Data setup time SI tSDS 150 — ns Data hold time tSDH 150 — ns CS-SCL time CS tCSS 250 — ns tCSH 250 — ns Table 34 *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.

8–78 EPSON Display Control Output Timing Figure 40 (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max FR delay time FR tDFR C L = 50 pF — 10 40 ns Table 35 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max FR delay time FR tDFR C L = 50 pF — 20 80 ns Table 36 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max FR delay time FR tDFR C L = 50 pF — 50 200 ns Table 37 *1 Valid only when the master mode is selected. *2 All timing is based on 20% and 80% of VDD . tDFR CL (OUT) FR

EPSON 8–79 SED1565 Series (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max Reset time tR — — 0.5 µs Reset “L” pulse width RES tRW 0.5 — — µs Table 38 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max Reset time tR —— 1 µs Reset “L” pulse width RES tRW 1— — µs Table 39 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Item Signal Symbol Condition Rating UnitsMin Typ Max Reset time tR — — 1.5 µs Reset “L” pulse width RES tRW 1.5 — — µs *1 All timing is specified with 20% and 80% of VDD as the standard. Table 40 Reset Timing Figure 41 tRW tR Reset completeDuring reset RES Internal status

EPSON 8–81 SED1565 Series CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) The liquid crystal display area can be enlarged with ease through the use of multiple SED1565 Series chips. Use a same equipment type. (1) SED1565 (master) ↔ SED1565 (slave) Figure 43 VSS VDD M/S Output Input SED1565 Series Master M/S FR CL DOF FR CL DOF SED1565 Series Slave

EPSON 8–83 SED1565 Series FR CL DOF CS1 CS2 RES WR,R/W RD, E D6, SCL D7, SI V DD VSS VSS2 VOUT CAP3- CAP1+ CAP1- CAP2- CAP2+ VRS V DD VR VDD M/S CLS C86 P/S HPM IRS FR FRS COM S COM 63 COM 33 COM 32 SEG 131 SEG 130 SEG 1 SEG 0 COM S COM 0 COM 30 COM 31 CHIP TOP VIEW An example A SAMPLE TCP PIN ASSIGNMENT SED1565T 0B TCP Pin Layout Note: The following does not specify dimensions of the TCP pins.

8–84 EPSON EXTERNAL VIEW OF TCP PINS Specifications

• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 25µm
• Sn plating
• Product pitch: 41P (19.0mm)
• Solder resist positional tolerance: –0.3 (Mold, marking area) (Mold, marking area) (Mold, marking area) (Mold, marking area) Section A Section A Section A Output terminal pattern shape Section B Test pat detailed view

EPSON 8–85 SED1565 Series NOTICE Please be advised on the following points in the use of this development manual. 1. This manual is subject to change without previous notice. 2. This manual does not guarantee or furnish the industrial property right nor its execution. Application examples in the manual are intended to ensure your better understanding of the product. Thus, the manufacturer shall not be liable for any trouble arising in your circuits from using such application example. Numerical values provided in the property table of this manual are represented with their magnitude on the numerical line. 3. No part of this manual may not be reproduced, copied or used for commercial purposes without a written permission from the manufacturer. In handling of semiconductor devices, your attention is required to the following points. [Precautions on Light] Property of semiconductor devices may be affected when they are exposed to light, possibly resulting in malfunctioning of the ICs. To prevent such malfunctioning of the ICs mounted on the boards or products, make sure that: (1) Your design and mounting layout done are so that the IC is not exposed to light in actual use. (2) The IC is protected from light in the inspection process. (3) The IC is protected from light in its front, rear and side faces.