SED1530 EPSON | Alldatasheet
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SSC5000SeriesDot Matrix LCD Controller Driver PF777-03 SED1530 Series n DESCRIPTION The SED1530 series is a single-chip LCD driver for dot-matrix liquid crystal displays (LCD’s) which is directly connectable to a microcomputer bus. It accepts 8-bit serial or parallel display data directly sent from a microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent of microprocessor clock. The use of the on-chip display RAM of 65 × 132 bits and a one-to-one correspondence between LCD panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of freedom. As a total of 133 circuits of common and segment outputs are incorporated, a single chip of SED1530 series can make 33 × 100-dot (16 × 16-dot kanji font: 6 columns × 2 lines) displays, and a single chip of SED1531 can make 65 × 132-dot (kanji font: 8 columns x 4 lines) displays when the SED1531 is combined with the common driver SED1635. The SED1532 can display the 65x200-dot (or 12-column by 4-line Kanji font) area using two ICs in master and slave modes. As an independent static indicator display is provided for time-division driving, the low-power display is realized during system standby and others. No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can implement a high-performance handy display system with a minimum current consumption and a smallest LSI configuration. Two types of SED1530 series are available: one in which common outputs are arranged on a single side and the other in which common outputs are arranged on both sides. n FEATURES l Direct RAM data display using the display RAM. When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed. (At normal display) l RAM capacity: 65 × 132 = 8580 bits l High-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800. l Serial interface l Many command functions: Read/Write Display Data, Display ON/OFF, Normal/Reverse Display, Page Address Set, Set Display Start Line, Set Column Address, Read Status, All Display ON/OFF, Set LCD Bias, Electronic contrast Controls, Read Modify Write, Select Segment Driver Direction, Power Save l Ultra Low Power Consumption l Built-in Power Supply Circuit for LCD l 133 Driver Output
Type 1 [VREG Temperature gradient 0.2% / °C]
- Specifications (for chip models) Type 2 [VREG Temperature gradient 0.00% / °C] n LINE UP Name Duty LCD bias Segment driver COM driver Display area Remarks SED1530D 0* 1/33 1/5, 1/6 100 33 33 × 100 COM single-side assignment SED1530D A* 1/33 1/5, 1/6 100 33 33 × 100 COM dual-side assignment SED1531D 0* 1/65 1/6, 1/8 132 0 65 × 132 SED1635 is used for COM. SED1532D 0* 1/65 1/6, 1/8 100 33 65 × 200 COM single-side right assignment SED1532D B* 1/65 1/6, 1/8 100 33 65 × 200 COM single-side left assignment Name Duty LCD bias Segment driver COM driver Display area Remarks SED1530D F* 1/33 1/5, 1/6 100 33 33 × 100 COM both-side layout SED1532D E* 1/65 1/6, 1/8 100 33 65 × 200 COM single-side, right-hand layout SED1533D F* 1/17 1/5 116 17 17 × 116 COM both-side layout SED1534D E* 1/9 1/5 124 9 9 × 124 COM single-side layout Note: The SED1530 series has the following subcodes depending on their shapes. (The SED1530 examples are given.) SED1530T : TCP (The TCP subcode differs from the inherent chip subcode.) SED1530D : Bear chips SED1530D * A : Aluminum pad SED1530D * B : Gold bump l On-chip LCD power circuit: Liquid crystal driving power supply booster circuit, voltage regulator circuit, voltage follower × 4. l On-chip electronic contrast control functions l Ultra low power consumption l Power supply voltages: VDD - VSS -2.4 V to -6.0 V VDD - V5 -4.5 V to -16.0 V (In the case of external power supply) l Wide operating temperature range: Ta = -40 to 85°C l CMOS process l Package: TCP and bare chip l Non-radiation-resistant design
n BLOCK DIAGRAM (SED1530D 0B ) O0 O99 O100 O15 VDD VSS CAP1+ CAP1– CAP2+ CAP2– CAP3– FRS FR CL DYO DOF M//S Segment driver Common driver Shift register Power supply circuit I/O buffer circuit 132 x 65-dot display data RAM Display data latch Line address decoder Line counter Initial display line register Page address register Column address decoder 8-bit column address counter 8-bit column address register Display timing generator circuit Bus holder Status register Oscillator Microprocessor interface I/O buffer COMS COM S Output status selector circuit VS1 CS1 CS2 A0 RD (E) WR (R/W) C86 P/S RES D7 (SI) (SCL) D5 D4 D3 D2 D1 D0 Command decoder VOUT VR
Chip Size: 6.65x4.57 mm Pad Pitch: 118 µm (Min.) SED153 *D *A (Aluminum pad model) Pad Center Size: 90x90 µm Chip Thickness: 300 µm SED153 *D *B (Gold bump model) Bump Size: 76x76 µm Bump Height: 23 µm (Typ.) Chip Thickness: 625 µm
Unit: um PAD PIN No. Name X Y 1 0127 2986 2142 2 0128 2862 3 0129 2738 4 0130 2614 5 0131 2490
6 COMS 2366
7 FRS 2242
8 FR 2124
9 DYO 2006
10 CL 1888
11 DOF 1770
12 VS1 1652
13 M/S 1534
14 RES 1416
15 P/S 1298
16 CS1 1180
17 CS2 1062
18 C86 944
19 A0 826
WR(W/R) 708
21 RD(E) 590
23 D0 236
24 D1 236
25 D2 118
26 D3 0
27 D4 -118
28 D5 -236
D6(SCL) -354
30 D7(SI) -472
32 V OUT -708
33 CAP3- -826
34 CAP1+ -944
35 CAP1- -1062
36 CAP2+ -1180
37 CAP2- -1298
39 V R -1534
40 V DD -1652
41 V 1 -1770
42 V 2 -1888
43 V 3 -2006
44 V 4 -2124
45 V 5 -2242
46 O0 -2366
47 O1 -2490
48 O2 -2614
49 O3 -2738
50 O4 -2862
No. Name X Y
51 O5 -2986 2142
52 O6 -3178 2006
53 O7 1888
54 O8 1770
55 O9 1652
56 O10 1534
57 O11 1416
58 O12 1298
59 O13 1180
60 O14 1062
61 O15 944
62 O16 826
63 O17 708
64 O18 590
65 O19 472
66 O20 354
67 O21 236
68 O22 118
69 O23 0
70 O24 -118
71 O25 -236
72 O26 -354
73 O27 -472
74 O28 -590
75 O29 -708
76 O30 -826
77 O31 -944
78 O32 -1062
79 O33 -1180
80 O34 -1298
81 O35 -1416
82 O36 -1534
83 O37 -1652
84 O38 -1770
85 O39 -1888
86 O40 -2006
87 O41 -2986 -2142
88 O42 -2862
89 O43 -2738
90 O44 -2614
91 O45 -2490
92 O46 -2366
93 O47 -2242
94 O48 -2124
95 O49 -2006
96 O50 -1888
97 O51 -1770
98 O52 -1652
99 O53 -1534
100 O54 -1416
No. Name X Y
101 O55 -1298 -2142
102 O56 -1180
103 O57 -1062
104 O58 -944
105 O59 -826
106 O60 -708
107 O61 -590
108 O62 -472
109 O63 -354
110 O64 -236
111 O65 -118
112 O66 0
113 O67 118
114 O68 236
115 O69 354
116 O70 472
117 O71 590
118 O72 708
119 O73 826
120 O74 944
121 O75 1062
122 O76 1180
123 O77 1298
124 O78 1416
125 O79 1534
126 O80 1652
127 O81 1770
128 O82 1888
129 O83 2006
130 O84 2124
131 O85 2242
132 O86 2366
133 O87 2490
134 O88 2614
135 O89 2738
136 O90 2862
137 O91 2986
138 O92 3178 -2006
139 O93 -1888
140 O94 -1770
141 O95 -1652
142 O96 -1534
143 O97 -1416
144 O98 -1298
145 O99 -1180
146 O100 -1062
147 O101 -944
148 O102 -826
149 O103 -708
150 O104 -590
No. Name X Y
151 O105 3178 -472
152 O106 -354
153 O107 -236
154 O108 -118
155 O109 0
156 O110 118
157 O111 236
158 O112 354
159 O113 472
160 O114 590
161 O115 708
162 O116 826
163 O117 944
164 O118 1062
165 O119 1180
166 O120 1298
167 O121 1416
168 O122 1534
169 O123 1652
170 O124 1770
171 O125 1888
172 O126 2006
n ABSOLUTE MAXIMUM RATINGS Notes: 1. V1 to V5 and VOUT voltages are based on VDD =0 V. 2. Voltages VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be satisfied. 3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical characteristics conditions during general operation. Otherwise, an LSI malfunction or reduced LSI reliability may result. VDD VSS VDD V5, VOUT V1 to V4 (SED1530 series)(System) VCC GND Rating Symbol Value Unit –0.3 to +7.0 Supply voltage range Triple boosting V DD –0.3 to +6.0 V Quadruple boosting –0.3 to +4.5 Supply voltage range (1) (VDD Level) V 5, VOUT –18.0 to +0.3 V Supply voltage range (2) (VDD Level) V 1, V2, V3, V4 V5 to +0.3 V Input voltage range V IN –0.3 to VDD +0.3 V Output voltage range V0 –0.3 to V DD +0.3 V Operating temperature range T OPR –40 to +85 °C Storage temperature rangeTCP TSTR –55 to +100 °C Bear chip –55 to +125
n ELECTRICAL CHARACTERISTICS l DC Characteristics (VSS = 0 V, VDD = 5 V ±10%, Ta = –40 to +85°C unless otherwise noted.) Item Symbol Condition Min. Typ. Max. Unit Pin used Power voltage(1) V DD 4.5 5.0 5.5 V V SS *1 Operational 2.4 – 6.0 Operating voltage Operational V5 VDD level (VDD = 0 V) –16.0 – –4.5 V V 5 *2 (2) Operational V1, V2 VDD level (VDD = 0 V) 0.4 × V5 –V DD VV 1, V2 Operational V3, V4 VDD level (VDD = 0 V) V 5 – 0.6 × V5 VV 3, V4 High-level input voltage VIHC 0.7 × VDD –V DD V* 3 VDD = 2.7 V 0.8 × VDD –V DD *3 Low-level input voltage V ILC VSS – 0.3 × VDD V* 3 VDD = 2.7 V V SS – 0.2 × VDD *3 High-level output voltage VOHC IOH = –1 mA 0.8 × VDD –V DD V* 5 VDD = 2.7 V, IOH = –0.5 mA 0.8 × VDD –V DD *5 Low-level output voltage VOLC IOL = 1 mA V SS – 0.2 × VDD V* 5 VDD = 2.7 V, IOL = 0.5 mA V SS – 0.2 × VDD *5 High-level input voltage VIHS 0.85 × VDD – VDD *4 VDD = 2.7 V 0.8 × VDD – VDD *4 Low-level input voltage V ILS VSS – 0.15 × VDD *4 VDD = 2.7 V V SS – 0.2 × VDD *4 Input leakage current I LI VIN = VDD or VSS –1.0 – 1.0 µA* 6 Output leakage current I LO –3.0 – 3.0 µA* 7 LCD driver ON resistance R ON Ta = 25°CV 5 = –14.0 V – 2.0 3.0 K Ω VDD level V 5 = –8.0 V – 3.0 4.5 Static current consumption ISSQ VIN = VDD or VSS – 0.01 5.0 µAV SS I5Q V5 = –18.0 V (VDD level) – 0.01 15.0 µAV 5 Input pin capacity C IN Ta = 25°C, f = 1 MHz – 5.0 8.0 pF *3 *4 Oscillation frequency fOSC Ta = 25°CV DD = 5 V 18 22 26 kHz *9 VDD = 2.7 V 18 22 26 Input voltage V DD Triple boosting 2.4 – 6.0 V *10 Quadruple boosting 2.4 – 4.5 Booster output voltage V OUT Triple voltage conversion (VDD level) –18.0 – – V V OUT Voltage regulator operation VOUT (VDD level) –18.0 – –6.0 V V OUT voltage Voltage follower operation V5 (V DD level) –18.0 – –6.0 V *11 voltage –16.0 – –4.5 Reference voltage V REG Ta = 25°C (VDD level) –2.75 –2.55 –2.35 V CMOSSchmitt SEG n COM n Recommended Operation Built-in power circuit
(µA) I DD (1) (ISS +15) 1234 VDD 5 6 7 (V) Conditions: Remarks: The built-in power supply is OFF and an external power supply is used. SED1530 V 5-VDD = –8.0V SED1531 V5-VDD = –11.0V SED1532 V5-VDD = –11.0V SED1533 V5-VDD = –6.0V SED1534 V5-VDD = –6.0V Ta = 25°C *12 SED1531, SED1532 SED1533, SED1534 SED1530 l Dynamic current consumption (1) when the built-in power supply is OFF Ta = 25°C Item Symbol Condition Min. Typ. Max. Unit Note SED1530 I DD VDD = 5.0 V, V5 – VDD = –8.0 V — 24 40 µA *12 (1) V DD = 3.0 V, V5 – VDD = –8.0 V — 22 35 SED1531 V DD = 5.0 V, V5 – VDD = –11.0 V — 40 65 VDD = 3.0 V, V5 – VDD = –11.0 V — 36 60 SED1532 V DD = 5.0 V, V5 – VDD = –11.0 V — 39 65 VDD = 3.0 V, V5 – VDD = –11.0 V — 32 55 SED1533 V DD = 3.0 V, V5 – VDD = –5.0 V — 20 35 SED1534 V DD = 3.0 V, V5 – VDD = –5.0 V — 20 35 l Dynamic current consumption (2) when the built-in power supply is ON Ta = 25°C Item Symbol Condition Min. Typ. Max. Unit Note SED1530 I DD VDD = 5.0 V, V5 – VDD = –8.0 V, dual boosting — 41 70 µA *13 (1) V DD = 3.0 V, V5 – VDD = –8.0 V, triple boosting — 48 80 SED1531 V DD = 5.0 V, V5 – VDD = –11.0 V, triple boosting — 96 160 VDD = 3.0 V, V5 – VDD = –11.0 V, quadruple boosting— 118 190 SED1532 V DD = 5.0 V, V5 – VDD = –11.0 V, triple boosting — 95 160 VDD = 3.0 V, V5 – VDD = –11.0 V, quadruple boosting— 114 190 SED1533 V DD = 3.0 V, V5 – VDD = –5.0 V, dual boosting — 30 50 SED1534 V DD = 3.0 V, V5 – VDD = –5.0 V, dual boosting — 32 55 l Current consumption during Power Save mode VSS =0V, VDD =2.7 to 5.5V Ta = 25°C Item Symbol Condition Min. Typ. Max. Unit Note During sleep IDDS1 SED1530, SED1531, SED1532 — 0.01 1 µA During standbyIDDS2 SED1530, SED1531, SED1532 — 10 20 l Typical current consumption characteristics (reference data)
- Dynamic current consumption (1) when LCD external power mode lamp is ON
(µA) I DD (1) (ISS +15) 1234 VDD 5 6 7 (V) Conditions: Remarks: The built-in power supply is ON. SED1530 V5-VDD = –8.0V, triple boosting SED1531 V 5-VDD = –11.0V, quadruple boosting SED1532 V 5-VDD = –11.0V, quadruple boosting SED1533 V 5-VDD = –5.0V, dual boosting SED1534 V 5-VDD = –5.0V, dual boosting Ta = 25°C *13 SED1531, SED1532 SED1533, SED1534 SED1530
- Dynamic current consumption (2) when the LCD built-in power circuit lamp is ON *1 Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the microprocessor. *2 V DD and V5 operating voltage range. (Refer to Fig.) The operating voltage range applies if an external power supply is used. *3 A0, D0 - D5, D6, D7 (SI), RD (E), WR (R/W), CS1, CS2, FR, M/S, C86, P/S and DOF pins *4 CL, SCL (D6) and RES pins *5 D0 - D5, D6, D7 (SI), FR, FRS, DYO, DOF and CL pins *6 A0, RD (E), WR (R/W), CS1, CS2, M/S, RES, C86 and P/S pins *7 Applies when the D0 - D7, FR, CL, DYO and DOF pins are in high impedance, *8 Resistance value when 0.1 V is applied between the output pin SEGn or COMn and each power supply pin (V1, V2, V3, V4). This is specified in the operating voltage (2) range. R ON = 0.1 V/ΔI (ΔI: Current flowing when 0.1 V is applied in the ON status.) *9 For the relationship between oscillation frequency and frame frequency. (Refer to Fig.) *10 For triple or quadruple boosting using the on-chip power using the primary-side power supply VDD must be used within the input voltage range. *11 The voltage regulator adjusts V5 within the voltage follower operating voltage range. *12, *13 Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity, etc. This is current consumption under the conditions of display data = checker, display ON, SED1530 = 1/33 duty, and SED1531 and SED1532 = 1/65 duty. *12 Applies to the case where the on-chip oscillator circuit is used and no access is made from the microprocessor. *13 Applies to the case where the on-chip oscillator circuit and the on-chip power circuit are used and no access is made from the microprocessor. The current flowing through voltage regulation resistors (R1, R2 and R3) is not included. The current consumption, when the on-chip voltage booster is used, is for the power supply VDD .
- Relationship between oscillation frequency and frame frequency The relationship between oscillation frequency fOSC and LCD frame frequency fF can be obtained by the following expression. (fF does not indicate the FR signal cycle but the AC cycle.) Relationship between clock (fCL ) and frame frequency fF Duty f CL f F SED1530 1/33 f OSC /8 f OSC /(8*33) SED1531 1/65 f OSC /4 f OSC /(4*65)SED1532 SED1533 1/17 f OSC /8 f OSC /(8*17) SED1534 1/9 f OSC /8 f OSC /(8*9)
- V SS and V5 operating voltage range
- Current consumption at access IDD (2) - Microprocessor access cycle This indicates current consumption when data is always written on the checker pattern at fcyc. When no access is made, only IDD (1) occurs. -20 -15 -10 0 2468 -16 -11 2.4 [V] V5-VDD Operating range VDD [V] 3.5 0.1 0.01 0 0.01 0.1 1 10 [mA] IDD (2) fcyc [MHz] SED1531, SED1532 SED1530 SED1533 SED1534 Condition: SED1530 V 5-VDD =–8.0V, triple boosting SED1531 V 5-VDD =–11.0V, quadruple boosting SED1532 V 5-VDD =–11.0V, quadruple boosting SED1533 V 5-VDD =–6.0V, dual boosting SED1534 V 5-VDD =–6.0V, dual boosting Ta = 25°C
n CONNECTION BETWEEN LCD Drivers The LCD panel display area can easily be expanded by use of multiple SED1530 series chips. The SED1530 series can also be connected to the common driver (SED1670). l SED1531 to SED1670 l SED1530 to SED1531 l SED1532 to SED1532 DOFCL DYO SED1532 (slave) SED1532 (master) FR FR CL DYO DOF M/S VDD M/S VSS DOFCL DYO SED1530 (slave) SED1530 (master) FR FR CL DYO DOF M/S VDD M/S VSS DOFCL DYO SED1531 (master) SED1670D 1A FR FR DOFF DIO YSCL M/S VDD
n LCD PANEL CONNECTION EXAMPLES SED1530D 0A <Master> SEG (100) SEG (100) COM (33) COM (17) COM (16) SED1530D AA <Master> SED1530 : 100 × 33dot @SED1532 : 200 × 65 dot SED1532 <Slave> SEG(100) VDD M/S FR DOF CL SED1532 <Master> SEG(100) M/S FR DOF CL COM(33) COM(32) 132 × 65 dot SED1670 SED1531 SEG(132) VDD FR CL DYO DOF M/S COM(65) DOFF DIO YSCL FR
NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. IBM is registered trademark of International Business Machines Corporation, U.S.A. © Seiko Epson Corporation 1996 All right reserved. ELECTRONIC DEVICE MARKETING DEPARTMENT IC Marketing & Engineering Group 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5816 FAX: 0425-87-5624 International Marketing Department I (Europe, U.S.A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5812 FAX: 0425-87-5564 International Marketing Department II (Asia) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN First issue Dec., 1996 Phone: 0425-87-5814 FAX: 0425-87-5110 Printed Nov. 1996 in Japan H