SEA01 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Absolute maximum ratings
- 2 Application information
- 2.1 Constant voltage and current control and with online digital trimming
- 3 Online digital trimming procedure
- 3.1 General features
- 3.2 Device address
- 3.3 Device commands
- 3.4 Emulation commands
- 3.4.1 Emulate Vref V
- 3.4.2 Emulate Vref I
- 3.5 Read commands and status register
- 3.5.1 Read Vref V
- 3.5.2 Read Vref I
- 3.6 Write NVM (OTP)
- 3.7 Reload NVM (OTP)
- 4 Package mechanical data
- 5 Ordering information
- 6 Revision history
Features
- Online digital trimming for the highest end- product accuracy in voltage and current control
- Automatic operation eliminates manual intervention in the production line
- Simple and robust trimming protocol and storage
- Redundant OTP (first and second trimming)
- Extended operating voltage range
- Very low quiescent current
- Offered in an SO8 package
Applications
- SMPS requiring accurate voltage and current regulation
- AC-DC adapters
- Battery chargers
Description
SEA01 is a highly integrated solution for SMPS applications requiring precise voltage and current regulation. The device integrates two voltage references, two op-amps (with open-drain outputs), a low-side current sensing circuit and an online digital trimming machine. The internal reference Vref V, along with one op- amp, is the core of the voltage control loop. The internal reference VrefI and the other op-amp make up the current control loop. The embedded digital trimming allows the user, through software, to adjust and permanently store both Vref V and VrefI internal references during the production test of the end product, compensating the tolerance of the external components and the error due to their discretized values. Redundant OTP gives the user a second chance to change the values stored in the non-volatile memory of the IC during the first trimming process. This feature allows having the highest end- product accuracy of voltage and current control without the use of external discrete components or manual intervention. SO8 287&ORFN 9FF 'DWD 287 'DWD 9FWUO ,VHQVH*QG 287 ',*,7$/ 75,00,1* 0$&+,1( 9UHI9 9UHI, 9FWUO ',*,7$/ 75,00,1* 0$&+,1( 9UHI9 9UHI, 2XW 'DWD&ORFN 2XW ,VHQVH *1' 9FF 9FWUO
1 Absolute maximum ratings
calculated with the formula Pdiss = Vcc • Icc + IOUT1 • VOUT1 + IOUT2 • VOUT2. Table 1. Absolute maximum ratings Table 2. Thermal data Table 3. Pin functions Clock logic input for I2C serial communication protocol. This pin will be externally pulled up to 3.6 V max. floating during normal operation). midpoint of a resistor divider that senses the output voltage. the positive end of the current sense resistor through a decoupling resistor. Ground. Return of the bias current of the device. 0 V reference for all voltages. possible to minimize load current effect on the voltage regulation setpoint.
primary side for voltage control loop. primary side for current control loop. 2C serial communication protocol. floating during normal operation). Table 4. Electrical characteristics Table 3. Pin functions (continued)
- Specification referred to -25 °C < Tamb < 105 °C.
- With V OUT1 > 3 V, If the voltage on Vctrl (the inverting input of the amplifier) is higher than the non-inverting
input (VrefV), and it is increased by 1 mV, the sink current at the output Out1 will be increased by 19 mA.
- The internal voltage reference is set to Vref V. The voltage control loop precision takes into account the
transconductance operational amplifier.
- When the inverting input at Isense is greater than 30 mV, and the voltage is increased by 1mV, the sinking
- The internal current sense threshold is tr iggered when the voltage on the Isense pin is VrefI. The current
can be trimmed with a resolution of 1 mV.
- The Data and Clock pins are connected to an internal bus at 3.3 V.
Table 4. Electrical characteristics (continued)
2 Application information
2.1 Constant voltage and current control and with online digital
Figure 3. Typical application schematic an accurate current limitation or regulation and/or very accurate voltage regulation). software without the use of external discrete components or manual intervention. the first step after measuring the output voltage of the application. adjust the value of the measured current to the target current. supply of the device independent from the output voltage).
Figure 4. Output voltage versus output current
SEA01 Online digital trimming procedure
3 Online digital trimming procedure
3.1 General features
The embedded digital trimming allows the user to adjust and permanently store using software, both the VrefV and VrefI internal references during the production test of the end- product, compensating the tolerance of the external components and the error due to their discretized values. The device provides a non-volatile memory (NVM) based on a redundant OTP (two OTP, one-time-programmable memories) and a volatile memory. The volatile memory is used to adjust the value of both Vref V and VrefI internal references. Once the optimal values have been found, the user can permanently store them in the OTP memory. The presence of a second OTP allows the user to perform a second trimming of the device. It is possible to perform a new search of the optimal values of VrefV and VrefI and permanently store these values in the second OTP. At device power-on the values of VrefV and VrefI depend on the OTP status: – if the IC non-volatile memory has never been burned (i.e. no value has ever been permanently stored in OTP memories) VrefV and VrefI are initialized at the default values (see Table 6 and Table 7) – if the IC non-volatile memory has been burned a first time (i.e. values stored in the first OTP) VrefV and VrefI are the values selected and stored by the user during the first trimming process – if the IC non-volatile memory has been burned a second time (i.e.values stored in the second OTP) VrefV and VrefI are the values selected and stored by the user during the second trimming process The device is provided with an I2C slave-only interface that requires only two pins for the communication: DATA and CLOCK. The I2C interface allows the user to access the device in a simple way, using the I2C-bus, also assuring robust data communication integrity thanks to an additional parity check control. Two wires, serial data and serial clock, carry information between the devices connected to the I2C bus. SEA01 can operate only as an I2C-slave, i.e. it needs to be addressed by a master (a microcontroller, industrial PC, ATE, etc.) that initiates a data transfer on the bus and generates the clock signal to permit that transfer. Generation of clock signals on the I 2C-bus is always the responsibility of the master. SEA01 can operate as either a receiver or transmitter (transmitter-slave) depending on the command received from the master. The serial data and serial clock are bidirectional lines connected to a positive supply voltage through a pull-up resistor: SEA01 has an internal pull-up on the DATA and CLOCK pins in order to pull HIGH the pins when they are floating, but the user has to implement an adequate pull-up of the lines using external pull-up resistors. When the bus is free, both lines are HIGH. The data on the serial data line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the serial clock line is LOW. Within the procedure of the I 2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions. A HIGH-to-LOW transition on the serial data line while the serial clock is HIGH is one such unique case. This situation indicates a START condition. A LOW- to-HIGH transition on the serial data line while the serial clock line is HIGH defines a STOP
Online digital trimming procedure SEA01 condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical – every byte put on the serial data line is 8 bits long – each byte is followed by an acknowledge bit – data is transferred with the most significant bit (MSB) first – data transfer with acknowledge is obligatory The acknowledge-related clock pulse is generated by the master. The transmitter releases the serial data line (HIGH) during the acknowledge clock pulse. The receiver pulls down the serial data line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Of course, setup and hold time must also be taken into account. When SEA01 is addressed, it generates an acknowledge after each byte has been received. When SEA01 doesn't acknowledge its address, the data line is left HIGH by the device. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a SEA01-receiver does acknowledge its address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by SEA01 generating the not-acknowledge on the first byte to follow. SEA01 leaves the data line HIGH and the master generates a STOP or a repeated START condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data transfers have the following format: after the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address the slave without first generating a STOP condition.
3.2 Device address
The device is provided with the following fixed 7-bit address, while the 8th bit is the data direction (R/W). This address corresponds to <52> Hex. MSB LSB A1 A2 A3 A4 A5 A6 A7 R/W 10 1 0 0 1 0 1 / 0
3.3 Device commands
The commands are implemented with a one-byte word including a bit for parity check (LSB). The parity check has the following structure. flag is internally activated. The data are implemented with a one-byte word including a bit for parity check (LSB). The parity check has the following structure. it is not possible to execute any command before a read command.
3.4 Emulation commands
and VrefI register) before deciding to permanently store the values in the device. Changing VrefV and VrefI is done independently. Table 5. Command mapping
3.4.1 Emulate Vref V
command and corresponds to the code given in Table 5. Table 6. VrefV values
check is ok. To reset the parity fail flag the user has to perform a read command. resulting in a direct change from the old to the new value.
- The device is initialized with the default va lue of 0000000 (i.e. the 0% trim value for VrefV). If the device has already been
burned once, the default value is the one stored in the first OTP memory. range is proportional to the trimming value [-3% , + 3%] with a trimming step of 0.2% referenced to the 0% trim value. Table 6. VrefV values (continued)
3.4.2 Emulate Vref I
and corresponds to the code given in Table 5. The value of VrefI is changed according to the data sent (see Table 7). The 8th bit D8 is the parity check bit. Table 7. VrefI values
check is ok. To reset the parity fail flag the user has to perform a read command. resulting in a direct change from the old to the new value.
- The device is initialized with the default value of 0000000 (i.e . 0% trim value of VrefI). If the device has already been burned
once, the default value is the one stored in the first OTP memory.
- The 0% trim value was assumed 30 mV as an example but th is value can be in the range [27 mV, 33 mV]. The trimming
range is proportional to the trimming value [-50% + 50%] with a trimming step of 3.3% referenced to the 0% trim value. Table 7. VrefI values (continued)
3.5 Read commands an d status register
two) or if a an error occurred during the trimming process (Status register) (see Table 8). communication error during the trimming process.
3.5.1 Read Vref V
Table 8. Status register
11 X 1
SEA01 Online digital trimming procedure In case of a communication error, the content of status register is <11>, which means that the internal parity flag fail was activated. After a read command is executed, the parity flag fail is reset and a new command can be executed by the device.
3.5.2 Read Vref I
The command “read VrefI” reads data from the volatile VrefI register and the OTP status register. It is a write/read command and corresponds to the code given in Table 5. Once the device receives the Emulate/read VrefI command, in order to perform a read, it is necessary to send a repeated start (Sr) and address as a read, i.e. with the 8th bit (R/W) set to 'one'. The device will send to the data bus an 8-bit word where the first two bits are the status register bit M1 and M2 and the following 6 bits are the value of VrefI with parity check as last bit. In case of a communication error, the content of the status register is <11>, which means that the internal parity flag fail was activated. After a read command is executed, the parity flag fail is reset and a new command can be executed by the device.
3.6 Write NVM (OTP)
After VrefV and VrefI have been trimmed to the desired level, the user can confirm their values and store them permanently. The presence of two OTP allows the user to repeat the trimming procedure a second time and change the value previously stored in the device. Please note that when the user starts from an IC already burned once, the default values of VrefV or VrefI are the ones stored in the first OTP. This is virtually a real-time trim-and-test without switching off the supply. It is important that during the entire process the supply voltage of the IC never falls below its UVLO level, otherwise, the settings stored in the volatile memory will be lost and the IC will return to the default setting or the values stored in the first OTP. It is also necessary that the burn command is executed with Vcc = 19 V with a current capability of 90 mA. Start/stop Byte 1 (address, write type) Ack Byte 2 command Ack Start/stop Byte 3 (address, read type) Ack Byte 4 read data Nack Start/stop Read VrefI S 0 Sr pck P x x Sent by slave (device) x x Sent by master
Online digital trimming procedure SEA01 If the search for the best value of VrefV and VrefI is done with a Vcc value lower than 19 V, the user has to pay attention that, during the step-up of Vcc before the burning of the NVM, a negative ringing on Vcc will cause a drop below the UVLO of the IC. The user can eventually decide to perform the search for the best value of Vref V and VrefI, storing these values in an external memory (ATE, industrial PC, etc.), then increasing Vcc to 19 V and waiting to have a stable Vcc level. The user can then resend the selected value of VrefV and VrefI stored in the external memory before sending the burn NVM command. Both values written in the VrefV & VrefI register (volatile memory) are permanently stored in the NVM (OTP) in a single step. It is possible to burn the NVM by sending the burn command (write) given in Table 5 followed by a data byte with the same code as a burn command. It is important to provide a zapping time of at least 45 msec and to have Vcc of the IC equal to 19 V with a current capability of 90 mA, in order to ensure correct blowing of the anti-fuse cells. After the stop (P) the device doesn't acknowledge any I2C communication for about 45 ms in order to perform the burning of the NVM. To protect the NVM memory from an incorrect write, if the parity fail flag was activated, i.e. an error occurred during the trimming process, the burn command is not executed. The NVM is written only if it was never written or written one time. If the NVM is written a second time, the previous content is lost. Please note that after a Write NVM command the Status Register is not automatically updated. It must be updated by turning off and on again the IC or by sending a Reload NVM command to the device. Once the update is performed, the number of times the IC has been burned can be read from the status register. Start/stop Byte 1 (address, write type) Ack Byte 2: command Ack Byte 3 (address, read type) Ack Start/stop Write NVM S P x Sent by slave (device) x x Sent by master
SEA01 Online digital trimming procedure
3.7 Reload NVM (OTP)
During the trimming process if the user has changed the value of VrefV or VrefI with the emulation command and wants to reload the content stored in the NVM, he can use the “Reload NVM” command which is a write command that reloads the NVM into the Vref V/VrefI registers (volatile memory). Start/stop Byte 1 (address, write type) Ack Byte 2 command Ack Start/stop Reload NVM S P x Sent by slave (device) x x Sent by master
4 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. SO8 mechanical data
Figure 5. SO8 package dimensions
5 Ordering information
Table 10. Ordering information
6 Revision history
Table 11. Document revision history 07-May-2013 1 Initial release.