SE9174C SEAWARD | Alldatasheet

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Technical content

Features

¾ Ideal for DDR-I, DDR-II and DDR-III V TT Applications ¾ Sink and Source 2A Continuous Current ¾ Integrated Power MOSFETs ¾ Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. ¾ High Accuracy Output Voltage at Full-Load ¾ Output Adjustment by Two External Resistors ¾ Low External Component Count ¾ Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output ¾ Current Limiting Protection ¾ On-Chip Thermal Protection ¾ Available in PSOP-8 (Exposed Pad) Packages ¾ V IN and VCNTL No Power Sequence Issue ¾ 100% Lead (Pb)-Free Pin Configuration Application ¾ Desktop PCs, Notebooks, and Workstations ¾ Graphics Card Memory Termination ¾ Set Top Boxes, Digital TVs, Printers ¾ Embedded Systems ¾ Active Termination Buses ¾ DDR-I, DDR-II and DDR-III Memory Systems Block Diagram Pin Description Pin Name Pin function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage input and Chip Enable VOUT Output Voltage

All contents are subject to change without prior notice Absolute Maximum Rating (1) Parameter Symbol Value Unit Input Voltage V IN 6 V Control Voltage V CNTL 6 V Power Dissipation P D Internally Limited -- ESD Rating -- 3 KV Storage Temperature Range T S -65 to 150 °C Lead Temperature (Soldering, 5 sec.) T LEAD 260 °C Package Thermal Resistance ΘJC 28 ºC/W Operating Rating(2) Parameter Symbol Value Units Input Voltage V IN 2.5 to 1.5 ±3% V Control Voltage V CNTL 5.0 or 3.3 ±5% V Ambient Temperature T A -40 to +85 ℃ Junction Temperature T J -40 to +125 ℃

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Units Input VCNTL Operation Current ICNTL I OUT=0A -- 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown),RLOAD = 180Ω -- 50 90 μA Output (DDR / DDR II / DDR III) Output Offset Voltage(3) VOS I OUT= 0A -20 -- +20 IOUT= +2A Load Regulation(4) ΔVLOAD IOUT= -2A -20 -- +20 mV Protection Current limit ILIM 2.2 -- -- A Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V -- 170 -- Thermal Shutdown Hysteresis ΔTSD 3.3V ≤ VCNTL ≤ 5V -- 35 -- REFEN Shutdown VIH Enable 0.6 -- -- Shutdown Threshold VIL Shutdown -- -- 0.2 V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A.

All contents are subject to change without prior notice Typical Operating Characteristics

All contents are subject to change without prior notice

Application Information

Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the SE9174C. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may re sult in large parasitic inductance and cause undesired oscillation between SE9174C and the preceding power converter. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on V REFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. Thermal Consideration SE9174C regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125℃. The power dissipation definition in device is: P D = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) /ΘJA Where T J(MAX) is the maximum operation junction temperature 125℃, TA is the ambient temperature and the ΘJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance ( ΘJA is layout dependent) for PSOP-8 package (Exposed Pad) is 75 ℃/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25℃ can be calculated by following formula: The thermal resistance ΘJA of PSOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of PSOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow.

All contents are subject to change without prior notice Application Diagram VIN VCNTL REFEN VOUT GNDCSS CIN CCNTL COUT RDUMMY RTTVIN=2.5V/1.8V/1.5V VCNTL=3.3V P1 P6 P3 P4 2N7002 EN R1 = R2 = 100KΩ, RTT = 50Ω/33Ω/25Ω COUT, min = 10μF (Ceramic) + 1000μF under the worst case testing condition RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1μF, CIN = 470μF(Low ESR), CCNTL = 47μF

All contents are subject to change without prior notice Outline Drawing PSOP-8 Contact Information Seaward Electronics Incorporated – China Room 1605, Building 1, International Pioneering Park, #1 Shangdi Xinxi Rd. Haidian District, Beijing 100085, China Tel: 86-10-8289-5700/01/05 Fax: 86-10-8289-5706 Email: sales@seawardinc.com.cn Seaward Electronics Corporation – Taiwan 2F, #181, Sec. 3, Min Quan East Rd. Taipei, Taiwan R.O.C Tel: 886-2-2712-0307 Fax: 886-2-2712-0191 Email: sales@seawardinc.com.tw Seaward Electronics Incorporated – North America 1512 Centre Pointe Dr. Milpitas, CA95035, USA Tel: 1-408-821-6600 Last Updated - 12/4/2008