NE555_07 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 20
Technical content
Datasheet sections
- 1 Schematic diagrams
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Monostable operation
- 4.2 Astable operation
- 4.3 Pulse width modulator
- 4.4 Linear ramp
- 4.6 Additional information
- 5 Package information
- 6 Ordering information
- 7 Revision history
Features
■ Low turn off time ■ Maximum operating frequency greater than 500kHz ■ Timing from microseconds to hours ■ Operates in both astable and monostable modes ■ High output current can source or sink 200mA ■ Adjustable duty cycle ■ TTL compatible ■ Temperature stability of 0.005% per °C
Description
The NE555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA. N DIP8 (Plastic package) D SO8 (Plastic micropackage) 1 - GND 2 - Trigger 3 - Output 4 - Reset 5 - Control voltage 6 - Threshold 7 - Discharge 8 - V CC Pin connections (top view)
1 Schematic diagrams
Figure 1. Block diagram Figure 2. Schematic diagram
2 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings Table 2. Operating conditions
3 Electrical characteristics
Table 3. T amb = +25°C, VCC = +5V to +15V (unless otherwise specified)
- Tested at V CC = +5V and VCC = +15V.
- This will determine th e maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20MΩ for 15V
operation and 3.5MΩ for +5V operation.
- Specified with trigger input high.
- No protection against excessive pin 7 current is necessary, providing the package dissipation rating is not exceeded.
- Time measured from a positiv e pulse (from 0V to 0.8xVCC) on the Threshold pin to the transition from high to low on the
Output pin. Trigger is tied to Threshold.
4 Application information
4.1 Monostable operation
external capacitor is initially held discharged by a transistor inside the timer. Figure 12. Typical schematics in monostable operation is easily determined by Figure 14. during the timing cycle discharges the external capacitor and causes the cycle to start over. pulse is applied, the output is driven to its LOW state. capacitor rapidly and drives the output to its LOW state. Figure 13 shows the actual waveforms generated in this mode of operation.
Figure 13. Waveforms in monostable operation Figure 14. Pulse duration versus R1C1
4.2 Astable operation
In the astable mode of operation, C1 charges and discharges between 1/3 VCC and 2/3 VCC. independent of the supply voltage.
4.3 Pulse width modulator
Figure 18. Pulse width modulator
4.4 Linear ramp
Figure 19. Linear ramp
Figure 21. 50% duty cycle oscillator and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.
4.6 Additional information
minimum recommended is 0.1µF in parallel with 1µF electrolytic.
5 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com
Figure 22. DIP8 package mechanical data
Figure 23. SO8 package mechanical data
6 Ordering information
7 Revision history
Table 4. Order codes 1-Jun-2003 1 Initial release. 15-Mar-2007 4 Expanded order code table.