SE555DG4

NA555_07 TI | Alldatasheet

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V CC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW) NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 Timing From Microseconds to Hours Adjustable Duty Cycle Astable or Monostable Operation TTL-Compatible Output Can Sink or Source up to 200 mA These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of V CC These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of V to With a 5-V supply, output levels are compatible with TTL inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 1973 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.

www.ti.com NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 ORDERING INFORMATION V THRES T A MAX PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING V CC V PDIP P Tube of NE555P NE555P Tube of NE555D SOIC D NE555 Reel of 2500 NE555DR C to C 11.2 V SOP PS Reel of 2000 NE555PSR N555 Tube of 150 NE555PW TSSOP PW N555 Reel of 2000 NE555PWR PDIP P Tube of SA555P SA555P C to C 11.2 V Tube of SA555D SOIC D SA555 Reel of 2000 SA555DR PDIP P Tube of NA555P NA555P C to 105 C 11.2 V Tube of NA555D SOIC D NA555 Reel of 2000 NA555DR PDIP P Tube of SE555P SE555P Tube of SE555D SOIC D SE555D C to 125 C 10.6 Reel of 2500 SE555DR CDIP JG Tube of SE555JG SE555JG LCCC FK Tube of SE555FK SE555FK (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE TRIGGER THRESHOLD DISCHARGE RESET OUTPUT VOLTAGE (1) VOLTAGE (1) SWITCH Low Irrelevant Irrelevant Low On High <1/3 V DD Irrelevant High Off High >1/3 V DD >2/3 V DD Low On High >1/3 V DD <2/3 V DD As previously established (1) Voltage levels shown are nominal. Submit Documentation Feedback

www.ti.com S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: RESET can override TRIG, which can override THRES. NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage (2) V V I Input voltage CONT, RESET, THRES, TRIG V CC V I O Output current 225 mA D package P package θ JA Package thermal impedance (3) (4) C/W PS package PW package 149 FK package 5.61 θ JC Package thermal impedance (5) (6) C/W JG package 14.5 T J Operating virtual junction temperature 150 C Case temperature for s FK package 260 C Lead temperature mm (1/16 in) from case for s JG package 300 C T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) Maximum power dissipation is a function of T J (max), θ JA and T A The maximum allowable power dissipation at any allowable ambient temperature is P D J (max) T A θ JA. Operating at the absolute maximum T J of 150 C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) Maximum power dissipation is a function of T J (max), θ JC and T C The maximum allowable power dissipation at any allowable case temperature is P D J (max) T C θ JC Operating at the absolute maximum T J of 150 C can affect reliability. (6) The package thermal impedance is calculated in accordance with MIL-STD-883. over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT NA555, NE555, SA555 4.5 V CC Supply voltage V SE555 4.5 V I Input voltage CONT, RESET, THRES, and TRIG V CC V I O Output current 200 mA NA555 105 NE555 T A Operating free-air temperature C SA555 SE555 125 Submit Documentation Feedback

www.ti.com Electrical Characteristics NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 V CC V to T A C (unless otherwise noted) NA555 SE555 NE555 PARAMETER TEST CONDITIONS UNIT SA555 MIN TYP MAX MIN TYP MAX V CC V 9.4 10.6 8.8 11.2 THRES voltage level V V CC V 2.7 3.3 2.4 3.3 4.2 THRES current (1) 250 250 nA 4.8 5.2 4.5 5.6 V CC V T A C to 125 C TRIG voltage level V 1.45 1.67 1.9 1.1 1.67 2.2 V CC V T A C to 125 C 1.9 TRIG current TRIG at V 0.5 0.9 0.5 µ A 0.3 0.7 0.3 0.7 RESET voltage level V T A C to 125 C 1.1 RESET at V CC 0.1 0.4 0.1 0.4 RESET current mA RESET at V 0.4 0.4 1.5 DISCH switch off-state 100 100 nA current 9.6 10.4 V CC V T A C to 125 C 9.6 10.4 CONT voltage V (open circuit) 2.9 3.3 3.8 2.6 3.3 V CC V T A C to 125 C 2.9 3.8 0.1 0.15 0.1 0.25 V CC I OL mA T A C to 125 C 0.2 0.4 0.5 0.4 0.75 V CC I OL mA T A C to 125 C 2.2 2.5 V CC I OL 100 mA Low-level output voltage T A C to 125 C 2.7 V V CC I OL 200 mA 2.5 2.5 V CC I OL 3.5 mA T A C to 125 C 0.35 0.1 0.2 0.1 0.35 V CC I OL mA T A C to 125 C 0.8 V CC I OL mA 0.15 0.25 0.15 0.4 13.3 12.75 13.3 V CC I OL 100 mA T A C to 125 C High-level output voltage V CC I OH 200 mA 12.5 12.5 V 3.3 2.75 3.3 V CC I OL 100 mA T A C to 125 C V CC V Output low, No load V CC V Supply current mA V CC V Output high, No load V CC V (1) This parameter influences the maximum value of the timing resistors R A and R B in the circuit of Figure For example, when V CC the maximum value is R R A R B 3.4 M Ω and for V CC the maximum value is M Ω Submit Documentation Feedback

www.ti.com Operating Characteristics NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 V CC V to T A C (unless otherwise noted) NA555 SE555 NE555 TEST PARAMETER UNIT SA555 CONDITIONS (1) MIN TYP MAX MIN TYP MAX Each timer, monostable (3) T A C 0.5 1.5 (4) Initial error of timing interval (2) Each timer, astable (5) 1.5 2.25 Each timer, monostable (3) T A MIN to MAX 100 (4) Temperature coefficient of ppm/ timing interval C Each timer, astable (5) 150 Each timer, monostable (3) T A C 0.05 0.2 (4) 0.1 0.5 Supply-voltage sensitivity of %/V timing interval Each timer, astable (5) 0.15 0.3 C L pF, Output-pulse rise time 100 200 (4) 100 300 ns T A C C L pF, Output-pulse fall time 100 200 (4) 100 300 ns T A C (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) Values specified are for a device in a monostable circuit similar to Figure with the following component values: R A k Ω to 100 k Ω C 0.1 µ (4) On products compliant to MIL-PRF-38535, this parameter is not production tested. (5) Values specified are for a device in an astable circuit similar to Figure with the following component values: R A k Ω to 100 k Ω C 0.1 µ Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ TA = 125°C ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = 25°C IOL − Low-Level Output Current − mA ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ VCC = 5 V LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ TA = −55°C 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 0.4 0.7 0.02 0.2 − Low-Level Output Voltage − VVOL ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ VCC = 10 V LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT − Low-Level Output Voltage − VVOL IOL − Low-Level Output Current − mA 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 0.4 0.7 0.02 0.2 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = 125°C ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = 25°C ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = −55°C TA = 125°C TA = 25°C TA = −55°C ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ VCC = 15 V LOW -LEVEL OUTPUT VOL TAGE vs LOW -LEVEL OUTPUT CURRENT − Low-Level Output Voltage − VVOL IOL − Low-Level Output Current − mA 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 0.4 0.7 0.02 0.2 0.6 0.2 1.4 1.8 2.0 0.4 1.6 0.8 1.2 IOH − High-Level Output Current − mA ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = 125°C ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = 25°C 100704020107421 ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ VCC = 5 V to 15 V ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ TA = −55°C VCC VOH − Voltage Drop − V)( DROP BETWEEN SUPPL Y VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 Data for temperatures below C and above C are applicable for SE555 circuits only. Figure Figure Figure Figure Submit Documentation Feedback

www.ti.com 5 6 7 8 9 10 11 − Supply Current − mA SUPPL Y CURRENT vs SUPPL Y VOLTAGE 12 13 14 15 TA = 25°C TA = 125°C TA = −55°C Output Low, No Load CCI VCC − Supply Voltage − V 0.995 0.990 0.985 0 5 10 1.005 1.010 NORMALIZED OUTPUT PULSE DURA TION (MONOST ABLE OPERA TION) vs SUPPL Y VOLTAGE 1.015 15 20 CCVPulse Duration Relative to Value at = 10 V VCC − Supply Voltage − V 0.995 0.990 0.985 −75 −25 25 1.005 1.010 NORMALIZED OUTPUT PULSE DURA TION (MONOST ABLE OPERA TION) vs FREE-AIR TEMPERA TURE 1.015 75 125 TA − Free-Air Temperature − °C −50 0 50 100 VCC = 10 V Pulse Duration Relative to Value at TA = 25/C0053C 150 100 200 250 300 − Propagation Delay Time − ns PROPAGA TION DELA Y TIME vs LOWEST VOL TAGE LEVEL OF TRIGGER PULSE Lowest Voltage Level of Trigger Pulse TA = −55°C TA = 125°C TA = 25°C tPD TA = 0°C TA = 70°C 0 0.1 x VCC 0.2 x VCC 0.3 x VCC 0.4 x VCC NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) Data for temperatures below C and above C are applicable for SE555 circuits only. Figure Figure Figure Figure Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION Monostable Operation VCC (5 V to 15 V) R A R L Output GND OUT VCCCONT RESET DISCH THRES TRIGInput Î Î Î 5 8 Pin numbers shown are for the D, JG, P, PS, and PW packages. NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 For monostable operation, any of these timers can be connected as shown in Figure If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through R A until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop Q goes high), drives the output low, and discharges C through Q1. Figure Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately t w 1.1R A Figure is a plot of the time constant for various values of R A and The threshold levels and charge rates both are directly proportional to the supply voltage, V CC The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to V CC Submit Documentation Feedback

www.ti.com − Output Pulse Duration − s C − Capacitance − µF 10−1 10−2 10−3 10−4 1001010.10.01 10−5 0.001 tw R A = 10 MΩ R A = 10 kΩ R A = 1 kΩ R A = 100 kΩ R A = 1 MΩ Voltage − 2 V/div Time − 0.1 ms/div ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Capacitor Voltage Output Voltage Input Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ R A = 9.1 kΩ C L = 0.01 µF R L = 1 kΩ See Figure 9 Astable Operation Voltage − 1 V/div Time − 0.5 ms/div tH Capacitor Voltage Output VoltagetL ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ R A = 5 k/C0087 RL = 1 k/C0087 R B = 3 k/C0087 See Figure 12 C = 0.15 µF GND OUT VCCCONT RESET DISCH THRES TRIG C R B R A Output R L 0.01 µF VCC (5 V to 15 V) (see Note A) Î Î Î NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Open 5 8 Pin numbers shown are for the D, JG, P, PS, and PW packages. NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) Figure 10. Typical Monostable Waveforms Figure 11. Output Pulse Duration vs Capacitance As shown in Figure adding a second resistor, R B to the circuit of Figure and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through R A and R B and then discharges through R B only. Therefore, the duty cycle is controlled by the values of R A and R B This astable connection results in capacitor C charging and discharging between the threshold-voltage level 0.67 V CC and the trigger-voltage level 0.33 V CC As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms Submit Documentation Feedback

www.ti.com tH /C00430.693 (RA /C0041R B) C tL /C00430.693 (RB) C Other useful relationships are shown below. period/C0043tH /C0041tL /C00430.693 (RA /C00412R B) C frequency/C00911.44 (RA /C00412R B) C Output driver duty cycle/C0043 tL tH /C0041tL /C0043 R B R A /C00412R B Output waveform duty cycle /C0043 tL tH /C0043 R B R A /C0041R B Low-to-high ratio /C0043 tH tH /C0041tL /C00431– R B R A /C00412R B f − Free-Running Frequency − Hz C − Capacitance − µF 100 k 10 k 1 k 100 1001010.10.01 0.1 0.001 R A + 2 RB = 10 MΩ R A + 2 RB = 1 MΩ R A + 2 RB = 100 kΩ R A + 2 RB = 10 kΩ R A + 2 RB = 1 kΩ Missing-Pulse Detector Time − 0.1 ms/div Voltage − 2 V/div ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC = 5 V R A = 1 kΩ C = 0.1 µF See Figure 15 Capacitor Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage Input Voltage VCC (5 V to 15 V) DISCH OUT VCCRESET R L R A A5T3644 C THRES GND CONT TRIG Input 0.01 µF ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Output 4 8 Pin numbers shown are shown for the D, JG, P, PS, and PW packages. NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) Figure shows typical waveforms generated during astable operation. The output high-level duration t H and low-level duration t L can be calculated as follows: Figure 14. Free-Running Frequency The circuit shown in Figure can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure Figure 15. Circuit for Missing-Pulse Detector Figure 16. Completed Timing Waveforms for Missing-Pulse Detector Submit Documentation Feedback

www.ti.com Frequency Divider Voltage − 2 V/div Time − 0.1 ms/div Capacitor Voltage Output Voltage Input Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ VCC = 5 V R A = 1250 Ω C = 0.02 µF See Figure 9 NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) By adjusting the length of the timing cycle, the basic circuit of Figure can be made to operate as a frequency divider. Figure shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. Figure 17. Divide-by-Three Circuit Waveforms Submit Documentation Feedback

www.ti.com Pulse-Width Modulation THRES GND C R AR L VCC (5 V to 15 V) Output DISCH OUT VCCRESET TRIG CONT Modulation Input (see Note A) Clock Input NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. 4 8 Pin numbers shown are for the D, JG, P, PS, and PW packages. Voltage − 2 V/div Time − 0.5 ms/div ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Capacitor Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Output Voltage ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Clock Input Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ R A = 3 kΩ C = 0.02 µF R L = 1 kΩ See Figure 18 ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ Modulation Input Voltage NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used. Figure 18. Circuit for Pulse-Width Modulation Figure 19. Pulse-Width-Modulation Waveforms Submit Documentation Feedback

www.ti.com Pulse-Position Modulation Voltage − 2 V/div ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ R A = 3 kΩ R B = 500 Ω R L = 1 kΩ See Figure 20 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Capacitor Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Modulation Input Voltage Time − 0.1 ms/div R B Modulation Input (see Note A) CONT TRIG RESET V CC OUT DISCH VCC (5 V to 15 V) R L R A C GND THRES NOTE A: The modulating signal can be direct or capacitively coupled to CONT . For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Pin numbers shown are for the D, JG, P, PS, and PW packages. 4 8 Output NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) As shown in Figure any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. Figure 20. Circuit for Pulse-Position Modulation Figure 21. Pulse-Position-Modulation Waveforms Submit Documentation Feedback

www.ti.com Sequential Timer S VCC RESET V CC OUT DISCH GND CONT TRIG 4 8 THRES R C C C 0.01 C C = 14.7 µF R C = 100 kΩ Output C RESET V CC OUT DISCH GND CONT TRIG 4 8 THRES R B 33 kΩ 0.001 0.01 µF C B = 4.7 µF R B = 100 kΩ Output BOutput AR A = 100 kΩ C A = 10 µF µF 0.01 µF 0.001 33 kΩRA THRES TRIG CONT GND DISCH OUT VCCRESET µF µF C BC A Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Voltage − 5 V/div t − Time − 1 s/div ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ See Figure 22 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output A ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output B ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output C ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ t = 0 ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ tw C = 1.1 RC C C ÏÏ ÏÏ ÏÏ tw C ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ tw B = 1.1 RB C B ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ tw A = 1.1 RA C A ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ tw A ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ tw B NA555 NE555 SA555 SE555 PRECISION TIMERS SLFS022F SEPTEMBER 1973 REVISED JUNE 2006 APPLICATION INFORMATION (continued) Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure shows a sequencer circuit with possible systems, and Figure shows the output waveforms. Figure 22. Sequential Timer Circuit Figure 23. Sequential Timer Waveforms Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type NA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NE555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NE555PSLE OBSOLETE SO PS 8 TBD Call TI Call TI NE555PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555Y OBSOLETE 0 TBD Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SE555D ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SE555DR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SE555JG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type SE555JGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type SE555N OBSOLETE PDIP N 8 TBD Call TI Call TI SE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 2

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 3

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant NA555DR D 8 SITE 27 330 12 6.4 5.2 2.1 8 12 Q1 NA555DR D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1 NE555DR D 8 SITE 27 330 12 6.4 5.2 2.1 8 12 Q1 NE555DR D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1 NE555PSR PS 8 SITE 41 330 16 8.2 6.6 2.5 12 16 Q1 NE555PWR PW 8 SITE 41 330 12 7.0 3.6 1.6 8 12 Q1 SA555DR D 8 SITE 27 330 12 6.4 5.2 2.1 8 12 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) NA555DR D 8 SITE 27 342.9 336.6 20.64 NA555DR D 8 SITE 41 346.0 346.0 29.0 NE555DR D 8 SITE 27 342.9 336.6 20.64 NE555DR D 8 SITE 41 346.0 346.0 29.0 NE555PSR PS 8 SITE 41 346.0 346.0 33.0 NE555PWR PW 8 SITE 41 346.0 346.0 29.0 SA555DR D 8 SITE 27 342.9 336.6 20.64 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Pack Materials-Page 2

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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