SE555D

NA555_V01 TI | Alldatasheet

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Technical content

S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community NA555,NE555,SA555,SE555 SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014 xx555PrecisionTimers

1 Features 3 Description

These devices are precision timing circuits capable of 1• Timing From Microseconds to Hours producing accurate time delays or oscillation. In the• Astable or Monostable Operation time-delay or mono-stable mode of operation, the

• Adjustable Duty Cycle timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode• TTL-Compatible Output Can Sink or Source of operation, the frequency and duty cycle can beUp to 200 mA controlled independently with two external resistors• On Products Compliant to MIL-PRF-38535, and a single external capacitor.All Parameters Are Tested Unless Otherwise The threshold and trigger levels normally are two-Noted. On All Other Products, Production thirds and one-third, respectively, of VCC. TheseProcessing Does Not Necessarily Include levels can be altered by use of the control-voltageTesting of All Parameters. terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If2 Applications the trigger input is above the trigger level and the
• Fingerprint Biometrics threshold input is above the threshold level, the flip- flop is reset and the output is low. The reset (RESET)• Iris Biometrics input can override all other inputs and can be used to• RFID Reader initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) PDIP (8) 9.81 mm × 6.35 mm SOP (8) 6.20 mm × 5.30 mm xx555 TSSOP (8) 3.00 mm × 4.40 mm SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

NA555,NE555,SA555,SE555 SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014 www.ti.com Table of Contents

5 Revision History

Changes from Revision H (June 2010) to Revision I Page

2 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

V CC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW) NA555,NE555,SA555,SE555 www.ti.com SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014

6 Pin Configuration and Functions

D, P, PS, FK I/O DESCRIPTIONPW, JGNAME NO. Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitorCONT 5 12 I/O connection DISCH 7 17 O Open collector output to discharge timing capacitor GND 1 2 – Ground 1, 3, 4, 6, 8, 9, 11, 13,NC – No internal connection14, 16, 18, OUT 3 7 O High current timer output signal RESET 4 10 I Active low reset input forces output and discharge low. THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V) Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: NA555 NE555 SA555 SE555

NA555,NE555,SA555,SE555 SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014 www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage(2) 18 V VI Input voltage CONT, RESET, THRES, TRIG VCC V IO Output current ±225 mA D package 97 P package 85 θJA Package thermal impedance(3)(4) °C/W PS package 95 PW package 149 FK package 5.61 θJC Package thermal impedance(5)(6) °C/W JG package 14.5 TJ Operating virtual junction temperature 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (6) The package thermal impedance is calculated in accordance with MIL-STD-883.

7.2 Handling Ratings

PARAMETER DEFINITION MIN MAX UNIT Tstg Storage temperature range –65 150 °C

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT NA555, NE555, SA555 4.5 16 VCC Supply voltage V SE555 4.5 18 VI Input voltage CONT, RESET, THRES, and TRIG VCC V IO Output current ±200 mA NA555 –40 105 NE555 0 70 TA Operating free-air temperature °C SA555 –40 85 SE555 –55 125

4 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

NA555,NE555,SA555,SE555 www.ti.com SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014

7.4 Electrical Characteristics

VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555 PARAMETER TEST CONDITIONS UNITSA555 MIN TYP MAX MIN TYP MAX VCC = 15 V 9.4 10 10.6 8.8 10 11.2 THRES voltage level V THRES current(1) 30 250 30 250 nA 4.8 5 5.2 4.5 5 5.6 VCC = 15 V TA = –55°C to 125°C 3 6 TRIG voltage level V VCC = 5 V TA = –55°C to 125°C 1.9 TRIG current TRIG at 0 V 0.5 0.9 0.5 2 μA 0.3 0.7 1 0.3 0.7 1 RESET voltage level V TA = –55°C to 125°C 1.1 RESET at VCC 0.1 0.4 0.1 0.4 RESET current mA RESET at 0 V –0.4 –1 –0.4 –1.5 DISCH switch off-state 20 100 20 100 nAcurrent DISCH switch on-state VCC = 5 V, IO = 8 mA 0.15 0.4 Vvoltage 9.6 10 10.4 9 10 11 VCC = 15 V VCC = 5 V TA = –55°C to 125°C 2.9 3.8 0.1 0.15 0.1 0.25 VCC = 15 V, IOL = 10 mA TA = –55°C to 125°C 0.2 0.4 0.5 0.4 0.75 VCC = 15 V, IOL = 50 mA TA = –55°C to 125°C 1 2 2.2 2 2.5 VCC = 15 V, IOL = 100 mA Low-level output voltage TA = –55°C to 125°C 2.7 V VCC = 15 V, IOL = 200 mA 2.5 2.5 VCC = 5 V, IOL = 3.5 mA TA = –55°C to 125°C 0.35 0.1 0.2 0.1 0.35 VCC = 5 V, IOL = 5 mA TA = –55°C to 125°C 0.8 VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4 13 13.3 12.75 13.3 VCC = 15 V, IOH = –100 mA TA = –55°C to 125°C 12 High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V 3 3.3 2.75 3.3 VCC = 5 V, IOH = –100 mA TA = –55°C to 125°C 2 VCC = 15 V 10 12 10 15 Output low, No load VCC = 5 V 3 5 3 6 Supply current mA VCC = 15 V 9 10 9 13 Output high, No load VCC = 5 V 2 4 2 5 (1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ. Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: NA555 NE555 SA555 SE555

NA555,NE555,SA555,SE555 SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014 www.ti.com

7.5 Operating Characteristics

VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555TESTPARAMETER UNITSA555CONDITIONS(1) MIN TYP MAX MIN TYP MAX Each timer, monostable(3) TA = 25°C 0.5 1.5(4) 1 3Initial error of timing %interval(2) Each timer, astable(5) 1.5 2.25 Each timer, monostable(3) TA = MIN to MAX 30 100(4) 50Temperature coefficient of ppm/ timing interval °CEach timer, astable(5) 90 150 CL = 15 pF,Output-pulse rise time 100 200(4) 100 300 nsTA = 25°C CL = 15 pF,Output-pulse fall time 100 200(4) 100 300 nsTA = 25°C (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 μF. (4) On products compliant to MIL-PRF-38535, this parameter is not production tested. (5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 μF.

6 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

7.6 Typical Characteristics

Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. Figure 1. Low-Level Output Voltage Figure 2. Low-Level Output Voltage Figure 3. Low-Level Output Voltage Figure 4. Drop Between Supply Voltage and Output Figure 5. Supply Current Figure 6. Normalized Output Pulse Duration

Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. Figure 7. Normalized Output Pulse Duration Figure 8. Propagation Delay Time(Monostable Operation)

8 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î NA555,NE555,SA555,SE555 www.ti.com SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014

8 Detailed Description

8.1 Overview

The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC.

8.2 Functional Block Diagram

A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES.

8.3 Feature Description

8.3.1 Mono-stable Operation

For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: NA555 NE555 SA555 SE555

Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 9. Circuit for Monostable Operation independent of the supply voltage, so long as the supply voltage is constant during the time interval. as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC. Figure 10. Typical Monostable Waveforms Figure 11. Output Pulse Duration vs Capacitance

10 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Pin numbers shown are for the D, JG, P, PS, and PW packages.

8.3.2 A-stable Operation

times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms

Figure 14. Free-Running Frequency

8.3.3 Frequency Divider

Figure 15. Divide-by-Three Circuit Waveforms

8.4 Device Functional Modes

Table 1. Function Table (1) Voltage levels shown are nominal.

12 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Pin numbers shown are shown for the D, JG, P, PS, and PW packages.

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

operating frequency. This section presents a simplified discussion of the design process.

9.2 Typical Applications

9.2.1 Missing-Pulse Detector

pulse as shown in Figure 17. Figure 16. Circuit for Missing-Pulse Detector

9.2.1.1 Design Requirements

9.2.1.2 Detailed Design Procedure

Pin numbers shown are for the D, JG, P, PS, and PW packages.

9.2.1.3 Application Curves

Figure 17. Completed Timing Waveforms for Missing-Pulse Detector

9.2.2 Pulse-Width Modulation

signal is shown, any wave shape could be used. Figure 18. Circuit for Pulse-Width Modulation

14 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

9.2.2.1 Design Requirements

9.2.2.2 Detailed Design Procedure

9.2.2.3 Application Curves

Figure 19. Pulse-Width-Modulation Waveforms

9.2.3 Pulse-Position Modulation

triangular-wave modulation signal for such a circuit; however, any wave shape could be used.

Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 20. Circuit for Pulse-Position Modulation

9.2.3.1 Design Requirements

capacitor. Both frequency and duty cycle will vary with the modulation voltage.

9.2.3.2 Detailed Design Procedure

improves VOH, but it is not required for TTL compatibility.

16 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0.

9.2.3.3 Application Curves

Figure 21. Pulse-Position-Modulation Waveforms

9.2.4 Sequential Timer

Figure 22. Sequential Timer Circuit

9.2.4.1 Design Requirements

9.2.4.2 Detailed Design Procedure

The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C.

9.2.4.3 Application Curves

Figure 23. Sequential Timer Waveforms

10 Power Supply Recommendations

18 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.2 Trademarks

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.4 Glossary

This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser based versions of this data sheet, refer to the left hand navigation.

www.ti.com 26-Oct-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JM38510/10901BPA ACTIVE CDIP JG 8 50 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510 /10901BPA Samples NA555D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 105 NA555 NA555DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 Samples NA555P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 105 NA555P Samples NA555PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 NA555P Samples NE555D OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 NE555 NE555DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 NE555 Samples NE555DR1G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM NE555 Samples NE555DRG4 OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 NE555 NE555P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU | SN N / A for Pkg Type 0 to 70 NE555P Samples NE555PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 NE555P Samples NE555PS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM N555 Samples NE555PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 N555 Samples NE555PW OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70 N555 NE555PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 N555 Samples SA555D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 SA555 SA555DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 SA555 Samples SA555DRG4 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 SA555 SA555P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SA555P Samples SE555D OBSOLETE SOIC D 8 TBD Call TI Call TI -55 to 125 SE555 SE555DG4 OBSOLETE SOIC D 8 TBD Call TI Call TI -55 to 125 SE555 SE555DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 Samples Addendum-Page 1

www.ti.com 26-Oct-2024 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SE555DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 Samples SE555FKB ACTIVE LCCC FK 20 55 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SE555FKB Samples SE555JG ACTIVE CDIP JG 8 50 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SE555JG Samples SE555JGB ACTIVE CDIP JG 8 50 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SE555JGB Samples SE555P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 SE555P Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2

www.ti.com 26-Oct-2024 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SE555, SE555M :

• Catalog : SE555
• Military : SE555M
• Space : SE555-SP , SE555-SP NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NA555DR SOIC D 8 2500 353.0 353.0 32.0 NE555DR SOIC D 8 2500 353.0 353.0 32.0 NE555DR1G4 SOIC D 8 2500 353.0 353.0 32.0 NE555PSR SO PS 8 2000 356.0 356.0 35.0 NE555PWR TSSOP PW 8 2000 356.0 356.0 35.0 SA555DR SOIC D 8 2500 353.0 353.0 32.0 SE555DR SOIC D 8 2500 350.0 350.0 43.0 SE555DRG4 SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) NA555P P PDIP 8 50 506.1 9 600 5.4 NA555P P PDIP 8 50 506 13.97 11230 4.32 NA555PE4 P PDIP 8 50 506 13.97 11230 4.32 NE555P P PDIP 8 50 506 13.97 11230 4.32 NE555P P PDIP 8 50 506.1 9 600 5.4 NE555PE4 P PDIP 8 50 506 13.97 11230 4.32 NE555PS PS SOP 8 80 530 10.5 4000 4.1 SA555P P PDIP 8 50 506 13.97 11230 4.32 SE555FKB FK LCCC 20 55 506.98 12.06 2030 NA SE555P P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE 10.16 9.00 7.11 6.22 1.60 0.38 6X 2.54 8X 0.58 0.38 4X 1.65 1.14 0.51 MIN 3.30 MIN

5.08 MAX

7.87 7.37 0.36

0.20 TYP

4X (0.94) CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package can be hermetically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification. 5. Falls within MIL STD 1835 GDIP1-T8 SEATING PLANE

0.25 C A B

A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

(7.62) 6X (2.54) 8X ( 1) THRU 7X ( 1.6) (1.6) (R0.05) TYP CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 LAND PATTERN EXAMPLE NON SOLDER MASK DEFINED SCALE: 9X SOLDER MASK OPENING TYP METAL TYP SYMM SYMM 4 5

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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