NE555DR UMW | Alldatasheet
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Technical content
S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î NE555 Precision Timers
1 Features 3 Description
These devices are precision timing circuits capable of 1• Timing From Microseconds to Hours producing accurate time delays or oscillation. In the• Astable or Monostable Operation time-delay or mono-stable mode of operation, the
- Adjustable Duty Cycle timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode• TTL-Compatible Output Can Sink or Source of operation, the frequency and duty cycle can beUp to 200 mA controlled independently with two external resistors• On Products Compliant to MIL-PRF-38535, and a single external capacitor.All Parameters Are Tested Unless Otherwise The threshold and trigger levels normally are two-Noted. On All Other Products, Production thirds and one-third, respectively, of VCC. TheseProcessing Does Not Necessarily Include levels can be altered by use of the control-voltageTesting of All Parameters. terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If2 Applications the trigger input is above the trigger level and the
- Fingerprint Biometrics threshold input is above the threshold level, the flip- flop is reset and the output is low. The reset (RESET)• Iris Biometrics input can override all other inputs and can be used to• RFID Reader initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
4 Simplified Schematic
R UMW NE555w ww.umw-ic.com 1 友台半导体有限公司
V CC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW)
6 Pin Configuration and Functions
D, P, PS, FK I/O DESCRIPTIONPW, JGNAME NO. Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitorCONT 5 12 I/O connection DISCH 7 17 O Open collector output to discharge timing capacitor GND 1 2 – Ground 1, 3, 4, 6, 8, 9, 11, 13,NC – No internal connection14, 16, 18, OUT 3 7 O High current timer output signal RESET 4 10 I Active low reset input forces output and discharge low. THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V) UMW R UMW NE555w ww.umw-ic.com 2 友台半导体有限公司
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage(2) 18 V VI Input voltage CONT, RESET, THRES, TRIG VCC V IO Output current ±225 mA D package 97 P package 85 θJA Package thermal impedance(3)(4) °C/W PS package 95 PW package 149 FK package 5.61 θJC Package thermal impedance(5)(6) °C/W JG package 14.5 TJ Operating virtual junction temperature 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (6) The package thermal impedance is calculated in accordance with MIL-STD-883.
7.2 Handling Ratings
PARAMETER DEFINITION MIN MAX UNIT Tstg Storage temperature range –65 150 °C
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT NA555, NE555, SA555 4.5 16 VCC Supply voltage V SE555 4.5 18 VI Input voltage CONT, RESET, THRES, and TRIG VCC V IO Output current ±200 mA NA555 –40 105 NE555 0 70 TA Operating free-air temperature °C SA555 –40 85 SE555 –55 125 UMW R UMW NE555w ww.umw-ic.com 3 友台半导体有限公司
7.4 Electrical Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555 PARAMETER TEST CONDITIONS UNITSA555 MIN TYP MAX MIN TYP MAX VCC = 15 V 9.4 10 10.6 8.8 10 11.2 THRES voltage level V THRES current(1) 30 250 30 250 nA 4.8 5 5.2 4.5 5 5.6 VCC = 15 V TA = –55°C to 125°C 3 6 TRIG voltage level V VCC = 5 V TA = –55°C to 125°C 1.9 TRIG current TRIG at 0 V 0.5 0.9 0.5 2 μA 0.3 0.7 1 0.3 0.7 1 RESET voltage level V TA = –55°C to 125°C 1.1 RESET at VCC 0.1 0.4 0.1 0.4 RESET current mA RESET at 0 V –0.4 –1 –0.4 –1.5 DISCH switch off-state 20 100 20 100 nAcurrent DISCH switch on-state VCC = 5 V, IO = 8 mA 0.15 0.4 Vvoltage 9.6 10 10.4 9 10 11 VCC = 15 V VCC = 5 V TA = –55°C to 125°C 2.9 3.8 0.1 0.15 0.1 0.25 VCC = 15 V, IOL = 10 mA TA = –55°C to 125°C 0.2 0.4 0.5 0.4 0.75 VCC = 15 V, IOL = 50 mA TA = –55°C to 125°C 1 2 2.2 2 2.5 VCC = 15 V, IOL = 100 mA Low-level output voltage TA = –55°C to 125°C 2.7 V VCC = 15 V, IOL = 200 mA 2.5 2.5 VCC = 5 V, IOL = 3.5 mA TA = –55°C to 125°C 0.35 0.1 0.2 0.1 0.35 VCC = 5 V, IOL = 5 mA TA = –55°C to 125°C 0.8 VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4 13 13.3 12.75 13.3 VCC = 15 V, IOH = –100 mA TA = –55°C to 125°C 12 High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V 3 3.3 2.75 3.3 VCC = 5 V, IOH = –100 mA TA = –55°C to 125°C 2 VCC = 15 V 10 12 10 15 Output low, No load VCC = 5 V 3 5 3 6 Supply current mA VCC = 15 V 9 10 9 13 Output high, No load VCC = 5 V 2 4 2 5 (1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ. UMW R UMW NE555w ww.umw-ic.com 4 友台半导体有限公司
7.5 Operating Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555TESTPARAMETER UNITSA555CONDITIONS(1) MIN TYP MAX MIN TYP MAX Each timer, monostable(3) TA = 25°C 0.5 1.5(4) 1 3Initial error of timing %interval(2) Each timer, astable(5) 1.5 2.25 Each timer, monostable(3) TA = MIN to MAX 30 100(4) 50Temperature coefficient of ppm/ timing interval °CEach timer, astable(5) 90 150 CL = 15 pF,Output-pulse rise time 100 200(4) 100 300 nsTA = 25°C CL = 15 pF,Output-pulse fall time 100 200(4) 100 300 nsTA = 25°C (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 μF. (4) On products compliant to MIL-PRF-38535, this parameter is not production tested. (5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 μF. UMW R UMW NE555w ww.umw-ic.com 5 友台半导体有限公司
7.6 Typical Characteristics
Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. Figure 1. Low-Level Output Voltage Figure 2. Low-Level Output Voltage Figure 3. Low-Level Output Voltage Figure 4. Drop Between Supply Voltage and Output Figure 5. Supply Current Figure 6. Normalized Output Pulse Duration
S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
8 Detailed Description
8.1 Overview
The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC.
8.2 Functional Block Diagram
A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES.
8.3 Feature Description
8.3.1 Mono-stable Operation
For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. UMW R UMW NE555w ww.umw-ic.com 8 友台半导体有限公司
Pin numbers shown are for the D, JG, P, PS, and PW packages.
8.3.2 A-stable Operation
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms
Figure 14. Free-Running Frequency
8.3.3 Frequency Divider
Figure 15. Divide-by-Three Circuit Waveforms
8.4 Device Functional Modes
Table 1. Function Table (1) Voltage levels shown are nominal.
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
9 Applications and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
operating frequency. This section presents a simplified discussion of the design process.
9.2 Typical Applications
9.2.1 Missing-Pulse Detector
pulse as shown in Figure 17. Figure 16. Circuit for Missing-Pulse Detector
9.2.1.1 Design Requirements
9.2.1.2 Detailed Design Procedure
Pin numbers shown are for the D, JG, P, PS, and PW packages.
9.2.1.3 Application Curves
Figure 17. Completed Timing Waveforms for Missing-Pulse Detector
9.2.2 Pulse-Width Modulation
signal is shown, any wave shape could be used. Figure 18. Circuit for Pulse-Width Modulation
9.2.2.1 Design Requirements
9.2.2.2 Detailed Design Procedure
9.2.2.3 Application Curves
Figure 19. Pulse-Width-Modulation Waveforms
9.2.3 Pulse-Position Modulation
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 20. Circuit for Pulse-Position Modulation
9.2.3.1 Design Requirements
capacitor. Both frequency and duty cycle will vary with the modulation voltage.
9.2.3.2 Detailed Design Procedure
improves VOH, but it is not required for TTL compatibility.
Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0.
9.2.3.3 Application Curves
Figure 21. Pulse-Position-Modulation Waveforms
9.2.4 Sequential Timer
Figure 22. Sequential Timer Circuit
9.2.4.1 Design Requirements
9.2.4.2 Detailed Design Procedure
The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C.
9.2.4.3 Application Curves
Figure 23. Sequential Timer Waveforms