NE5410 PHILIPS | Alldatasheet

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Philips Semiconductors Linear Products Product specification NE/SE541010-Bit high-speed multiplying D/A converter 767August 31, 1994 853-0945 13721

DESCRIPTION

The NE5410/SE5410 are 10-bit Multiplying Digital-to-Analog Converters pin- and function-compatible with the industry-standard MC3410, but with improved performance. These are capable of high-speed performance, and are used as general-purpose building blocks in cost effective D/A systems. The NE/SE5410 provides complete 10-bit accuracy and differential non-linearity over temperature, and a wide compliance voltage range. Segmented current sources, in conjunction with an R/2R DAC, provide the binary weighted currents. The output buffer amplifier and voltage reference have been omitted to allow greater speed, lower cost, and maximum user flexibility.

FEATURES

  • Pin- and function-compatible with MC3410
  • 10-bit resolution and accuracy (±0.05%)
  • Guaranteed differential non-linearity over temperature
  • Wide compliance voltage range—-2.5 to +2.5V
  • Fast settling time—250ns typical
  • Digital inputs are TTL- and CMOS-compatible
  • High-speed multiplying input slew rate—20mA/µs
  • Reference amplifier internally-compensated
  • Standard supply voltages +5V and -15V

APPLICATIONS

  • Successive approximation A/D converters
  • High-speed, automatic test equipment
  • High-speed modems
  • Waveform generators
  • CRT displays
  • Strip CHART and X-Y plotters
  • Programmable power supplies
  • Programmable gain and attenuation PIN CONFIGURATION 8 9 F Package TOP VIEW VEE GND OUTPUT D 1 (MSB) D 2 D 3 D 4 D 5 VREF + D 10 (LSB) D 9 D 8 D 7 D 6 VREF – VCC BLOCK DIAGRAM MSB LSB 4 5 6 7 8 9 10 11 12 13 CURRENT SWITCHES LADDER TERMINATORS R-2R LADDER BIAS CIRCUITRY REFERENCE CURRENT AMPLIFIER GND 1 2 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 VREF(+) VREF(–) VCC IO VEE

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 16-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C NE5410F 0582B 16-Pin Ceramic Dual In-Line Package (CERDIP) -55 to +125°C SE5410F 0582B

Philips Semiconductors Linear Products Product specification NE/SE541010-Bit high-speed multiplying D/A converter August 31, 1994 768 ABSOLUTE MAXIMUM RATINGS TA=+25°C, unless otherwise specified. SYMBOL PARAMETER RATING UNIT VCC Power supply +7.0 VDC VEE -18 VDC VI Digital input voltage +15 VDC VO Applied output voltage +4, -5.0 VDC IREF(16) Reference current 2.5 mA VREF Reference amplifier inputs VCC , VEE VDC VREF(D) Reference amplifier differential inputs 0.7 VDC TA Operating temperature range SE5410 -55 to +125 °C NE5410 0 to +70 °C TJ Junction temperature Ceramic package +150 °C TSTG Storage temperature -65 to +150 °C PD Maximum power dissipation TA=25°C (still-air)1 1190 mW NOTES: 1. Derate above 25°C at the following rate: F package at 9.5mW/°C DC ELECTRICAL CHARACTERISTICS (Continued) VCC =+5.0VDC , VEE =-15VDC , IREF =2.0mA, all digital inputs at high logic level. SE5410: TA=-55°C to +125°C, NE5410 Series: TA=0°C to +70°C, unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT ∈ R Relative accuracy Over Temperature ±0.025 ±0.05 % ∈ R (Error relative to full scale IO ) ±1/4 ±1/2 LSB Differential non-linearity Over temperature ±0.025 ±0.05 % ±1/4 ±1/2 LSB tS Settling time to within ±1/2 LSB (all bits low to high) TA = 25°C 250 ns tPLH tPHL Propagation delay time TA = 25°C 35 20 ns TCIO Output full-scale current drift 20 40 ppm/°C VIH Digital input logic levels (all bits) High level, Logic “1” Low level, Logic “0” 2.0 0.8 VDC IIH IIL Digital input current (all bits) High level, VIH = 5.5V Low level, VIL = 0.8V –20 µA IREF(15) Reference input bias current (Pin 15) –1.0 –5.0 µA IOH Output current (all bits high) VREF = 2.000V, R16 = 1000Ω 3.937 3.996 4.054 mA IOL Output currents (all bits low) TA = 25°C 0 0.4 µA VO Output voltage compliance TA = 25°C ∈ R < 0.050% relative to full-scale –2.5 +2.5 VDC SR IREF Reference amplifier slew rate 20 mA/µs ST IREF Reference amplifier settling time 0 to 4.0mA, ±0.1% 2.0 µs PSRR(–) Output current power supply sensitivity 0.003 0.01 %/% C O Output capacitance VO = 0 25 pF

Connections for a positive reference voltage are shown in Figure 6a. positive input level at Pin 15. half what it is in the case of R16=1.0kΩ , and settling time is ±10µs. source is 0.5mA for stability. Figure 5. NE5410 Equivalent Circuit

Figure 6. Basic Connections voltage may be reduced if VEE >-15V. current drift with temperature. with a reference current of 2.0mA on Pin 16. current remains above 0.5mA. approximately the same time as when all bits are switched off-to-on. to swing to -2.5V, the settling time increases to 1.5µs. lead length are all necessary. A typical test setup for measuring settling time is shown in Figure 7.

Figure 11. Successive Approximation A/D Converter 10-bit conversion time = 3.3µs with 3MHz clock.

2504 SAR

Figure 12. 8-Bit µP Bus Interface With this double latch technique, valid data will be latched to the DAC until updated with the E2 pulse. Timing will depend on the processor used.

Figure 13. Staircase A/D