SE370C777AFZT

TMS370CX7X_09 TI1 | Alldatasheet

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SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume Production – One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production – Reprogrammable EPROM Devices for Prototyping Purposes /C0068Internal System Memory Configurations – On-Chip Program Memory Versions – ROM: 24K Bytes – EPROM: 24K Bytes – Data EEPROM: 256 Bytes – Static RAM: 512 Bytes /C0068Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options: – Divide-by-4 (0.5 MHz – 5 MHz SYSCLK) – Divide-by-1 (2 MHz – 5 MHz SYSCLK) Phase-Locked Loop (PLL) – Supply Voltage (V CC ): 5 V ± 10% /C0068Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1) /C0068TMS370 Series Compatibility – Instructions Upwardly Compatible With All TMS370 Devices – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes /C0068Two 16-Bit General-Purpose Timers /C0068On-Chip 24-Bit Watchdog Timer /C0068Flexible Interrupt Handling /C0068CMOS/Package /TTL-Compatible I/O Pins – 64-Pin Plastic and Ceramic Shrink Dual-In-Line Packages /44 Bidirectional,

9 Input Pins

– 68-Pin Plastic and Ceramic Leaded Chip Carrier Packages /46 Bidirectional, – All Peripheral Function Pins Are Software Configurable for Digital I/O /C0068Workstation/PC-Based Software Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FN/FZ PACKAGE (TOP VIEW) VSS1 MC T2AIC1/CR XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT 9876543 VCC2 VSS2 VCC1 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V CC3 V SS3 V CC1 V CC2 VSS2 T2AEVT T2AIC2/PWM INT1 / NMI INT2 INT3 D3/SYSCLK RESET AN0 / E0 AN1 / E1 AN2 / E2 AN3 / E3 AN4 / E4 AN5 / E5 AN6 / E6 AN7 / E7 JN/NM PACKAGE (TOP VIEW) 32 33 64B5 MC V SS1 T2AEVT T2AIC2 / PWM T2AIC1 / CR XTAL2 / CLKIN XTAL1 VCC1 VCC3 V SS1 VCC1 D3/SYSCLK RESET INT1 / NMI INT2 INT3 T1IC / CR T1PWM AN7 / E7 T1EVT V SS1 AN6 / E6 AN5 / E5 AN4 / E4 AN3 / E3 AN1 / E1 AN2 / E2 V SS3 AN0 / E0 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated

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ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ PIN ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ SDIP (64) ÁÁÁ ÁÁÁ LCC (68) ÁÁÁ ÁÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port A is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port B is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port C is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ INT1/NMI INT2 INT3 ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ I I/O I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7) Port E can be programmed individually as general-purpose input pins if not used as ADC1 analog input or positive reference input. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VCC3 VSS3 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin ÁÁÁÁÁ ÁÁÁÁÁ RESET ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System reset bidirectional pin. As an input, RESET initializes the microcontroller; as open-drain out- put, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ MC ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode control (MC) pin. MC enables EEPROM write-protection-override (WPO) mode, also EPROM VPP. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ XTAL2/CLKIN XTAL1 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Internal oscillator crystal input/external clock source input Internal oscillator output for crystal ÁÁÁÁÁ ÁÁÁÁÁ VCC1 ÁÁÁ ÁÁÁ 31, 57 ÁÁÁ ÁÁÁ 33, 61 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage ÁÁÁÁÁ ÁÁÁÁÁ VCC2 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 15,63 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage for digital I/O † I = input, O = output

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Descriptions (Continued) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ PIN ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ SDIP (64) ÁÁÁ ÁÁÁ LCC (68) ÁÁ ÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VSS1 ÁÁÁ Á Á Á ÁÁÁ 58,40 ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ground reference for digital logic ÁÁÁÁÁ ÁÁÁÁÁ VSS2 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 16,62 ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ground reference for digital I/O logic ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ D3/SYSCLK ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port D is a general-purpose bidirectional I/O port. D3 also can be configured as SYSCLK. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port G is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ T1IC/CR T1PWM T1EVT ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer1 input capture/counter-reset input pin/general-purpose bidirectional pin Timer1 pulse-width-modulation (PWM) output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ T2AIC1/CR T2AIC2/PWM T2AEVT ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ ÁÁ ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer2A input capture 1/counter reset input pin/general-purpose bidirectional pin Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer2A external event input pin/general-purpose bidirectional pin † I = input, O = output

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ROM: 24K Bytes EPROM: 24K Bytes VSS1 VCC1 RESETMCXTAL2/ CLKIN XTAL1INT3INT2INT1 E0–E7 or AN0–AN7 VCC2 ‡VSS2 ‡ RAM

512 BytesCPU

A-to-D Converter 1System Control Clock Options: Divide-by-4 or Divide-by-1(PLL) T1PWM T1EVT T1IC/CR T2AIC2/PWM T2AEVT T2AIC1/CR VSS3 VCC3 Port A Interrupts Port G Port D† Data EEPROM

256 Bytes

† For the 64-pin devices, there are only six pins for port D. ‡ For the 64-pin devices, omit these power pins The TMS370C077, TMS370C777, and SE370C777 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx7x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx7x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx7x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. All TMS370Cx7x devices contain the following on-chip peripheral modules: /C0068Eight-channel, 8-bit analog-to-digital converter 1 (ADC1) /C0068One 24-bit general-purpose watchdog timer /C0068Two 16-bit general-purpose timers (one with an 8-bit prescaler)

Table 1 provides a memory configuration overview of the TMS370Cx7x devices. Table 1. Memory Configurations

64 PIN PSDIP/CSDIP

† System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized. configuration of the device. ROM and EPROM devices have a different configuration as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 2. Suffix Letter Configuration ‡ Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering. mask charge or cycle time for the low-cost mask-ROM device is not practical. breadboards and prototype systems while iterating initial designs.

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description (continued) The TMS370Cx7x family provides the system designer with very economical, efficient solutions to real-time control applications. The TMS370 family compact development tool (CDT ) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx7x into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of personal-computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle. The TMS370Cx7x family, together with the TMS370 family CDT370, starter kit, software tools, the SE370C777 reprogrammable device, comprehensive product documentation, and customer support, provide a complete solution to the needs of the system designer. CPU The CPU used on TMS370Cx7x devices is the high-performance 8-bit TMS370 CPU module. The ’x7x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x7x instruction set is summarized in Table 17. Figure 1 illustrates the CPU registers and memory blocks. CDT is a trademark of Texas Instruments Incorporated.

015 Program Counter (PC)

7 Legend:

† Reserved means that the address space is reserved for future expansion. ‡ Not available means that the address space is not accessible. Figure 1. Programmer’s Model

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256 bytes of the on-chip RAM memory. the conditional jump instructions) use these status bits to determine program flow. /C0068The two interrupt-enable bits control the two interrupt levels. The ST register and status-bit notation are shown in Table 3. Table 3. Status Register

registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address. 2000h as the contents of memory locations 7FFEh and 7FFFh (reset vector). Figure 2. Program Counter After Reset EEPROM, EPROM, input/output pins, peripheral functions, and system-interrupt vectors. peripheral file frames 1 through 7, addresses 1010h through 107Fh.

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1040h–104FhTimer 1 Peripheral Contr. 1060h–106FhTimer 2A Peripheral Contr. 1070h–107FhADC1 Peripheral Contr. † Reserved = the address space is reserved for future expansion. ‡ Not available = address space is unavailable in the mode illustrated. Figure 3. TMS370Cx7x Memory Map 256 bytes of RAM (0000h – 00FFh) are the register files, R0 through R255. stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 peripheral file (PF) The TMS370Cx7x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the peripheral file (PF) directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator, or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 shows the TMS370Cx7x peripheral files. Table 4. TMS370Cx7x Peripheral File Address Map ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1000h–100Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P000–P00F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved for factory test ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010h–101Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P010–P01F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System and EEPROM/EPROM control registers ÁÁÁÁÁÁÁ 1020h–103Fh ÁÁÁÁÁÁÁ P020–P03F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital I/O port control registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1040h–104Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P040–P04F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1050h–105Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P050–P05F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1060h–106Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P060–P06F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 2A registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1070h–107Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P070–P07F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog-to-digital converter 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1080h–10FFh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P080–P0FF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved data EEPROM The TMS370Cx7x devices contain 256 bytes of data EEPROM, and have a memory map beginning at location 1F00h, and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User’s Guide (literature number SPNU127), or the TMS370 Family Data Manual (SPNS014B). The data EEPROM features include the following: /C0068Programming: – Bit, byte, and block write/erase modes – Internal charge pump circuitry: No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register (DEECTL) located in the PF frame beginning at location P01A. – In-circuit programming capability: There is no need to remove the device to program. /C0068Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation /C0068Write protection can be overridden by applying 12 V to MC. Table 5 shows the memory map of the control registers.

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Table 5. Data EEPROM and Program EPROM Control Registers Memory Map †F o r the 24K-byte EPROM device, the program memory is controlled by P01C and P01E. at address locations 6000h through 7FFFh, as shown in Table 6. Table 6. TMS370C777 EPROM Memory Map 101Eh (P01E), and the 8K-byte array is controlled by register EPCTLM located at 101Ch (P01C). EPCTLL and EPCTLM, located at the addresses in PF frame 1 as shown in Table 5. – Reset: All programming to the EPROM module is halted. located between addresses 7FC0h and 7FDFh. TI is a trademark of Texas Instruments Incorporated.

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx7x CPU-based device. Family Data Manual (SPNS014B) for more information. (SPNS014B) for more information. low, then the reset logic holds the device in a reset state for as long as these actions are active. of the reset. A reset does not clear these flags. Table 7 lists the reset sources. Table 7. Reset Sources

1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).
2. Registers A and B initialize to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to by the PC.

register bits are initialized to their reset state.

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The TMS370 family software programmable interrupt structure permits flexible on-chip and external-interrupt configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of the status register. Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx7x has six hardware-system interrupts (plus RESET ) as shown in Table 8. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. All of the interrupt sources are maskable individually by local interrupt-enable control bits in the associated peripheral file (PF). Each interrupt source FLAG bit is readable individually for software polling or for determining which interrupt source generated the associated system interrupt. The interrupt-control block diagram is illustrated in Figure 4.

Figure 4. Interrupt Control INT1, INT2, and INT3 control registers in PF frame 1.

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Table 8. Hardware System Interrupts nonprivileged mode and must be configured by software prior to exiting the privileged mode.

Table 9. Privileged Bits † The privileged bits are shown in a bold typeface in the peripheral file frame 1 section. pin (normally not available in the end application except in a service or diagnostic environment). time when the mask is manufactured. is entered by executing the idle instruction when the PWRDWN/IDLE bit in register SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered. , external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected. In the HALT mode (HALT/STANDBY = 1), the TMS370Cx7x is placed in its lowest power-consumption mode. or an external interrupt on INT1, INT2, INT3) is detected. The low-power mode selection bits are summarized in Table 10.

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Table 10. Low-Power/Idle Control Bits through a programmable contact, the device always enters the IDLE mode. that the NMI always is generated, regardless of the interrupt enable flags. STANDBY and HALT modes, the clocking of the watchdog timer is inhibited. devices have the divide-by-4 option. low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. steeper decay of emissions produced by the oscillator.

privileged bits are bold typefaced and shaded. Table 11. Peripheral File Frame 1: System Configuration Registers

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Table 12. Peripheral File Frame 2: Digital Port Control Registers † To configure pin D3 as SYSCLK, set port D control register 2 = 08h. Table 13. Port Configuration Register Setup

block diagram is shown in Figure 5. Figure 5. Timer 1 Block Diagram capture or compare register. if watchdog feature is not needed.

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timer 1 (T1) module (continued) /C0068Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR). /C0068Interrupts that can be generated on the occurrence of: – A capture – A compare equal – A counter overflow – An external edge detection /C0068Sixteen T1 module control registers: Located in the PF frame beginning at address P040 Table 14 lists the T1 module control register.

Table 14. Timer 1 Module Register Memory Map

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bit 0, in the T1CTL2 register. Figure 6. Capture/Compare Mode

bit 0, in the T1CTL2 register. Figure 7. Dual-Compare Mode

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software programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used. WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value). The WD can be configured as one of the three mask options: standard WD, hard WD, or simple counter. Figure 8. Standard Watchdog

Figure 9. Hard Watchdog

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– Simple counter can be configured as an event counter, pulse accumulator, or an interval timer. Figure 10. Simple Counter diagram is shown in Figure 11.

Figure 11. Timer 2A Block Diagram

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The T2A module control registers are listed in Table 15. Table 15. Timer 2A Module Register Memory Map

106Bh, bit 0, in the T2ACTL2 register. Figure 12. Dual-Compare Mode

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Figure 13. Dual-Capture Mode

/C0068Six ADC1 module control registers are located in the control register frame beginning at address 1070h. The ADC1 module control registers are listed in Table 16. Table 16. ADC1 Module Control Register Memory Map

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The ADC1 module block diagram is illustrated in Figure 14. Figure 14. ADC1 Block Diagram

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction set overview Table 17 provides an opcode-to-instruction cross reference of all 73 instructions and 274 opcodes of the ‘370Cx7x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.

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Table 17. TMS370 Family Opcode/Instruction Map† instructions have a relative address as the last operand.

Table 17. TMS370 Family Opcode/Instruction Map† (Continued) instructions have a relative address as the last operand.

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development system support The TMS370 family development support tools include an assembler, a C compiler, a linker, compact development tool, and an EEPROM/UVEPROM programmer. /C0068Assembler/linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Provides high-speed operation – Provides format conversion utilities for popular formats /C0068ANSI C compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3 , or Sun-4 ) – Generates assembly code for the TMS370 that can be easily inspected – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct referencing of the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker /C0068CDT370 (compact development tool) Timer real-time in-circuit emulation – Base (Part Number EDSCDT37T – for PC, requires cable) – Cable for 68-pin PLCC (Part No. EDSTRG68PLCC) – Cable for 64-pin SDIP (Part No. EDSTRG64SDIL) – Includes EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Uploads/downloads program and data memory – Executes programs and software routines – Includes 1024 samples trace buffer – Includes single-step executable instructions – Uses software breakpoints to halt program execution at selected address /C0068Microcontroller programmer – Base (Part No. TMDS3760500A — for PC, requires programmer head) – Single unit head for 68-pin PLCC (Part No. TMDS3780510A) – Single unit head for 64-pin SDIP (Part No. TMDS3780511A) – Includes PC-based, window/function-key oriented user interface for ease of use and rapid learning environment HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

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Table 18. Device Part Numbers reliability has not been characterized.

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Table 19 is a collection of all the peripheral file frames using the ’Cx7x (provided for a quick reference). Table 19. Peripheral File Frame Compilation † To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 19. Peripheral File Frame Compilation (Continued) and to simple counter. The WD input select 2 bits are ignored.

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SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 45POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ VCC1 = VCC§ Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. NOTE 1: Unless otherwise noted, all voltage values are with respect to VSS1 . recommended operating conditions MIN NOM MAX UNIT VCC1 Supply voltage (see Note 1) 4.5 5 5.5 VVCC1 RAM data-retention supply voltage (see Note 2) 3 5.5 V VCC2 Digital I/O supply voltage (see Note 1) 4.5 5 5.5 V VCC3 Analog supply voltage (see Note 1) 4.5 5 5.5 V VSS2 Digital I/O supply ground – 0.3 0 0.3 V VSS3 Analog supply ground – 0.3 0 0.3 V VIL Low level input voltage All pins except MC VSS1 0.8 V VIL Low-level input voltage MC, normal operation VSS1 0.3 V All pins except MC, XTAL2/CLKIN, and RESET 2 VCC VIH High-level input voltage MC (non-WPO mode) VCC1 –0.3 VCC1 +0.3 VIH gg XTAL2/CLKIN 0.8 VCC1 VCC1 RESET 0.7 VCC1 VCC1 EEPROM write protect override (WPO) 11.7 12 13 VMC MC (mode control) voltage EPROM programming voltage (VPP ) 13 13.2 13.5 VVMC () g (see Note 3) Microprocessor VCC1 –0.3 VCC1 +0.3 V Microcomputer VSS1 0.3 L version 0 70 TA Operating free-air temperatureA version – 40 85 °C T version – 40 105 NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS1 . 2. RESET must be activated externally when VCC1 or SYSCLK is out of the recommended operating range. 3. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system clock cycles (tc) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is present on MC.

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage IOL = 1.4 mA 0.4 V VOH High level output voltage IOH = –50 mA 0.9 VCC1 VVOH High-level output voltage IOH = –2 mA 2.4 V 0 V < VI ≤ 0.3 V 10 0.3 V < VI < VCC1 –0.3 V 50 mA II Input current MC VCC1 –0.3 V ≤ VI ≤ VCC1 +0.3 V 10 mA II Input current VCC1 + 0.3 V < VI ≤ 13 V 650

12 V ≤ VI ≤ 13 V See Note 4 50 mA

I/O pins 0 V ≤ VI ≤ VCC1 ± 10 mA IOL Low-level output current VOL = 0.4 V 1.4 mA IOH High level output current VOH = 0.9 VCC1 – 50 mA IOH High-level output current VOH = 2.4 V – 2 mA SYSCLK = 5 MHz 35 56See Notes 5 and 6 35 56 Supply current (operating mode) SYSCLK = 3 MHz 25 36 mAy(g ) OSC POWER bit = 0 (see Note 7) See Notes 5 and 6 25 36 mA SYSCLK = 0.5 MHz 13 18See Notes 5 and 6 13 18 SYSCLK = 5 MHz See Notes 5 and 6 12 17 ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 8) SYSCLK = 3 MHz See Notes 5 and 6 8 11 mA SYSCLK = 0.5 MHz See Notes 5 and 6 2.5 3.5 Supply current (STANDBY mode) SYSCLK = 3 MHz See Notes 5 and 6 6 8.6 mAy( ) OSC POWER bit = 1 (see Note 9) SYSCLK = 0.5 MHz See Notes 5 and 6 2 3 mA Supply current (HALT mode) XTAL2/CLKIN < 0.2 V See Note 5 2 30 mA NOTES: 4. Input current IPP is a maximum of 50 mA only when programming EPROM. 6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 7. Maximum operating current for TMS370Cx7x = 10 (SYSCLK) + 5.8 mA. 8. Maximum standby current for TMS370Cx7x = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

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All timings are measured between high and low measurement points as indicated in Figure 20 and Figure 21.

0.8 V (Low)

2 V (High)

0.8 VCC V (High)

Figure 20. XTAL2/CLKIN Measurement Points Figure 21. General Measurement Points

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Figure 24. Signal Switching Timing NOTE 11: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

Figure 25. SYSCLK Timing

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analog-to-digital converter 1 (ADC1) The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC1 performance by preventing digital switching noise in the logic circuitry that can be present on V SS1 and VCC1 when coupling into the A/D analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT VCC3 Analog supply voltage 4.5 5 5.5 VVCC3 Analog supply voltage VCC1 –0.3 VCC1 +0.3 V VSS3 Analog ground VSS1 –0.3 VSS1 +0.3 V Vref Non-VCC3 reference† 2.5 VCC3 VCC3 + 0.1 V Analog input for conversion VSS3 Vref V † Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time. operating characteristics over recommended ranges of operating conditions PARAMETER TEST CONDITIONS MIN MAX UNIT Differential/integral linearity error‡§ VCC3 = 5.5 V V rerf = 5.1 V ± 0.9 LSB ICC3 Analog supply current Converting 2 mA ICC3 Analog supply current Nonconverting 5 mA II Input current, AN0–AN7 0 V ≤ VI ≤ 5.5 V 2 mA Iref Input charge current 1 mA Z f Source impedance of Vf SYSCLK ≤ 3 MHz 24 kW Zref Source impedance of Vref 3 MHz < SYSCLK ≤ 5 MHz 10 kW ‡ Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. § Excluding quantization error of 1/2 LSB

signaling that a conversion has started and that the analog signal can be removed. † The value given is valid for a signal with a source impedance > 1 kW . If the source impedance is < 1 kW , use a minimum sampling time of 1ms. Figure 26. Analog Timing

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mechanical drawing by drawing number and name. Table 20. TMS370Cx7x Family Package Type and Mechanical Cross-Reference

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95

20 PIN SHOWN

0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

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FZ (S-CQCC-J) J-LEADED CERAMIC CHIP CARRIER 4040219/B 03/95 0.180 (4,57) 0.140 (3,55) C 0.020 (0,51) 0.032 (0,81)A B A B 0.025 (0,64) R TYP 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) MIN 0.090 (2,29) A MIN MAX 0.485 (12,32) (12,57) 0.495 0.455 (11,56)(10,92) 0.430 MAXMIN BC MIN MAX 0.410 (10,41) (10,92) 0.430 PINS NO. OFJEDEC MO-087AC MO-087AB MO-087AA OUTLINE

28 LEAD SHOWN

(at Seating Plane) 142 6 1812 5 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA JN (R-CDIP-T64) CERAMIC DUAL-IN-LINE PACKAGE 0.750 (19,05) 0.730 (18,54) 0.760 (19,30) 0.740 (18,80) 0.175 (4,45) TYP Seating Plane 0.072 (1,83) 0.088 (2,24) 4040224/A 09/95 0.012 (0,31) 0.009 (0,23) 0.040 (1,02) TYP 2.376 (60,35) 2.424 (61,57) 0.020 (0,51) 0.016 (0,41) See Note C 2.178 (55,32) 2.162 (54,91) 0.078 (1,98) 0.094 (2,39) 0.060 (1,52) 0.040 (1,02) 0.070 (1,78) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Each pin centerline located within 0.010 (0,26) of it true longitudinal position.

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58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NM (R-PDIP-T64) PLASTIC SHRINK DUAL-IN-LINE PACKAGE 0.740 (18,80) 0.760 (19,30) 0.670 (17,02) 0.680 (17,27) 0.010 (0,25) NOM Seating Plane 0.125 (3,18) MIN 4040056/B 05/95 0.020 (0,51) MIN 0.048 (1,216) 0.032 (0,816) 2.280 (57,91) MAX 0.022 (0,56) 0.014 (0,36) 0.222 (5,64) MAX 0.070 (1,78) M0.010 (0,25) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SE370C777AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C777AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI TMS370C777AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C777ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 Addendum-Page 1

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