TMS370C758B_12 TI1 | Alldatasheet
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SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume Production – One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production – Reprogrammable EPROM Devices for Prototyping Purposes /C0068Internal System Memory Configurations – On-Chip Program Memory Versions – ROM: 4K to 48K Bytes – EPROM: 16K to 48K Bytes – ROM-less – Data EEPROM: 256 or 512 Bytes – Static RAM: 256 to 3.5K Bytes – External Memory/Peripheral Wait States – Precoded External Chip-Select Outputs in Microcomputer Mode /C0068Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options – Divide-by-4 (0.5 MHz – 5 MHz SYSCLK) – Divide-by-1 (2 MHz – 5 MHz SYSCLK) Phase-Locked Loop (PLL) – Supply Voltage (V CC ): 5 V ± 10% /C0068Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1) /C0068Two 16-Bit General-Purpose Timers /C0068On-Chip 24-Bit Watchdog Timer /C0068Two Communication Modules – Serial Communications Interface 1 (SCI1) – Serial Peripheral Interface (SPI) /C0068Flexible Interrupt Handling /C0068TMS370 Series Compatibility /C0068CMOS/Package /TTL-Compatible I/O Pins – 64-Pin Plastic and Ceramic Shrink Dual-In-Line Packages/44 Bidirectional,
9 Input Pins
– 68-Pin Plastic and Ceramic Leaded Chip Carrier Packages/46 Bidirectional, – All Peripheral Function Pins Are Software Configurable for Digital I/O /C0068Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FN/FZ PACKAGE (TOP VIEW) VSS1 MC T2AIC1/CR SCICLK SCIRXD SCITXD XTAL2/CLKIN XTAL1 SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT 9876543 D0 / CSE2 / OCF VCC2 VSS2 VCC1 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V CC3 V SS3 V CC1 V CC2 VSS2 T2AEVT T2AIC2/PWM INT1 INT2 INT3 D1 / CSH3 D2 / CSH2 D3 / SYSCLK D 4/R/W D5 / CSPF D6/CSH1 /EDS D7/CSE1 /WAIT RESET AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 JN/NM PACKAGE (TOP VIEW) 32 33 64B5 MC VSS1 AN0 T2AEVT T2AIC2 / PWM T2AIC1 / CR SCICLK SCIRXD SCITXD XTAL2 / CLKIN XTAL1 V CC1 VCC3 D0 / CSE2 / OCF VSS1 VCC1 D1 / CSH3 D3 / SYSCLK D 4/R/W D6 / CSH1/ EDS D7 / CSE1/W A I T RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC / CR T1PWM AN7 T1EVT V SS1 AN6 AN5 AN4 AN3 AN1 AN2 VSS3
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁÁÁÁ ÁÁÁÁÁÁ ALTERNATE FUNCTION ÁÁÁ ÁÁÁ SDIP (64) ÁÁÁ ÁÁÁ LCC (68) ÁÁ ÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DESCRIPTION ‡ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ Á Á Á Á Á Á Á Á Á Á ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0–DATA7). ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ Á Á Á Á Á Á Á Á ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0–ADDR7). ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ Á Á Á Á Á Á Á Á ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8–ADDR15). ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ INT1 INT2 INT3 ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ NMI ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁ Á Á Á Á ÁÁ I I/O I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁ Á Á Á Á Á Á Á Á ÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7) Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ VCC3 VSS3 ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ RESET ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ Á Á ÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ MC ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ Á Á ÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ XTAL2/CLKIN XTAL1 ÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁ Á Á ÁÁ I O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Internal oscillator crystal input/external clock source input Internal oscillator output for crystal ÁÁÁÁÁ ÁÁÁÁÁ VCC1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ 31, 57 ÁÁÁ ÁÁÁ 33, ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage ÁÁÁÁÁ ÁÁÁÁÁ VCC2 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 15,63 ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage † I = input, O = output ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.
memory bank switching. Refer to Table 1 for function A memory accesses. I/O pin B: Opcode fetch goes low during the opcode fetch memory cycle. I/O pin A: Chip select half output 3 goes low during memory accesses. I/O pin A: Chip select half output 2 goes low during memory accesses. I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency. I/O pin A: Chip select half output 1 goes low during memory accesses. external memory and has the same timings as the five chip selects. I/O pin A: Chip select eighth output goes low during memory accesses. I/O pin B: Wait input pin extends bus signals. ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK. NOTE 1: The three-pin configuration SCI is referred to as SCI1. Table 1. Function A: Memory Accesses Locations for ‘x5x Devices
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ROM: 4K, 8K, 12K, 16K, 32K, or 48K Bytes EPROM: 16K, 32K, or 48K Bytes VSS1 VCC1 RESETMCXTAL2/ CLKIN XTAL1INT3INT2INT1 E0–E7 or AN0–AN7 VCC2VSS2 Data EEPROM 0, 256, or 512 Bytes RAM 256, 512, 1K, 1.5K, or 3.5K Bytes CPU Port D†Port CPort B Watchdog Timer 1 Timer 2A Serial Communications Interface 1 Serial Peripheral Interface Analog-to-Digital Converter 1System Control Clock Options: Divide-by-4 or Divide-by-1(PLL) T1PWM T1EVT T1IC/CR T2AIC2/PWM T2AEVT T2AIC1/CR SCICLK SCITXD SCIRXD SPICLK SPISIMO SPISOMI VSS3 VCC3 Port A Interrupts Memory Expansion Data Address LSbyte Address MSbyte Control † For the 64-pin devices, there are only six pins for port D.
description
The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families: the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x. The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory configuration overview of the TMS370Cx5x devices.
Table 2. Memory Configurations
68 PIN PLCC/CLCC, OR
64 PIN PSDIP/CSDIP
‡ TMS370C45x support ROM memory security. Refer to the program ROM section. ¶ System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
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configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 3. Suffix Letter Configuration † Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering. TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet. mask ROM devices is not practical. allow quick updates to breadboards and prototype systems while iterating initial designs. configuration bits throughout both low-power modes. drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I/O) pins when operating in the microcomputer mode. The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDS ) and compact development tool (CDT ) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family XDS development tools communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle. The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. modes The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list. /C0068Microcomputer single chip mode: – Operates as a self-contained microcomputer with all memory and peripherals on-chip. – Maximizes the general-purpose I/O capability for real-time control applications. /C0068Microcomputer with external expansion mode: – Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM, EPROM, and data EEPROM) remains active. – Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port control, to become external memory as follows: – Port A: 8-bit data memory – Port B and C: 16-bit address memory – Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O) – Utilizes the pins available (not used for address, data, or control memory) as general-purpose input/output by programming them individually. – Lowers the system cost by not requiring an external address/data latch (address memory and data memory are nonmultiplexed). XDS and CDT are trademarks of Texas Instruments Incorporated.
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modes (continued) – Reduces external interface decode logic by using the precoded chip select outputs that provide direct memory/peripheral chip select or chip enable functions. – Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2, CSH1 , CSH2, and CSH3 as memory-bank selects under software control. – Function B maps up to 40K bytes of external memory into the address space by using EDS under software control. /C0068Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations. /C0068Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external bus interface. – Application program in external memory enables the internal program ROM or EPROM to be active in the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control register accomplishes this.) memory/peripheral wait operation The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT -input pin. The CPU continues to wait as long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller. Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions and memory and peripheral accesses automatically, thus making every external access a minimum of three system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states can be used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost.
015 Program Counter
7 Legend:
† Reserved means the address space is reserved for future expansion. Figure 1. Programmer’s Model
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256 bytes of the on-chip RAM memory. the conditional-jump instructions) use these status bits to determine program flow. /C0068The two interrupt-enable bits control the two interrupt levels. The ST register, status bit notation, and status bit definitions are shown in Table 4. Table 4. Status Registers
registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address. 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector). Figure 2. Program Counter After Reset assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.
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† Reserved = the address space is reserved for future expansion. ‡ Not available (N/A) = address space unavailable in the mode illustrated. § Precoded chip select outputs available on external expansion bus. Figure 3. TMS370Cx5x Memory Map
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RAM/register file (RF) Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in Table 5 along with other ’x5x devices. Table 5. RAM Memory Map
256 Bytes
512 Bytes
is contained in register B. Registers A and B are the only registers cleared on reset. shows the TMS370Cx5x peripheral files. Table 6. TMS370Cx5x Peripheral File Address map ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1000h–100Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P000–P00F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved for factory test ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010h–101Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P010–P01F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System and EEPROM/EPROM control registers ÁÁÁÁÁÁÁ 1020h–102Fh ÁÁÁÁÁÁÁ P020–P02F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital I/O port control registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1030h–103Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P030–P03F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Serial peripheral interface registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1040h–104Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P040–P04F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1050h–105Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P050–P05F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Serial communication interface 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1060h–106Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P060–P06F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 2A registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1070h–107Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P070–P07F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog-to-digital converter 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1080h–10BFh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P080–P0BF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10C0h–10FFh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P0C0–P0FF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ External peripheral control data EEPROM The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices. Table 7. Data-EEPROM Memory Map
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– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. (DEECTL) located in the PF frame beginning at location P01A. – In-circuit programming capability: There is no need to remove the device to program it. – Reset: All programming of the data EEPROM module is halted. – Write protection active: There is one write-protect bit per 32-byte EEPROM block. /C0068Write protection can be overridden by applying 12 V to MC. Table 8 shows the memory map of the control registers. Table 8. Data EEPROM and Program EPROM Control Registers Memory Map is controlled by P014, P01C, and P01E. through DFFFh (see Figure 3).
second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C). controlled by EPCTLH, located at 1014h (P014). Table 9. EPROM Memory Map (EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8. – Reset: All programming to the EPROM module is halted. Table 10. ROM Memory Map interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. TI is a trademark of Texas Instruments Incorporated.
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The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device. number SPNS014B) for more information. SPNS014B) for more information. reset logic holds the device in a reset state for as long as these actions are active. of the reset. A reset does not clear these flags. Table 11 lists the reset sources. Table 11. Reset Sources
- The CPU registers initialize: ST = 00h, SP = 01h (reset state).
- Registers A and B initialize to 00h (no other RAM is changed).
- The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
- The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
- Program execution begins with an opcode fetch from the address pointed to by the PC.
goes inactive (refer to page 7 for operating modes description).
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the status register. Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx5x has nine hardware system interrupts (plus RESET ) as shown in Table 12. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4.
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Figure 4. Interrupt Control On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported. corresponding addresses, and hardware priorities.
Table 12. Hardware System Interrupts ‡ Releases microcontroller from STANDBY and HALT low-power modes. § Releases microcontroller from STANDBY low-power mode. mode and must be configured by software prior to exiting the privileged mode.
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Table 13. Privileged Bits † The privileged bits are shown in a bold typeface in Table 15. pin (normally not available in the end application except in a service or diagnostic environment). time when the mask is manufactured. HALT/STANDBY bit in SCCR2 controls which low-power mode is entered. communications interface 1) is detected.
In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode. Table 14. Low-Power/Idle Control Bits through a programmable contact, the device always enters the IDLE mode. means that the NMI is generated always, regardless of the interrupt enable flags. STANDBY and HALT modes, the clocking of the watchdog timer is inhibited. the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1. low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. steeper decay of emissions produced by the oscillator.
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programming. The privileged bits are shown in a bold typeface and shaded. Table 15. Peripheral File Frame 1: System Configuration Registers
addresses, registers, and control bits within this peripheral file frame. Table 16. Peripheral File Frame 2: Digital Port Control Registers † To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
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Table 17. Port Configuration Register Setup
Figure 5. Timer 1 Block Diagram watchdog feature is not needed.
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Table 18 shows the T1 module control register. Table 18. T1 Module Register Memory Map
bit 0, in the T1CTL2 register. Figure 6. Capture/Compare Mode
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bit 0, in the T1CTL2 register. Figure 7. Dual-Compare Mode
Figure 8. Standard Watchdog
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– Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK. Figure 9. Hard Watchdog
Figure 10. Simple Counter
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Figure 11. Timer 2A Block Diagram
The T2A module-control registers are illustrated in Table 19. Table 19. Timer 2A Module Register Memory Map
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bit 0, in the T2ACTL2 register. Figure 12. Dual-Compare Mode
Figure 13. Dual-Capture Mode
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
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serial peripheral interface (SPI) module The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length (1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications. The SPI module features include the following: /C0068Three external pins: – SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin – SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin – SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin /C0068Two operational modes: master and slave /C0068Baud rate: Eight different programmable rates – Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK SPI BAUD RATE /C0043SYSCLK 2 /C00322 b – Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK. For maximum slave SPI BAUD RATE < SYSCLK/8 where b = bit rate in SPICCR.5-3 (range 0–7) /C0068Data word format: one to eight data bits /C0068Simultaneous receive and transmit operation (transmit function can be disabled in software) /C0068Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms. /C0068Seven SPI module control registers located in control register frame beginning at address P030h
The SPI module control registers are illustrated in Table 20. Table 20. SPI Module Control Register Memory Map
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The SPI block diagram is illustrated in Figure 14. † The diagram is shown in slave mode. Figure 14. SPI Block Diagram 16-bit baud-select register.
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 39POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 serial communications interface 1 (SCI1) module (continued) Features of the SCI1 module include: /C0068Three external pins: – SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin – SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin – SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin /C0068Two communications modes: asynchronous and isosynchronous† /C0068Baud rate: 64K different programmable rates – Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK ASYNCHRONOUS BAUD /C0043SYSCLK (BAUD REG /C00411)/C003232 – Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK ISOSYNCHRONOUS BAUD /C0043SYSCLK (BAUD REG /C00411)/C00322 /C0068Data-word format – One start bit – Data-word length programmable from 1 to 8 bits – Optional even/odd/no parity bit – One or two stop bits /C0068Four error-detection flags: parity, overrun, framing, and break detection /C0068Two wake-up multiprocessor modes: Idle-line and address bit /C0068Half or full-duplex operation /C0068Double-buffered receive and transmit functions /C0068Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX) operations. – Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX EMPTY flag (transmitter shift register is empty) – Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR monitoring four interrupt conditions – Separate enable bits for transmitter and receiver interrupts – NRZ (non return-to-zero) format /C0068Eleven SCI1 module control registers are located in control register frame beginning at address P050h. † Isosynchronous = Isochronous
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The SCI1 module control registers are illustrated in Table 21. Table 21. SCI1 Module Control Register Memory Map The SCI1 module block diagram is illustrated in Figure 15.
Figure 15. SCI1 Block Diagram – AN1–AN7 can also be configured as positive-input voltage reference.
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/C0068ADC1 operations can be accomplished through either interrupt driven or polled algorithms. /C0068Six ADC1 module control registers are located in the control-register frame beginning at address 1070h. The ADC1 module control registers are illustrated in Table 22. Table 22. ADC1 Module Control Register Memory Map
The ADC1 module block diagram is illustrated in Figure 16. Figure 16. ADC1 Block Diagram
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
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Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.
Table 23. TMS370 Family Opcode/Instruction Map† instructions have a relative address as the last operand.
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Table 23. TMS370 Family Opcode/Instruction Map† (Continued) instructions have a relative address as the last operand.
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 development system support The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit emulator (XDS/22), CDT, and an EEPROM/UVEPROM programmer. /C0068Assembler/linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Features high-speed operation – Includes format conversion utilities for popular formats /C0068ANSI C-Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3 or Sun-4 ) – Generates assembly code for the TMS370 that can be inspected easily – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct reference of the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker /C0068CDT370 (compact development tool) real-time in-circuit emulation – Base (Part Number EDSCDT370 – for PC, requires cable) – Cable for 68-pin PLCC (Part No. EDSTRG68PLCC) – Cable for 64-pin SDIP (Part No. EDSTRG64SDIL) – Provides EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Allows uploading/downloading of program and data memory – Provides capability to execute programs and software routines – Includes 1024 samples trace buffer – Includes single-step executable instructions – Allows use of software breakpoints to halt program execution at selected address /C0068XDS/22 (extended development support) in-circuit emulator – Base (Part Number TMDS3762210 for PC, requires cable) – Cable for 68-pin PLCC/64-Pin SDIP (Part No. TMDS3788868) – Contains all of the features of the CDT370 described above but does not have the capability to program the data EEPROM and program EPROM – Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace samples with symbolic disassembly – Allows breakpoints to be qualified by address and/or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint – Provides timers for analyzing total and average time in routines HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
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development system support (continued) – Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and for tracing display /C0068Microcontroller programmer – Base (Part No. TMDS3760500A – for PC, requires programmer head) – Single unit head for 68-pin PLCC (Part No. TMDS3780510A) – Single unit head for 64-pin SDIP (Part No. TMDS3780511A) – Personal computer-based, window/function-key oriented user interface for ease of use and rapid learning environment /C0068Design kit (Part No. TMDS3770110 – for PC) – Includes TMS370 Application Board and TMS370 Assembler diskette and documentation. – Supports quick evaluation of TMS370 functionality – Provides capability to upload and download code – Provides capability to execute programs and software routines, and to single-step executable instructions – Allows software breakpoints to halt program execution at selected addresses – Includes wire-wrap prototype area – Includes reverse assembler /C0068Starter Kit (Part No. TMDS37000 – For PC) – Includes TMS370 Assembler diskette and documentation – Includes TMS370 Simulator – Includes programming adapter board and programming software – Does not include – (to be supplied by the user): – + 5 V power supply – ZIF sockets – 9-pin RS232 cable
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Table 24. Device Part Numbers ‡ System evaluators are for use only in prototype environment, and their reliability has not been characterized.
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Table 25 is a listing of all the peripheral file frames using the ’Cx5x (provided for a quick reference). Table 25. Peripheral File Frame Compilation † To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 25. Peripheral File Frame Compilation (Continued)
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SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ VCC1 = VCC§ Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. NOTE 2: Unless otherwise noted, all voltage values are with respect to VSS1 . recommended operating conditions MIN NOM MAX UNIT VCC1 Supply voltage (see Note 2) 4.5 5 5.5 VVCC1 RAM data-retention supply voltage (see Note 3) 3 5.5 V VCC2 Digital I/O supply voltage (see Note 2) 4.5 5 5.5 V VCC3 Analog supply voltage (see Note 2) 4.5 5 5.5 V VSS2 Digital I/O supply ground – 0.3 0 0.3 V VSS3 Analog supply ground – 0.3 0 0.3 V VIL Low level input voltage All pins except MC VSS1 0.8 V VIL Low-level input voltage MC, normal operation VSS1 0.3 V All pins except MC, XTAL2/CLKIN, and RESET 2 VCC1 VIH High-level input voltage MC (non-WPO mode) VCC1 –0.3 VCC1 +0.3 VIH gg XTAL2/CLKIN 0.8 VCC1 VCC1 RESET 0.7 VCC1 VCC1 EEPROM write protect override (WPO) 11.7 12 13 VMC MC (mode control) voltage EPROM programming voltage (VPP ) 13 13.2 13.5 VVMC () g (see Note 4) Microprocessor VCC1 –0.3 VCC1 +0.3 V Microcomputer VSS1 0.3 L version 0 70 TA Operating free-air temperature A version – 40 85 °C T version – 40 105 NOTES: 2. Unless otherwise noted, all voltage values are with respect to VSS1 . 3. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range. 4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (tc) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is present on MC. electrical characteristics over recommended operating free-air temperature range (unless
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage (see Note 5)IOL = 1.4 mA 0.4 V VOH High level output voltage IOH = –50 mA 0.9 VCC1 VVOH High-level output voltage IOH = –2 mA 2.4 V 0 V < VI ≤ 0.3 V 10 0.3 V < VI < VCC1 –0.3 V 50 mA II Input current MC VCC1 –0.3 V ≤ VI ≤ VCC1 +0.3 V 10 mA II Input current VCC1 + 0.3 V < VI ≤ 13 V 650
12 V ≤ VI ≤ 13 V See Note 6 50 mA
I/O pins 0 V ≤ VI ≤ VCC1 ± 10 mA IOL Low-level output current (see Note 5)VOL = 0.4 V 1.4 mA IOH High level output current VOH = 0.9 VCC1 – 50 mA IOH High-level output current VOH = 2.4 V – 2 mA TMS370Cx50A TMS370Cx52A 30 45 Supply current (id ) TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B SYSCLK = 5 MHz See Notes 7 and 8 35 56 (operating mode) OSC POWER bit = 0 (see Note 9) TMS370Cx50A TMS370Cx52A 20 30 mA (see Note 9) TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B SYSCLK = 3 MHz See Notes 7 and 8 25 36 TMS370Cx59A † 46 55 ICC Sl t TMS370Cx50A TMS370Cx52A 5 11 Supply current (operating mode) OSC POWER bit = 0 (see Note 9) TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B SYSCLK = 0.5 MHz See Notes 7 and 8 13 18 mA TMS370Cx59A † 22 28 S l t (STANDBY d ) SYSCLK = 5 MHz, See Notes 7 and 8 12 17 Supply current (STANDBY mode) OSC POWER bi t = 0 (see Note 10) SYSCLK = 3 MHz, See Notes 7 and 8 8 11 mAOSC POWER bit = 0 (see Note 10) SYSCLK = 0.5 MHz, See Notes 7 and 8 2.5 3.5 Supply current (STANDBY mode) SYSCLK = 3 MHz, See Notes 7 and 8 6 8.6 mAy( ) OSC POWER bit = 1 (see Note 11) SYSCLK = 0.5 MHz, See Notes 7 and 8 2 3 mA Supply current (HALT mode) XTAL2/CLKIN < 0.2 V,See Note 7 2 30 mA † TMS370Cx59 only operate up to 3 MHz SYSCLK NOTES: 5. In prior versions of the TMS370 family, the IOL current was equal to 2 mA for ports A, B, C, and D and the RESET pin. 6. Input current IPP is a maximum of 50 mA only when the EPROM is being programmed. 8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 9. Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6 (SYSCLK) + 7 mA. Maximum operating current for TMS370Cx53A, TMS370Cx56A, TMS370Cx58A, and TMS370Cx58B = 10 (SYSCLK) + 5.8 mA. 10. Maximum standby current for TMS370Cx5xA = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0). 11. Maximum standby current for TMS370Cx5xA and TMS370Cx5xB = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, valid only up to 3 MHz of SYSCLK.)
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NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. Figure 19. Recommended Crystal/Clock Connections driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. Figure 20. Typical Output Load Circuit (see Note A) Figure 21. Typlcal Buffer Circuitry
All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23.
0.8 V (Low)
2 V (High)
0.8 VCC V (High)
Figure 22. XTAL2/CLKIN Measurement Points Figure 23. General Measurement Points
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† For VIL and VIH, refer to recommended operating conditions. low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 24. External Clock Timing for Divide-by-4 † For VIL and VIH, refer to recommended operating conditions. low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 25. External Clock Timing for Divide-by-1
Figure 26. Signal-Switching Timing NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
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switching characteristics and timing requirements for external read and write (see Figure 27 and Figure 28)† NO. PARAMETER MIN MAX UNIT 5 t Cycle time SYSCLK (system clock) Divide-by-4 clock 200 2000 ns5 tc C ycle time, SYSCLK (system clock) Divide-by-1 PLL 200 500 ns 6 tw(SCL) Pulse duration, SYSCLK low 0.5tc–25 0.5tc ns 7 tw(SCH) Pulse duration, SYSCLK high 0.5tc 0.5tc+20 ns 8 td(SCL-A) Delay time, SYSCLK low to address R/W and OCF valid 0.25tc+75 ns 9 tv(A) Valid time, address to EDS, CSE1, CSE2, CSH1, CSH2 , CSH3, and CSPF low 0.5tc–90 ns 10 tsu(D) Setup time, write data time to EDS high 0.75tc–80‡ ns 11 th(EH-A) Hold time, address, R/W and OCF from EDS, CSE1, CSE2 , CSH1, CSH2, CSH3, and CSPF high 0.5tc–60 ns 12 th(EH-D)W Hold time, write data time from EDS high 0.75tc+15 ns 13 td(DZ-EL) Delay time, data bus high impedance to EDS low (read cycle) 0.25tc–35 ns 14 td(EH-D) Delay time, EDS high to data bus enable (read cycle) 1.25tc–40 ns 15 td(EL-DV)R Delay time, EDS low to read data valid tc–95‡ ns 16 th(EH-D)R Hold time, read time from EDS high 0 ns 17 tsu(WT-SCH) Setup time, WAIT time to SYSCLK high 0.25tc+70§ ns 18 th(SCH-WT) Hold time, WAIT time from SYSCLK high 0 ns 19 td(EL-WTV) Delay time, EDS low to WAIT valid 0.5tc–60 ns 20 tw Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3 , and CSPF low tc–80‡ tc+40‡ ns 21 td(AV-DV)R Delay time, address valid to read data valid 1.5tc–115‡ ns 22 td(AV-WTV) Delay time, address valid to WAIT valid tc–115 ns 23 td(AV-EH) Delay time, address valid to EDS high (end of write) 1.5tc–85‡ ns † tc = system-clock cycle time = 1/SYSCLK ‡ If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked. § If the autowait feature is enabled, the WAIT input can assume a “don’t care” condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
370 Drives Data Read Data Drive Read Data
370 Drives
Figure 27. Switching Characteristics and Timing Requirements for External-Read
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Figure 28. Switching Characteristics and Timing Requirements for External-Write
Figure 29. SCI1 Isosynchronous† Mode Timing for Internal Clock
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Figure 30. SCI1 Isosynchronous† Timing for External Clock
NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0. Figure 31. SPI Master External Timing
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NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0. Figure 32. SPI-Slave External Timing
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 69POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can be present on V SS1 and VCC1 from coupling into the ADC1 analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT VCC3 Analog supply voltage 4.5 5 5.5 VVCC3 Analog supply voltage VCC1 –0.3 VCC1 +0.3 V VSS3 Analog ground VSS1 –0.3 VSS1 +0.3 V Vref Non-VCC3 reference† 2.5 VCC3 VCC3 + 0.1 V Analog input for conversion VSS3 Vref V † Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time. operating characteristics over recommended ranges operating conditions PARAMETER MIN MAX UNIT Differential/integral linearity error‡§ VCC3 = 5.5 V V ref = 5.1 V ± 0.9 LSB ICC3 Analog supply current Converting 2 mA ICC3 Analog supply current Nonconverting 5 mA II Input current, AN0–AN7 0 V ≤ VI ≤ 5.5 V 2 mA II Iref input charge current 1 mA Z f Source impedance of Vf SYSCLK ≤ 3 MHz 24 kW Zref Source impedance of Vref 3 MHz < SYSCLK ≤ 5 MHz 10 kW ‡ Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. § Excluding quantization error of 1/2 LSB
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signaling that a conversion has started and that the analog signal can be removed. † The value given is valid for a signal with a source impedance > 1 kW . If the source impedance is < 1 kW , use a minimum sampling time of 1ms. Figure 33. Analog Timing
mechanical drawing by drawing number and name. Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference
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Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference (Continued)
www.ti.com 3-Dec-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) SE370C756AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C756AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C758AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C758AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C758BFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C758BJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C759AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI TMS370C256AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C356AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C356ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI TMS370C756AFNT ACTIVE PLCC FN 68 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMS370C758AFNTG4 OBSOLETE PLCC FN 68 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR TMS370C758ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI TMS370C758BFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C758BNMT OBSOLETE SDIP NM 64 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
www.ti.com 3-Dec-2012 Addendum-Page 2 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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