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SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume Production – One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production – Reprogrammable-EPROM Devices for Prototyping Purposes /C0068Internal System Memory Configurations – On-Chip Program Memory Versions – ROM: 16K Bytes – EPROM: 16K Bytes – Data EEPROM: 256 Bytes – Static RAM: 256 Bytes Usable as Registers – Standby RAM With Separate Power Supply Pin: 256 Bytes /C0068Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options – Divide-by-1 (2 MHz–5 MHz SYSCLK) Phase-Locked Loop (PLL) – Divide-by-4 (0.5 MHz–5 MHz SYSCLK) – Supply Voltage (V CC ) 5 V ±10% /C0068Programmable Acquisition and Control Timer (PACT) Module – Input Capture on up to Six Pins, Four of Which Can Have a Programmable Prescaler – One Input Capture Pin Can Drive an 8-Bit Event Counter – Up to Eight Timer-Driven Outputs – Interaction Between Event Counter and Timer Activity – 18 Independent Interrupt Vectors – Watchdog With Selectable Time-Out Period – Asynchronous Mini Serial Communication Interface (Mini SCI) /C0068Flexible Interrupt Handling – Two Software-Programmable Interrupt Levels – Global- and Individual-Interrupt Masking – Programmable Rising- or Falling-Edge Detect – Individual-Interrupt Vectors /C0068Serial Peripheral Interface (SPI) – Variable-Length High-Speed Shift Register – Synchronous Master/Slave Operation /C0068Eight Channel 8-Bit Analog-to-Digital Converter 1 (ADC1) /C0068TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With All TMS370 Devices /C0068CMOS/TTL Compatible I/O Pins/Packages – All Peripheral Function Pins Software Configurable for Digital I/O – 16 Bidirectional Pins, Nine Input Pins – 44-Pin Plastic and Ceramic Leaded Chip Carrier (LCC) Packages /C0068Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Multi-Window User Interface – Microcontroller Programmer PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. XTAL2/CLKIN MC RESET SPICLK SPISOMI SPISIMO 18 19 AN3 AN4 AN5 AN6 AN7 D6/CP6 D7/CP5 D4/CP4 D5/CP1 OP1/CP3 OP2/CP2 20 21 22 23 FZ AND FN PACKAGES (TOP VIEW) V V 5432164 4 AN2 AN1 AN0 V V XTAL1 OP7 OP8 INT1 SS1 SCIRXD SCITXD OP3 OP4 OP5 OP6 42 41 4043 24 25 26 27 28 CC3 SS3 CC1 V CCSTBY
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
44 PINS
ÁÁÁ ÁÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESCRIPTION
ÁÁÁÁÁ NAME ÁÁÁÁ NO. ÁÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port A is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ D4/CP4 D5/CP1 D6/CP6 D7/CP5 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port D is a general-purpose bidirectional port. Also configurable as SYSCLK (see Note 1) PACT input capture 4 (see Note 2) PACT input capture 1 (see Note 2) PACT input capture 6 (see Note 2) PACT input capture 5 (see Note 2) ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC1 analog input pins (AN0–AN7)/port E digital input pins (E0–E7) Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog input or positive reference input. ÁÁÁÁÁ ÁÁÁÁÁ INT1 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ External interrupt (non-maskable or maskable)/general-purpose input pin ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ OP1/CP3 OP2/CP2 OP3 OP4 OP5 OP6 OP7 OP8 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PACT PWM output 1/input capture 3 (see Note 3) PACT output pin 2/input capture 2 (see Note 3) PACT PWM output 3 PACT PWM output 4 PACT PWM output 5 PACT PWM output 6 PACT PWM output 7 PACT PWM output 8 ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ SCIRXD SCITXD ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PACT mini SCI data receive input pin PACT mini SCI data transmit output pin ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ SPISOMI SPISIMO SPICLK ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin ÁÁÁÁÁ ÁÁÁÁÁ RESET ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. ÁÁÁÁÁ ÁÁÁÁÁ MC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ XTAL2/CLKIN XTAL1 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Internal oscillator crystal input/External clock source input Internal oscillator output for crystal ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ VCC1 VSS1 VCC3 VSS3 VCCSTBY ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage for digital logic and digital I/O pins Ground reference for digital logic and digital I/O pins ADC1 positive supply voltage and optional positive reference input ADC1 ground supply and low reference input pin Positive supply voltage pin for standby RAM † I = input, O = output NOTES: 1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers. 2. These digital I/O buffers are connected internally to some of the PACT module’s input capture pins. This allows the microcontroller to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry. 3. CP2 and CP3 are connected internally to OP2 and OP1. CP2 and CP3 can be used only to capture OP2 and OP1, respectively and not as external capture inputs.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Interrupts CP1 SCITXD SCIRXD V System Control Clock Options: Divide-By-4 or Divide-By-1 (PLL) Standby RAM
256 Bytes
ROM: 16K Bytes EPROM: 16K Bytes ÏÏÏÏÏ ÏÏÏÏÏ Data EEPROM ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ
128 BYTES
The TMS370C036, TMS370C736, and SE370C736 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx36 refers to these devices. The TMS370 family provides cost-effective real-time system control through advanced peripheral-function modules and various on-chip memory configurations. The TMS370Cx36 family of devices uses high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low operating power, wide operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx36 devices attractive for system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications. All TMS370Cx36 devices contain the following on-chip peripheral modules: /C0068Programmable acquisition and control timer (PACT) – Asynchronous mini SCI – PACT watchdog timer /C0068Serial peripheral interface (SPI) /C0068Eight channel, 8-bit analog-to-digital converter 1 (ADC1)
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Table 1 provides a memory configuration overview of the TMS370Cx36 devices. Table 1. Memory Configurations
44 PIN PACKAGES
† System evaluators and development are for use only in prototype environment, and their reliability has not been characterized. are configured through a programmable contact during manufacture. Table 2. Suffix Letter Configuration ‡ Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering. OTP (TMS370C736) and reprogrammable (SE370C736) devices are available. when the mask charge or cycle time for the low-cost mask ROM devices is not practical. breadboards and prototype systems while iterating initial designs. instruction-set-compatible, providing easy transition between members of the family. module allows for levels of flexibility and power not found in traditional microcontroller timers.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) The TMS370Cx36 family provides the system designer with an economical, efficient solution to real-time control applications. The PACT compact development tool (CDT ) meets the challenge of efficiently developing the software and hardware required to design the TMS370Cx36 into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle. The TMS370Cx36 family together with the TMS370 PACT CDT370, BP programmer, software tools, SE370C736 reprogrammable devices, comprehensive product documentation, and customer support provides a complete solution to the needs of the system designer. central processing unit (CPU) The CPU on the TMS370Cx36 device is the high-performance 8-bit TMS370 CPU module. The ’x36 implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x36 instruction map is shown in Table 16. The ’370Cx36 CPU architecture provides the following components: CPU registers: /C0068A stack pointer (SP) that points to the last entry in the memory stack /C0068A status register (ST) that monitors the operation of the instructions and contains the global interrupt-enable bits /C0068A program counter (PC) that points to the memory location of the next instruction to be executed A memory map that includes: /C0068256-byte general-purpose RAM that can be used for data memory storage, program instructions, general purpose register, or the stack /C0068256-byte general-purpose standby RAM, which is powered through a separate VCCSTBY pin to protect the memory against power failures on the main VCC1 pins /C0068128-byte dual-port RAM that contains the capture registers, the circular buffer, and a command/definition area /C0068A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control /C0068256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off conditions /C006816K-byte ROM or 16K-byte EPROM CDT is a trademark of Texas Instruments Incorporated.
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Figure 1 Illustrates the CPU registers and memory blocks.
015 Program Counter
7 Legend:
† Reserved means the address space is reserved for future expansion. Figure 1. Programmer’s Model is used to store the return address on subroutine calls as well as the ST contents during interrupt sequences. four status bits (condition flags) and two interrupt-enable bits. the conditional-jump instructions) use the status bits to determine program flow. /C0068The two interrupt-enable bits control the two interrupt levels.
The ST, status-bit notation, and status-bit definitions are shown in Table 3. Table 3. Status Registers registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address. contents of the reset vector. Figure 2. Program Counter After Reset EEPROM, I/O pins, peripheral functions, and system-interrupt vectors. data information are passed.
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† Reserved means that the address space is reserved for future expansion. Figure 3. TMS370Cx36 Memory Map stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 standby RAM module The 256 byte standby RAM is general-purpose and powered through a separate VCCSTBY pin. The data stored in this memory is protected against power failures on the main VCC1 pins. The standby RAM data is saved if the power failure on the main VCC1 pins is detected externally and an external reset is generated when VCC1 falls below 4.3 V (see Figure 4). The external reset must remain low during the entire power failures. The falling edge of the reset signal is internally detected to set the standby RAM in low-power HALT mode. After the next power up, the RESET pin must be pulled high to get out of the HALT mode of the standby RAM. In halt mode, the standby RAM consumes only leakage current.
4.3 Volt
Standby RAM Locked in Halt Mode Figure 4. Standby RAM Locked in Halt Mode lists the TMS370Cx36 PF address map. Table 4. TMS370Cx36 Peripheral File Address Map ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1000h–100Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P000–P00F Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010h–101Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P010–P01F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System and EPROM/EEPROM control registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1020h–102Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P020–P02F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital I/O port control registers ÁÁÁÁÁÁÁ 1030h–103Fh ÁÁÁÁÁÁÁ P030–P03F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPI registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1040h–104Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P040–P04F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PACT registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1050h–106Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P050–P06F Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1070h–107Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P070–P07F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog-to-digital converter 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1080h–10FFh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P080–P0FF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved
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– Bit-, byte-, and block-write/erase modes. – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. beginning at location P01A. See Table 5. – In-circuit programming capability. There is no need to remove the device to program. /C0068Write protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write protection active. There is one write-protect bit per 32-byte EEPROM block. /C0068Write protection can be overridden by applying 12 V to MC. Table 5. Data EEPROM and PROGRAM EPROM Control Registers Memory Map in the peripheral file (PF) frame at location P01C as shown in Table 5. TI is a trademark of Texas Instruments Incorporated.
fabrication. Refer to Figure 3 for ROM memory map. The system-reset operation ensures an orderly start-up sequence for the TMS370Cx36 CPU-based device. User’s Guide (literature number SPNU127) for more information. /C0068Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the TMS370 User’s Guide (literature number SPNU127) for more information. TMS370 User’s Guide (literature number SPNU127) for more information. reset logic holds the device in a reset state for as long as these actions are active. low by the external hardware or the PACT module’s watchdog. Table 6. Reset Sources
- The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
- Registers A and B are initialized to 00h (no other RAM is changed).
- The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
- The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
- Program execution begins with an opcode fetch from the address pointed to the PC.
register bits are initialized to their reset state.
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Figure 5. Interrupt Control low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts (continued) chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx36 has 21 hardware system interrupts (plus RESET ) as shown in Table 7. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt. Twenty of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is supported. Software configuration of the external interrupts is performed through the INT1 control register in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupt INT1 can be software configured as a general-purpose input pin if the interrupt function is not required.
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Table 7. Hardware System Interrupts and must be configured by software prior to exiting the privileged mode.
Table 8. Privilege Bits system configuration registers section of Table 10. HALT/STANDBY bit in SCCR2 controls the low-power mode selection. In the HALT mode (HALT/STANDBY = 1), the TMS370Cx36 is placed in its lowest power consumption mode. power-down mode-selection bits are summarized in Table 9.
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Table 9. Low-Power/Idle Control Bits through a programmable contact, the device always enters the IDLE mode. means that the NMI is generated always, regardless of the interrupt enable flags. of the WD timer is inhibited. EPROM has only the divide-by-4. decay of emissions produced by the oscillator.
programming. The privileged bits are shown in a bold typeface and shaded areas. Table 10. Peripheral File Frame 1: System-Configuration Registers
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Table 11. Peripheral File Frame 2: Digital Port-Control Registers † To configure pin D3 as SYSCLK, set port D control register 2 = 08h. Table 12. Port Configuration Register Setup used for communications between the microcontroller and external peripherals or another microcontroller.
/C0068Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. The SPI module-control registers are listed in Table 13. Table 13. SPI Module-Control Register Memory Map
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The SPI block diagram is illustrated in Figure 6. † The block diagram is shown in slave mode. Figure 6. SPI Block Diagram within the dual-port Ram, the CPU can access these parameters quickly. third is an area near the end of the program memory which holds the interrupt vectors of PACT.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 programmable acquisition and control timer (PACT) module (continued) The PACT module features include the following: /C0068Input-capture functions on up to six input pins (CP1 to CP6), depending on the mode selected: – Mode A: CP1–2 are dedicated capture, CP3–6 are circular buffer capture, and CP6 is also an event pin. – Mode B: CP1–4 are dedicated capture, CP5–6 are circular buffer capture, and CP6 is also an event pin. /C0068Multiple timer-driven outputs on eight pins (OP1 to OP8) – Standard compare command: set or clear an output pin whenever the timer/counter is equal to a certain value – Virtual timers: enable variations of the PWM’s period and provides periodic interrupts to the processor. – Double event-compare command: comparisons of the 8-bit event counter with two event-compare values and the actions that can be performed are based on each value: – Event-compare 1 matching the event counter: sets or resets the selected output pin (OP1–OP8), generates interrupt, and generates a 32-bit capture into the circular buffer. – Event-compare 2 matching the event counter: sets or resets the selected output pin (OP1–OP8), generates interrupt, generates a 32-bit capture into the circular buffer, and resets the 20-bit default timer. – Offset timer definition-time from last event: – Generates an interrupt when the maximum event count is reached – Stores the 16-bit virtual timer in the circular buffer on each event – Stores the 20-bit default timer and 8-bit event counter in the circular buffer when the maximum event count is reached – Resets the 20-bit hardware default timer when the maximum event count is reached. – Conditional-compare command has a timer-compare value and an event-compare value. – Generates an interrupt when the event-compare value equals the event counter and the timer-compare value equals the last defined timer – Sets or clears one of the seven output pins (OP1–OP7) when the event compare value equals the event counter and the timer-compare value equals the last defined timer – Baud rate timer definition: runs the mini-serial communications port built into the PACT module. /C0068Configurable timer overflow rates /C0068One 8-bit event counter driven by CP6 /C0068Up to 20-bit timer capability /C0068Interaction between event counter and timer activity /C0068Register-based organization allowing direct access to timer parameters by the CPU /C006818 independent interrupt vectors with two priority levels /C0068Integrated, configurable watchdog with selectable time-out period
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receiver/transmitter (UART) with independent setup of baud rate for receive and transmit lines. The PACT module block diagram is illustrated in Figure 7. Figure 7. PACT Block diagram
Table 14. PACT Control Registers
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– AN1–AN7 also can be configured as positive-input voltage reference. /C0068The ADDATA register, which contains the digital result of the last ADC1 conversion. /C0068ADC1 operations can be accomplished through either interrupt-driven or polled algorithms. The ADC1 module control registers are listed in Table 15. Table 15. ADC1 Module Control Register Memory Map
The ADC1 module block diagram is illustrated in Figure 8. Figure 8. ADC1 Block Diagram
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
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Table 16 provides an opcode to instruction cross reference of all 73 instructions and 274 opcodes of the ‘370Cx36 instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.
Table 16. TMS370 Family Opcode/Instruction Map† instructions have a relative address as the last operand.
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Table 16. TMS370 Family Opcode/Instruction Map† (Continued) have a relative address as the last operand.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 development system support The TMS370 family development support tools include an assembler, a C-compiler, a linker, CDT and an EEPROM/UVEPROM programmer. /C0068Assembler/linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Provides high-speed operation – Includes format conversion utilities for popular formats /C0068ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3 or Sun-4 ) – Generate assembly code for the TMS370 that can be inspected easily – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct reference the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker /C0068CDT370 (Compact Development Tool) PACT real-time in-circuit emulation – Base (Part Number EDSCDT37P – for PC, requires cable) – Cable for 44-pin PLCC (Part No. EDSTRG44PLCC36) – EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Includes compatibility to upload/download program and data memory – Execute programs and software routines – Includes 1024-sample trace buffer – Includes single-step executable instructions – Uses software breakpoints to halt program execution at selected address /C0068Microcontroller programmer – Base (Part No. TMDS3760500A – for PC, requires programmer head) – Single unit head for 44-pin PLCC (Part No. TMDS3780512A) – PC-based, window/function-key-oriented user interface for ease of use and rapid learning environment HP700 is a trademark of Hewlett Packard, Incorporated. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.
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Figure 9 illustrates the numbering and symbol nomenclature for the TMS370Cx36 family. Figure 9. TMS370Cx36 Family Nomenclature
Table 17. Device Part Numbers reliability has not been characterized.
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Figure 10 shows a sample of the new code release form.
- A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
- An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.
or the TMS370 Family Data Manual (literature number SPNS014B). code is approved by the customer.
- Customer: Date: 2. TI: Field Sales:
Figure 10. Sample New Code Release Form
Table 18. Peripheral File Frame Compilation Table 18 is a collection of all the peripheral file frames used in the ’Cx36 (provided for a quick reference). † To configure D3 as SYSCLK, set port D register 2 = 08h.
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Table 18. Peripheral File Frame Compilation (Continued)
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 4. Unless otherwise noted, all voltage values are with respect to VSS1 . 5. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. recommended operating conditions MIN NOM MAX UNIT VCC1 Supply voltage (see Note 4) 4.5 5 5.5 V VCC1 RAM data-retention supply voltage (see Note 6) 3 5.5 V VCCSTBY Standby RAM supply voltage 4.5 5 5.5 VVCCSTBY Standby RAM data retention supply voltage (see Note 6) 3 5.5 V VCC3 Analog supply voltage (see Note 4) 4.5 5 5.5 V VSS3 Analog supply ground – 0.3 0 0.3 V VIL Low level input voltage All pins except MC VSS1 0.8 V VIL Low-level input voltage MC, normal operation VSS1 0.3 V V Hi h l l i t lt All pins except MC, XTAL2/CLKIN, and RESET 2 VCC1 VVIH High-level input voltage XTAL2/CLKIN 0.8 VCC1 VCC1 V RESET 0.7 VCC1 VCC1 EEPROM write protect override (WPO) 11.7 12 13 VMC MC (mode control) voltage EPROM programming voltage (VPP ) 13 13.2 13.5 V Microcomputer VSS1 0.3 L version 0 70 TA Operating free-air temperatureA version – 40 85 °C T version – 40 105 NOTES: 4. Unless otherwise noted, all voltage values are with respect to VSS1 . 6. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range.
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 37POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage All outputs IOL = 1.4 mA 0.4 V VOH High-level output voltage All outputs except PACT outputs IOH = –50 mA 0.9 VCC1 VVOH High level out ut voltage PACT outputs IOH = –50 mA 0.7 VCC1 V All outputs IOH = –2 mA 2.4 0 V ≤ VI ≤ 0.3 V 10 mA MC 0.3 V < VI < VCC1 – 0.3 V 50 mA II Input current MC VCC1 –0.3 < VI < VCC1 +0.3 V 10 mA VCC1 +0.3 V < VI < 13 V 650 mA I/O pins 0 V <VI < VCC1 ± 10 mA IOL Low-level output current All outputs VOL = 0.4 V 1.4 mA IOH High level output current All outputs VOH = 0.9 VCC1 – 50 mA IOH High-level output current All outputs VOH = 2.4 V – 2 mA Supply current (operating mode) OSC POWER bit = 0 See Notes 7 and 8 SYSCLK = 5 MHz 36 45 mA ICC1 Supply current (STANDBY mode) OSC POWER bit = 0 See Notes 7 and 8 SYSCLK = 5 MHz 7 12 mA Supply current (HALT mode) See Notes 7 and 8 XTAL2/CLKIN < 0.2 V 5 30 mA ICCSTBY Standby RAM supply current (operating mode OSC POWER bit = 0) SYSCLK = 5 MHz VCCSTBY = 4.5 V 1 1.5 mA 8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF).
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B. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. Figure 11. Recommended Crystal/Clock Connections driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. Figure 12. Typical Output Load Circuit (See Note A) Figure 13. Typical Buffer Circuitry
All timings are measured between high and low measurement points as indicated in Figure 14 and Figure 15.
0.8 V (Low)
2 V (High)
0.8 VCC V (High)
Figure 14. XTAL2/CLKIN Measurement Points Figure 15. General Measurement Points
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NOTES: 9. For V IL and VIH, refer to recommended operating conditions.
- This pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 16. External Clock Timing for Divide-by-4 NOTES: 9. For V IL and VIH, refer to recommended operating conditions.
- This pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 17. External Clock Timing for Divide-by-1
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† The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 20. SPI Master External Timing†
† The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 21. SPI Slave External Timing†
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
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The ADC1 converter has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can be present on VSS1 and VCC1 from coupling into the ADC1 analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT VCC3 Analog supply voltage 4.5 5 5.5 VVCC3 Analog supply voltage VCC1 –0.3 VCC1 +0.3 V VSS3 Analog ground VSS1 –0.3 VSS1 +0.3 V Vref Non-VCC3 reference† 2.5 VCC3 VCC3 + 0.1 V Analog input for conversion VSS3 Vref V † Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time. operating characteristics over recommended ranges operating conditions PARAMETER MIN MAX UNIT Differential/integral linearity error‡§ VCC3 = 5.5 V V ref = 5.1 V ± 0.9 LSB ICC3 Analog supply current Converting 2 mA ICC3 Analog supply current Nonconverting 5 mA II Input current, AN0–AN7 0 V ≤ VI ≤ 5.5 V 2 mA Iref Input charge current 1 mA Z f Source impedance of Vf SYSCLK ≤ 3 MHz 24 kW Zref Source impedance of Vref 3 MHz < SYSCLK ≤ 5 MHz 10 kW ‡ Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. § Excluding quantization error of 1/2 LSB
signaling that a conversion has started and that the analog signal can be removed. † The value given is valid for a signal with a source impedance > 1 kW . If the source impedance is < 1 kW , use a minimum sampling time of 1ms. Figure 22. Analog Timing mechanical drawing by drawing number and name. Table 19. TMS370Cx36 Family Package Type and Mechanical Cross-Reference
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
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FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95
20 PIN SHOWN
0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA FZ (S-CQCC-J) J-LEADED CERAMIC CHIP CARRIER 4040219/B 03/95 0.180 (4,57) 0.140 (3,55) C 0.020 (0,51) 0.032 (0,81)A B A B 0.025 (0,64) R TYP 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) MIN 0.090 (2,29) A MIN MAX 0.485 (12,32) (12,57) 0.495 0.455 (11,56)(10,92) 0.430 MAXMIN BC MIN MAX 0.410 (10,41) (10,92) 0.430 PINS NO. OFJEDEC MO-087AC MO-087AB MO-087AA OUTLINE
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(at Seating Plane) 142 6 1812 5 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SE370C736AFZT OBSOLETE JLCC FZ 44 TBD Call TI Call TI TMS370C736AFNT OBSOLETE PLCC FN 44 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 Addendum-Page 1
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