TMS370CX1X_15 TI1 | Alldatasheet

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SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 1POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 D CMOS/EEPROM/EPROM Technologies on a Single Device - - Mask-ROM Devices for High-Volume Production - - One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production - - Reprogrammable-EPROM Devices for Prototyping Purposes D Internal System Memory Configurations - - On-Chip Program Memory Versions - - ROM: 2K, 4K, or 8K Bytes - - E P R O M :8 KB y t e s - - Data EEPROM: 256 Bytes - - Static RAM: 128 or 256 Bytes Usable as Registers D Flexible Operating Features - - Low-Power Modes: STANDBY and HALT - - Commercial, Industrial, and Automotive Temperature Ranges - - Clock Options - - Divide-by-1 (2 MHz- -5 MHz SYSCLK) Phase-Locked Loop (PLL) - - Divide-by-4 (0.5 MHz- -5 MHz SYSCLK) - - Supply Voltage (VCC)5V 10% D 16-Bit General Purpose Timer - - Software Configurable as a 16-Bit Event Counter, or a 16-Bit Pulse Accumulator, or a 16-Bit Input Capture Functions, or Two Compare Registers, or a Self-Contained PWM Function - - Software Programmable Input Polarity - - 8-Bit Prescaler, Providing a 24-Bit Real-Time Timer D On-Chip 24-Bit Watchdog Timer - - EPROM/OTP Devices: - - EPROM ’712A Standard Watchdog - - EPROM ’712B Hard Watchdog - - Mask-ROM Devices: Hard Watchdog, Simple Counter, or Standard Watchdog D Flexible Interrupt Handling - - Two Software Programmable Interrupt Levels - - Global-and Individual-Interrupt Masking - - Programmable Rising- or Falling-Edge Detect - - Individual Interrupt Vectors D Serial Peripheral Interface (SPI) - - Variable-Length High-Speed Shift Register - - Synchronous Master/Slave Operation D TMS370 Series Compatibility - - Register-to-Register Architecture - - 128 or 256 General-Purpose Registers - - 14 Powerful Addressing Modes - - Instructions Upwardly Compatible With All TMS370 Devices D CMOS/TTL Compatible I/O Pins/Packages - - All Peripheral Function Pins Software Configurable for Digital I/O - - 21 Bidirectional Pins, 1 Input Pin - - 28-Pin Plastic and Ceramic DIP, or Leaded Chip Carrier (LCC) Packages D Workstation/PC-Based Development System - - C Compiler and C Source Debugger - - Real-Time In-Circuit Emulation - - Extensive Breakpoint/Trace Capability - - Multi-Window User Interface - - Microcontroller Programmer PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. V CC XTAL2/CLKIN XTAL1 V SS RESET SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC INT3 INT2 INT1 JD AND N PACKAGES (TOP VIEW) 3212 8 2 7 12 13 SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC XTAL2/CLKIN XTAL1 42 6 14 15 16 1718 SS INT1 INT2 INT3 V RESET FZ AND FN PACKAGES (TOP VIEW)CCV

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997

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28 PINS

DIP and LCC I/O† DESCRIPTION NAME NO. I/O† DESCRIPTION I/O Port A is a general-purpose bidirectional I/O port. I/O Port D is a general-purpose bidirectional I/Oport. D3 is also configurable as SYSCLK. INT1 INT2 INT3 I I/O I/O External interrupt (non-maskable or maskable)/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin T1IC/CR T1PWM T1EVT I/O Timer1 input capture/counter reset inputpin/general-purpose bidirectional pin Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin SPISOMI SPISIMO SPICLK I/O SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin RESET 27 I/O System reset bidirectional pin; as input pin, RESETinitializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. MC 19 I Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP XTAL2/CLKIN XTAL1 I O Internal oscillator crystal input/External clock source input Internal oscillator output for crystal VCC 4 Positive supply voltage VSS 12 Ground reference † I = input, O = output All trademarks are the property of their respective owners.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 3POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 functional block diagram Interrupts T1IC/CR T1EVT T1PWM V System Control Clock Options: Divide-By-4 or Divide-By-1 (PLL) RAM 128 or 256 BytesCPU Port A Port D Timer 1 Watchdog INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC SPISOMI SPISIMO SPICLK Serial Peripheral Interface RESET SS VCC Program Memory ROM: 2K, 4K, or 8K Bytes EPROM: 8K Bytes Data EEPROM 0 or 256 Bytes

description

The TMS370C010, TMS370C012, TMS370C311, TMS370C310, TMS370C312, TMS370C712, and SE370C712 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx1x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral-function modules and various on-chip memory configurations. The TMS370Cx1x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance andextensive on-chip peripheral functions make the TMS370Cx1x devices attractive for system designs forautomotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications. All TMS370Cx1x devices contain the following on-chip peripheral modules: D Serial peripheral interface (SPI) D One 24-bit general-purpose watchdog timer D One 16-bit general-purpose timer with an 8-bit prescaler

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Table 1 provides a memory configuration overview of the TMS370Cx1x devices. Table 1. Memory Configurations

28 PIN PACKAGES

† System evaluators and development are for use only in prototype environment and their reliability has not been characterized. the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configuredthrough a programmable contact during manufacture. Table 2. Suffix Letter Configuration ‡ Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering. devices. The OTP (TMS370C712) device and reprogrammable (SE370C712) device are available. when the mask charge or cycle time for the low-cost mask ROM devices is not practical. breadboards and prototype systems while iterating initial designs.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 5POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 description (continued) The TMS370Cx1x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes. The TMS370Cx1x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx1x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family. The SPI provides a convenient method of serial interaction for high-speed communications between simpler shift register-type devices, such as display drivers, analog-to-digital (A/D) converters, PLL, input/output (I/O) expansion, or other microcontrollers in the system. The TMS370Cx1x family provides the system designer with economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDS) and compact development tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx1x into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family XDS development tool communicates through a standard RS-232-C interface with an existing personal computer. This allows the use of the PC’s editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive menus and screen windowing so that a system designer can begin developing software with minimal training. Precise real-time, in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reducing the time-to-market cycle. The TMS370Cx1x family together with the TMS370 familyXDS22, CDT370, design kit, starter kit, software tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. central processing unit (CPU) The CPU on the TMS370Cx1x device is the high-performance 8-bit TMS370 CPU module. The ’x1x implements an efficient register-to-register architecture thateliminates the conventional accumulator bottleneck. The complete ’x1x instruction map is shown in Table 17 in the TMS370Cx1x instruction set overview section. The ’370Cx1x CPU architecture provides the following components: CPU registers: D A stack pointer that points to the last entry in the memory stack D A status register that monitors the operation of the instructions and contains the global interrupt-enable bits D A program counter (PC) that points to the memory location of the next instruction to be executed XDS and CDT are trademarks of Texas Instruments Incorporated.

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Figure 1 illustrates the CPU registers and memory blocks.

015 Program Counter

7 Legend:

† Reserved means the address space is reserved for future expansion. ‡ Not available means the address space is not accessible. Figure 1. Programmer’s Model

four status bits (condition flags) and two interrupt-enable bits. the conditional-jump instructions) use the status bits to determine program flow. D The two interrupt-enable bits control the two interrupt levels. The ST, status-bit notation, and status-bit definitions are shown in Table 3. Table 3. Status Registers registers contains the most significant byte (MSbyte)and least significant byte (LSbyte) of a 16-bit address. contents of the reset vector. Figure 2. Program Counter After Reset I/O pins, peripheral functions,and system-interrupt vectors. which peripheral control and data information is passed.

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† Reserved means that the address space is reserved for future expansion. ‡ Not available means that the address space is not accessible. Figure 3. TMS370Cx1x Memory Map is shown in Table 4 along with ’712 devices. Table 4. RAM Memory Map stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

shows the TMS370Cx1x PF address map. Table 5. TMS370Cx1x Peripheral File Address Map

  • - Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

beginning at location P01A. See Table 6.

  • - In-circuit programming capability. There is no need to remove the device to program.

D Write protection. Writes to the data EEPROM are disabled during the following conditions.

  • - Reset. All programming of the data EEPROM module is halted.
  • - Write protection active. There is one write-protect bit per 32-byte EEPROM block.

D Write protection can be overridden by applying 12 V to MC. Table 6. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

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other internal memory. During programming, the EPROMis controlled by the EPROM control register (EPCTL). the peripheral file (PF) frame at location P01Ch as shown in Table 6. performed at the time of device fabrication. Table 7. Program ROM Memory Map The system-reset operation ensures an orderly start-up sequence for the TMS370Cx1x CPU-based device. User’s Guide(literature number SPNU127) for more information. D Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See theTMS370 Family User’s Guide(literature number SPNU127) for more information. TMS370 Family User’s Guide(literature number SPNU127) for more information. reset logic holds the device in a reset state for as long as these actions are active. instructions are located between addresses 7FC0h and 7FDFh.

of the reset. A reset does not clear these flags. Table 8 depicts the reset sources. Table 8. Reset Sources

  1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
  2. Register A and B are initialized to 00h (no other RAM is changed).
  3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
  4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
  5. Program execution begins with an opcode fetch from the address pointed to the PC.

register bits are initialized to their reset state.

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Figure 4. Interrupt Control low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority.

chains is performed within the peripheral modules to support interrupt expansion for future modules. mask and priority conditions. associated system interrupt. interrupt function is not required (INT1 can be similarly configured as an input pin). Table 9. Hardware System Interrupts

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and must be configured by software prior to exiting the privileged mode. Table 10. Privilege Bits pin (normally not available in the end application except in a service or diagnostic environment). time when the mask is manufactured. HALT/STANDBY bit in SCCR2 controls the low-power mode selection. , external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected. In the HALT mode (HALT/STANDBY = 1), the TMS370Cx1x is placed in its lowest power consumption mode. detected. The power-down mode-selection bits are summarized in Table 11.

Table 11. Low-Power/Idle Control Bits

0 X † IDLE

through a programmable contact, thedevice always enters the IDLE mode. means that the NMI is generated always, regardless of the interrupt enable flags. of the WD timer is inhibited. EPROM has only the divide-by-4, while the ’712B has divide-by-1. low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. steeper decay of emissions produced by the oscillator.

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programming. The privileged bits are shown in a bold typeface and shaded areas. Table 12. Peripheral File Frame 1: System-Configuration Registers

Table 13. Peripheral File Frame 2: Digital Port-Control Registers † D3 as SYSCLK, set port D control register 2 = 08h. Table 14. Port Configuration Register Setup

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T1 module block diagram is shown in Figure 5. Figure 5. Timer 1 Block Diagram capture or compare registers.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 19POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 programmable timer 1 (continued) D Selectable edge-detection circuitry that, depending onthe mode of operation, senses active transitions on the input capture pins (T1IC/CR) D Interrupts that can be generated on the occurrence of: - - A capture - - A compare equal - - A counter overflow - - An external edge detection D Sixteen T1 module control registers located in the PF frame beginning at address P040 The T1 module control registers are illustrated in Table 15.

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Table 15. Timer 1 Module Register Memory Map

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Figure 7. Dual-Compare Mode

as one of three mask options as follows: standard watchdog, hard WD, or simple counter. Figure 8. Standard Watchdog

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  • - INT1 is enabled as a nonmaskable interrupt during low power modes.

Figure 9. Hard Watchdog

  • - Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

Figure 10. Simple Counter used for communications between the microcontroller and external peripherals or another microcontroller.

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D Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. The SPI module-control registers are illustrated in Table 16. Table 16. SPI Module-Control Register Memory Map

The SPI block diagram is illustrated in Figure 11. † The diagram is shown in the slave mode. Figure 11. SPI Block Diagram two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

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Table 17. TMS370 Family Opcode/Instruction Map† instructions have a relative address as the last operand.

Table 17. TMS370 Family Opcode/Instruction Map†(Continued) instructions have a relative address as the last operand.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997

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development system support The TMS370 family development support tools include an assembler, a C-compiler, a linker, an in-circuit emulator XDS/22, CDT and an EEPROM/UVEPROM programmer. D Assembler/linker (Part No. TMDS3740850- -02 for PC) - - Includes extensive macro capability - - Provides high-speed operation - - Includes format conversion utilities for popular formats D ANSI C Compiler (Part No. TMDS3740855- -02 for PC, Part No. TMDS3740555- -09 for HP700, Sun-3 or Sun-4) - - Generate assembly code for the TMS370 that can be inspected easily - - Improves code execution speed and reduces code size with optional optimizer pass - - Enables direct reference the TMS370’s port registers by using a naming convention - - Provides flexibility in specifying the storage for data objects - - Interfaces C functions and assembly functions easily - - Includes assembler and linker D CDT370 (Compact Development Tool) real-time in-circuit emulation - - Base (Part Number EDSCDT370 - - for PC, requires cable) - - Cable for 28-pin DIP (Part No. EDSTRG28DIL) - - Cable for 28-pin PLCC (Part No. EDSTRG28PLCC) - - EEPROM and EPROM programming support - - Allows inspection and modification of memory locations - - Includes compatibility to upload/download program and data memory - - Execute programs and software routines - - Includes 1024 samples trace buffer - - Includes single-step executable instructions - - Uses software breakpoints to halt program execution at selected address D XDS/22 in-circuit emulator - - Base (Part Number TMDS3762210 for PC, requires cable) - - Cable for 28-pin DIP/PLCC (Part No. TMDS3788828) - - Contains all the features of the CDT370 described previously but does not have the capability to program the data EEPROM and program EPROM - - Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace samples with symbolic disassembly - - Allows qualification of breakpoints by address and/or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 31POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 development system support (continued) - - Provides timers for analyzing total and average time in routines - - Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and to trace display D Microcontroller programmer - - Base (Part No. TMDS3760500A - - for PC, requires programmer head) - - Single unit head for 28-pin PLCC (Part No. TMDS3780510A) - - Single unit head for 28-pin DIP (Part No. TMDS3780511A) - - PC-based, window/function-key-oriented user interface for ease of use and rapid learning environment D Design kit (Part No. TMDS3770110 - - for PC) - - Includes TMS370 Application Board and TMS370 Assembler diskette and documentation - - Supports quick evaluation of TMS370 functionality - - Capability to upload and download code - - Capability to execute programs and software routines, and to single-step executable instructions - - Software breakpoints to halt program execution at selected addresses - - Wire-wrap prototype area - - Reverse assembler D Starter Kit (Part No. TMDS37000 - - for PC) - - Includes TMS370 Assembler diskette and documentation - - Includes TMS370 Simulator - - Includes programming adapter board and programming software - - Does not include (to be supplied by the user) - - + 5 V power supply - - ZIF sockets - - Nine-pin RS232 cable

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Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx1x family. (PLL) clock, and low-power modes are enabled. Figure 12. TMS370Cx1x Family Nomenclature

and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices. Table 18. Device Part Numbers reliability has not been characterized.

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Figure 13 shows a sample of the new code release form.

  1. A ROM description in object form on Floppy Disk, Modem XFR, orEPROM (Verification file will be returned via same media)
  2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

or theTMS370 Family Data Manual(literature number SPNS014B). code is approved by the customer.

  1. Customer: Date: 2. TI: Field Sales:

Figure 13. Sample New Code Release Form

Table 19 is a collection of all the peripheral file frames used in the ’Cx1x (provided for a quick reference). Table 19. Peripheral File Frame Compilation † D3 as SYSCLK, set port D control register 2 = 08h.

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Table 19. Peripheral File Frame Compilation (Continued)

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997 37POST OFFICE BOX 1443HOUSTON, TEXAS 77251- -1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. recommended operating conditions MIN NOM MAX UNIT V Supply voltage (see Note 1) 4.5 5 5.5 V VCC RAM data-retention supply voltage (see Note 3) 3 5.5 V V Low level input voltage All pins except MC VSS 0.8 VVIL Low-level input voltage MC, normal operation VSS 0.3 V V Hi h l l i t lt All pins except MC, XTAL2/CLKIN, and RESET 2 VCC VVIH High-level input voltage XTAL2/CLKIN 0.8 VCC VCC V RESET 0.7 VCC VCC EEPROM write protect override (WPO) 11.7 12 13 VMC MC (mode control) voltage EPROM programming voltage (VPP) 13 13.2 13.5 VVMC MC (mode control) voltage Microcomputer VSS 0.3 V L version 0 70 TA Operating free-air temperature A version -- 4 0 85 CTA Operating free air temperature T version -- 4 0 105 C NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 3. RESET must be externally activated when VCC or SYSCLK is not within the recommended operating range.

SPNS012F - - MAY 1987 - - REVISED FEBRUARY 1997

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage IOL =1 . 4m A 0.4 V V High level output voltage IOH =- - 5 0A 0.9 VCC VVOH High-level output voltage IOH =- - 2m A 2.4 V 0V  VI  0.3 V 10 A MC 0.3 V < VI  13 V 650 A II Input current MC S e eN o t e4

12 V VI  13 V 50 mA

I/O pins 0V  VI  VCC  10 A IOL Low-level output current VOL =0 . 4V 1.4 mA I High le el o tp t c rrent VOH =0 . 9VCC -- 5 0 A IOH High-level output current VOH =2 . 4V -- 2 mA See Notes 5 and 6 SYSCLK = 5 MHz 20 36 Supply current (operating mode) O S CP O W E Rb i t=0( s e eN o t e7 ) See Notes 5 and 6 SYSCLK = 3 MHz 13 25 mAOSC POWER bit 0 (see Note 7) See Notes 5 and 6 SYSCLK = 0.5 MHz 5 11 See Notes 5 and 6 SYSCLK = 5 MHz 10 17 ICC Supply current (STANDBY mode) O S CP O W E Rb i t=0( s e eN o t e8 ) See Notes 5 and 6 SYSCLK = 3 MHz 6.5 11 mAOSC POWER bit 0 (see Note 8) See Notes 5 and 6 SYSCLK = 0.5 MHz 2 3.5 Supply current (STANDBY mode) See Notes 5 and 6 SYSCLK = 3 MHz 4.5 8.6 mASupply current (STANDBY mode) O S CP O W E Rb i t=1( s e eN o t e9 ) See Notes 5 and 6 SYSCLK = 0.5 MHz 1.5 3.0 mA Supply current (HALT mode) S e eN o t e5 XTAL2/CLKIN < 0.2 V 1 30 A NOTES: 4. Input current IPP is a maximum of 50 mA only when you are programming EPROM. 6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extracurrent = 0.01 mA x (total load capacitance + crystal capacitance in pF). 7. Maximum operating current = 5.6 (SYSCLK) + 8 mA. 8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

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All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.

0.8 V (Low)

2 V (High)

Figure 17. XTAL2/CLKIN Measurement Points Figure 18. General Measurement Points

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Figure 21. SYSCLK Timing Figure 22. Signal Switching Timing NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 23. SPI Master External Timing

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NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 24. SPI Slave External Timing

mechanical drawing by drawing number and name. Table 20. TMS370Cx1x Family Package Type and Mechanical Cross-Reference

MCDI005 – JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PINS SHOWN

0.590 (14,99) 0.620 (15,75) TYP 0.590 (15,00) 0.012 (0,30) 0.008 (0,20) 2.435 2.050 0.020 (0,51) MIN 0.125 (3,18) MIN 2.650 4040087/B 04/95 Seating Plane A 0.045 (1,14) 0.065 (1,65) 0.075 (1,91) MAX (4 Places) 2824PINS ** 0.021 (0,53) 0.015 (0,38) 1.250 (31,75) DIM A MAX 0.175 (4,45) 0.140 (3,56) (36,83) 1.450 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package is hermetically sealed with a metal lid. D. The terminals are gold-plated.

MPDI008 – OCTOBER 1994 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.560 (14,22) 0.520 (13,21) 0.610 (15,49) 0.590 (14,99) 524840 0.125 (3,18) MIN 2.390 (60,71) (62,23)(53,09) (51,82) 2.040 2.090 2.450 2.650 (67,31) (65,79) 2.590 0.010 (0,25) NOM 4040053/B 04/95 A 0.060 (1,52) TYP 322824 1.230 (31,24) (32,26) (36,83) (35,81) 1.410 1.4501.270 PINS ** DIM 0.015 (0,38) 0.021 (0,53) A MIN A MAX 1.650 (41,91) (40,89) 1.610 0.020 (0,51) MIN 0.200 (5,08) MAX 0.100 (2,54) M0.010 (0,25) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-011 D. Falls within JEDEC MS-015 (32 pin only)

MPLC004A – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95

20 PIN SHOWN

0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

MJLC003A – FEBRUARY 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FZ (S-CQCC-J) J-LEADED CERAMIC CHIP CARRIER 4040219/B 03/95 0.180 (4,57) 0.140 (3,55) C 0.020 (0,51) 0.032 (0,81)A B A B 0.025 (0,64) R TYP 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) MIN 0.090 (2,29) A MIN MAX 0.485 (12,32) (12,57) 0.495 0.455 (11,56)(10,92) 0.430 MAXMIN BC MIN MAX 0.410 (10,41) (10,92) 0.430 PINS NO. OFJEDEC MO-087AC MO-087AB MO-087AA OUTLINE

28 LEAD SHOWN

(at Seating Plane) 142 6 1812 5 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

www.ti.com 30-Nov-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SE370C712AFZT OBSOLETE JLCC FZ 28 TBD Call TI Call TI SE370C712AJDT OBSOLETE CDIP SB JD 28 TBD Call TI Call TI SE370C712BFZT OBSOLETE JLCC FZ 28 TBD Call TI Call TI SE370C712BJDT OBSOLETE CDIP SB JD 28 TBD Call TI Call TI TMS370C012AFNA NRND PLCC FN 28 TBD Call TI Call TI TMS370C012AFNL NRND PLCC FN 28 TBD Call TI Call TI TMS370C310AFNA NRND PLCC FN 28 TBD Call TI Call TI TMS370C310AFNL NRND PLCC FN 28 TBD Call TI Call TI TMS370C712AFNT OBSOLETE PLCC FN 28 TBD Call TI Call TI TMS @1986 TI 370C712AFNT TMS370C712BFNT OBSOLETE PLCC FN 28 TBD Call TI Call TI TMS370C712BNT OBSOLETE PDIP N 28 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 30-Nov-2014 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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