SE050A1HQ1/Z01SG

SE050_V01 NXP | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Introduction
• 1.1 SE050 use cases
• 1.2 SE050 target applications
• 1.3 SE050 naming convention
• 2 Features and benefits
• 2.1 Key benefits
• 2.2 Key features
• 2.3 Features in detail
• 3 Functional description
• 3.1 Functional diagram
• 3.1.1 Random number generator
• 3.1.2 Supported secure object types
• 3.1.3 Access control
• 3.1.4 Sessions and multi-threading
• 3.1.5 Attestation and trust provisioning
• 3.1.6 Application support
• 3.2 Credential Storage & Memory
• 3.3 Preprovisioned "Ease of Use"
• 3.4 Startup behaviour
• 4 Communication interfaces
• 4.1 I2C Interfaces
• 4.1.1 Supported I2C frequencies
• 4.2 ISO7816 and ISO14443 Interface
• 5 Power-saving modes
• 5.1 Power-down mode
• 5.2 Deep Power-down mode
• 6 Ordering information
• 6.1 Ordering options
• 6.2 Ordering SE050 samples
• 6.3 Configuration
• 7 Pinning information
• 7.1 Pinning
• 7.1.1 Pinning HX2QFN20
• 8 Package
• 9 Marking
• 10 Packing information
• 10.1 Reel packing
• 11 Electrical and timing characteristics
• 12 Limiting values
• 13 Recommended operating conditions
• 14 Characteristics
• 14.1 DC characteristics
• 14.1.1 General and General Purpose I/O interface
• 14.1.2 I2C Interface
• 14.1.3 Power consumption
• 14.2 AC characteristics
• 14.3 I2C Bus Timings
• 14.4 EMC/EMI
• 15 Abbreviations
• 16 References
• 17 Revision history
• 18 Legal information

Plug & Trust Secure Element Rev. 3.4 — 28 March 2022 Product data sheet 504934

1 Introduction

The SE050 is a ready-to-use IoT secure element solution. It provides a root of trust at the IC level and it gives an IoT system state-of-the-art, edge-to-cloud security capability right out of the box. SE050 allows for securely storing and provisioning credentials and performing cryptographic operations for security critical communication and control functions. SE050 is versatile in IoT security use cases such as secure connection to public/private clouds, device-to-device authentication or protection of sensor data. SE050 has an independent Common Criteria EAL 6+ security certification up to OS level and supports both RSA & ECC asymmetric cryptographic algorithms with high key length and future proof ECC curves. The latest security measures protect the IC even against sophisticated non-invasive and invasive attack scenarios. The SE050 is a turnkey solution that comes with Java Card operating system and an applet optimized for IoT security use cases pre-installed. This is complemented by a comprehensive product support package, enabling fast time to market & easy design- in with Plug & Trust middleware for host applications, easy to use development kits, reference designs, and extensive documentation for product evaluation. The SE050 is a product platform that comes in several pin-to-pin compatible product variants, see [4]. Additional information on the integration can be found in several application notes on the NXP website. Also see [3]. For additional information on guidelines for the usability of SE050 and the security recommendations for using the module, see [5] To implement inclusive language, the terms "master/slave" has been replaced by "controller/target", following the recommendation of MIPI.

1.1 SE050 use cases

• Secure connection to public/private clouds, edge computing platforms, infrastructure
• Device-to-device authentication
• Secure data protection
• Secure commissioning support
• Secure CL/MIFARE/Wi-Fi interactions
• Device ID for blockchain
• Secure key storage
• Secure provisioning of credentials
• Ecosystem protection
• Qi 1.3 wireless charging authentication
• Matter Ready

1.2 SE050 target applications

• Smart Industry
• Smart Home
• Smart Cities
• Smart Supply Chains a a a - 0 3 2 9 9 0 H O S T M C U / M P U P L U G A N D T R U S T M W I 2 C S D A S C L N F C D E V I C E R E A D E R S E N S O R C L K R S T I O 2 : S C L I O : S D A L BL AS D AS C L S E 0 5 0 I o T A P P L E T J C O P O S 1 4 4 4 3 1 4 4 4 3 7 8 1 6 I 2 C target S W I 2 C controller I 2 C A C T U A T O R

Figure 1. SE050 solution block diagram providing a wireless interface to an external device like a smartphone.

1.3 SE050 naming convention

includes application specific data. The SE050 commercial names have the following format. All letters are explained in Table 1 . Table 1. SE050 commercial name format

Table 1. SE050 commercial name format...continued

2 Features and benefits

2.1 Key benefits

• Plug & Trust for fast and easy design with complete product support package
• Easy integration with different MCU & MPU platforms and OS´ (Linux, RTOS, Windows, Android, etc.)
• Turnkey solution ideal for system-level security without the need to write security code
• Secure credential injection for root of trust at IC level
• Secure, zero-touch connectivity to public & private clouds
• Real end-to-end security, from sensor to cloud
• Ready-to-use example code for each of the key use cases

2.2 Key features

measures is proven by a Common Criteria EAL6+ certification. applet only. With that, the content from the memory is fully isolated from the host system.

• Built on NXP Integral Security Architecture 3.0 ™
• CC EAL 6+ certified HW and OS as environment to run NXP IoT applications, supporting fully encrypted communications and secured lifecycle management
• FIPS 140-2 certified platform with Security Level 3 for OS and Applet, and Security Level 4 related to Physical Security of the HW – Disclaimer: FIPS certification require a specific product type. For more information, refer to [4].
• Effective protection against advanced attacks, including Power Analysis and Fault Attacks of various kinds
• Multiple logical and physical protection layers, including metal shielding, end-to-end encryption, memory encryption, tamper detection Product data sheet Rev. 3.4 — 28 March 2022 504934 3 / 32

• Support for RSA and ECC asymmetric cryptography algorithms, future proof curves and high key length, e.g. Brainpool, Edwards and Montgomery curves
• Support for AES and DES symmetric cryptographic algorithms for encryption and decryption
• Support for AES Modes: CBC, ECB, CTR
• HMAC, CMAC, SHA-1, SHA-224/256/384/512 operations
• Various options for key derivation functions, including HKDF, MIFARE KDF, PRF (TLS- PSK)
• Extended temperature range for industrial applications (-40 °C to +105 °C)
• Small footprint HX2QFN20 package (3x3 mm)
• Standard physical interface I2C target (High-speed mode, 3.4 Mbps), I2C controller (Fast mode, 400 kbps). Both can be active at the same time
• Dedicated CL wireless interface for IoT use cases simplifying configuration set-up, maintenance in the field and late stage configuration
• Secured user flash memory up to 50 kB for secure data or key storage
• Support for SCP03 protocol (bus encryption and encrypted credential injection) to securely bind the host with the secure element
• TRNG compliant to NIST SP800-90B
• DRBG compliant to NIST SP800-90A
• Support for applet level secure messaging channels to allow end-to-end encrypted communication in multi-tenant ecosystems
• In 2022 NXP launched a new generation of product variants, the SE050E platform. The SE050E platform supports the following new features. – AES Modes: CCM and GCM – GMAC – EC Curves for ECDH: Curve448
• Matter Ready: SE050 provides the necessary cryptographic functions to support the upcoming Matter standard for connecting smart home devices. Note: The available features in each product vary according to the chosen variant. More details are available on [4].

2.3 Features in detail

Table 2. Feature Overview

Table 2. Feature Overview...continued [1] New feature of the new generation of SE050 product family.

3 Functional description

3.1 Functional diagram

Figure 2. SE050 functional diagram SE050 commands are wrapped using the Smartcard T=1 over I²C (T=1o I2C) protocol. encapsulation is available on [1]. such as write, read, delete and update.

3.1.1 Random number generator

3.1.2 Supported secure object types

Plug & Trust Secure Element

• Symmetric Key (AES, 3DES)
• ECC Key
• RSA Key
• HMAC Key
• Binary File
• User ID
• Counter
• Hash-Extend register

3.1.3 Access control

Each secure object can be linked to object specific access control policies. An access control policy associates a user identified by an authentication with a set of privileges such as read, write, … To scale the functionality into a broad range of ecosystems, a set of different authentication options is provided:

• User-ID based authentication
• Symmetric key based authentication with secure messaging
• Asymmetric key based authentication with secure messaging At creation of a secure object, an optional set of policies is associated with that secure object. Each policy assigns a set of allowed operations on that object to an authentication object.

3.1.4 Sessions and multi-threading

The SE050 IoT applet is prepared for ecosystems where multi-threading and multi-tenant use cases are needed on APDU level. To enable that, the applet supports 2 simultaneous sessions that can span full secure messaging sessions, self-authenticated APDUs for tenants not requiring long-lasting sessions and on top one default session for single tenant use cases .

3.1.5 Attestation and trust provisioning

SE050 applet comes with a set of trust provisioned root credentials allowing the owner of the device to securely attest all generated secure keys. Next to that, a customer has the possibility to define own attestation keys. Attestation certificates signed by an attestation CA are included in certain SE050 configurations as documented in [4].

3.1.6 Application support

For specific ecosystems, SE050 IoT applet has built-in crypto features to simplify the deployment of specific use cases such as

• MIFARE SAM functionality
• Wifi password protection
• ECC-Key and RSA-Key based cloud connectivity
• Secure Sensor readout using I2C controller
• Remote attestation and trust provisioning
• Platform Configuration Registers Product data sheet Rev. 3.4 — 28 March 2022 504934 7 / 32

Plug & Trust Secure Element

3.2 Credential Storage & Memory

Within SE050, all credentials and secure objects are stored inside a dynamic file structure. At creation, a user has to associate a file identifier with the object created. This identifier is then used in subsequent operations to access the object. The number of objects that can be allocated is only limited by the available memory in the system. After usage, objects can be deleted and the associated memory is freed up again. There is also the possibility to create transient objects. Transient objects have an object descriptor stored in non-volatile memory, but the object content is stored in RAM. Together with the import/export functionality of SE050, transient objects can be used securely store secret keys in a remote memory system.

3.3 Preprovisioned "Ease of Use" configurations

Some generic SE050 variants are offered pre-configured for ease of use and can be used during development phase and in the field. With this customers have all keys pre- injected in SE050 that are required for the main use cases as e.g. cloud onboarding. For more information, see: [4]

3.4 Startup behaviour

If a supply voltage is applied to pins Vin, Vcc within the specified supply voltage operating range or a RF field according to ISO/IEC 14443 is applied to antenna pins LA, LB the IC boots up. During boot the IC checks for active interface according list below (in the order of the list):

• ISO7816: If interface available for this product type, check CLK to be toggling, then wait for RST to be high
• ISO14443: If interface available for this product type, check of RF field on LA, LB antenna pins
• I2C: If interface available for this product type, check if both I2C_SDA, I2C_SCL pins are at high level (internal weak pull-up active)
• The chosen interface is the only interface the SE050 will receive commands for processing. To select a different interface the IC needs to be reset.

4 Communication interfaces

4.1 I2C Interfaces

The I2C interface vary according the specific SE050 variant see Section 4.1.1. The SE050 has one I2C interface supporting target and one I2C interface supporting controller mode. The I2C target interface is the main communication interface of the device and is used by the host controller to send arbitrary APDUs to the device. It supports clock frequencies up to 3.4 MHz when operated in High-Speed Mode (HS). The I2C interface is using the Smartcard T=1 over I2C protocol. The default target address of the SE050 is configured to 0x48. Product data sheet Rev. 3.4 — 28 March 2022 504934 8 / 32

Figure 3. target address securely written and read. This interface features a maximum SCL clock rate of 400 kHz. I2C controller can only be used when the I2C target interface is active.

4.1.1 Supported I2C frequencies

setting for the SE050 new generation products, SE050E. The SE050 I2C controller interface supports maximum 400 kHz SCL clock frequency. For more details on the features of each configuration, refer to [4].

4.2 ISO7816 and ISO14443 Interface

input capacitance is 56 pF. In addition one additional GPIO pad IO2 is supported. kept in reset state the current consumption is as defined for idle, see Table 12.

5 Power-saving modes

activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode).

5.1 Power-down mode

• All internal clocks are frozen
• CPU enters power-saving mode with program execution being stopped

1 ISO7816 is not enabled in generic SE050 configurations (see [4], AN12436) but available on customer

• CPU registers keep their contents
• RAM keeps its contents The SE050 enters into Power-down mode by receiving "End of APDU session request" via the T=1 over I2C protocol. In Power-down mode, all internal clocks are frozen. The IOs hold the logical states they had at the time Power-down mode was activated. To exit from the Power-down mode an external interrupt edge must be triggered by a falling edge on I2C_SDA2.

5.2 Deep Power-down mode

mode is activated by pulling enable PIN (ENA) to a logic zero level. and only the I2C pads stay supplied. To leave the Deep Power-down mode pad ENA has to be pulled up to to a logic „1" level. VCC needs to be supplied by pin VOUT.

6 Ordering information

6.1 Ordering options

Table 3. SE050 Ordering information Table 4. SE050 Ordering information for development kit

Table 4. SE050 Ordering information for development kit...continued

6.2 Ordering SE050 samples

6.3 Configuration

7 Pinning information

7.1 Pinning

7.1.1 Pinning HX2QFN20

Figure 4. Pin configuration for HX2QFN20 (SOT1969-1) on the top with a printed dot. I2C_SDA 9 I2C target data, if not used n.c. I2C_SCL 10 I2C target clock, if not used n.c. Table 5. Pin description HX2QFN20

Power-down mode is used. N. c. if not used. Table 5. Pin description HX2QFN20...continued voltage is VIN and for IO2 it is VOUT.

8 Package

Please refer to the package data sheet [2], SOT1969-1.

9 Marking

Table 6. Marking codes

10 Packing information

10.1 Reel packing

The SE050 product is available in tape on reel.

Table 7. Reel packing options

12 Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Table 8. Limiting values supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed. [3] JESD22-C101, JEDEC Standard Field induced charge device model test method. [4] Depending on appropriate thermal resistance of the package.

13 Recommended operating conditions

Table 9. Recommended operating conditions

Table 9. Recommended operating conditions...continued [1] Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed. [3] All product properties and values specified within this data sheet are only valid within the operating ambient temperature range. down mode current <5 µA is not guaranteed. Figure 5. Characteristic supply voltage operating range

14 Characteristics

14.1 DC characteristics

the device are considered positive.

14.1.1 General and General Purpose I/O interface

0.7 VCC ≤ VI ≤ VCC

Table 10. Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V;

0.3 VCC < VI ≤ VCC;

0 V ≤ VI ≤ VCC; Test

0.3 V;VCC = VCC(max);

0.15 VCC

input voltage VI is approximately 0.5 VCC. Current IIL is tested at input voltage VI= 0.3 V. [2] External pull-up resistor 20 kΩ to VCC assumed. The worst case test condition for parameter VOH is present at minimum VCC. Figure 6. Input characteristic of RST_N

0 V VILmax VIHmin

Figure 7. Input characteristic of IO1/IO2 Figure 8. Input characteristic of CLK when the IC is not in reset Figure 9. Input characteristic of CLK during IC reset

14.1.2 I2C Interface

SCL, SDA pads are in open-drain mode. Table 11. Electrical DC characteristics of I2C pads SDA, SCL. Conditions: VCC, VIN = 1.62 V to 3.6 V; VSS = 0 V; Tamb

14.1.3 Power consumption

Table 12. Electrical characteristics of IC supply voltage VCC; VSS = 0 V; Tamb = -40 °C to +105 C [1] Maximum current consumption with concurrent AES and Public Key Cryptography 19 mA.

Plug & Trust Secure Element

14.2 AC characteristics

Conditions: VCC = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit tEEP FLASH erase + program time [2] 2.3 ms tEEE FLASH erase time 0.9 ms tEEW FLASH program time 1.4 ms tEER FLASH data retention time Tamb = +55 °C 25 years NEEC FLASH endurance (maximum number of programming cycles applied to the whole memory block performed by NXP static and dynamic wear leveling algorithm) 20 × 106 100 × 106 cycles Table 13. Non-volatile memory timing characteristics [1] Typical values are only referenced for information. They are subject to change without notice. [2] Given value specifies physical access times of FLASH memory only. SCL, SDA pads in open-drain mode.

applications

tCLKW, Tamb and VCC in their specified limits - 3.4 MHz tPD Power down duration time (I2C wake-up) CPU clock = 48 MHz [3] 67 μs tWKPD Wake-up from power down duration time (I2C wake-up) CPU clock = 48 MHz [4] 97 μs CPIN Pin capacitances RST_N, I2C_SDA, /I2C_SCL Test frequency = 1 MHz; Tamb = 25 °C - 10.5 pF tENalt ENA low time and Vout, Vcc low time for entering deep power down mode [5] 2 μs Ron Resistance of power switch Tamb=105 °C, Iload=25 mA, Vin=1.62 V

1.1 Ohm

Iout maximum current driving capability of pin Vout Tamb=105 °C 25 mA Inputs: RST_N (active only if ISO7816 UART interface is enabled) Table 14. Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1]; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS =

0 V; Tamb = -40 °C to + 105 °C

SCL, SDA pads in open-drain mode. [1] All appropriately marked values are typical values and only referenced for information. They are subject to change without notice. [2] tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall time between 70 % and 30 % of the signal amplitude. [5] Low glitches below 0.4 V on pin ENA and Vin, Vout, Vcc larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.

0.5 VDD

cycle) timing is measured at 50 % of VCC. time between 70 % and 30 % of the signal amplitude. Figure 10. External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL, values are only referenced for information. They are subject to change without notice. Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)

Plug & Trust Secure Element Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical values are only referenced for information. They are subject to change without notice. Symbol Parameter Conditions Min Typ Max Unit [3] [2] 0.25 x tIOWx_min μs tfIO I/O Input fall time Input/reception mode [1] [2] 1 μs [3] [2] 0.25 x tIOWx_min μs trOIO I/O Output rise time Output/transmission mode; CL = 30 pF [2] 0.1 μs tfOIO I/O Output fall time Output/transmission mode; CL = 30 pF [2] 0.1 μs Inputs: CLK and RST_N fCLK External clock frequency in ISO/IEC 7816 UART tCLKW, tamb and VCC in their specified limits [4] 0.85 11.5 MHz tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) 40 60 % trCLK CLK input rise time [5] [6] tfCLK CLK input fall time [2] [6] [6] trRST RST_N input rise time [2] 400 μs tfRST RST_N input fall time [2] [7] 400 μs Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)...continued minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example. [2] tr is defined as rise time between 10 % and 90 % of the signal amplitude. max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221. yields the allowed limits of 0.85 MHz and 11.5 MHz. [5] During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VCC − 0.3 V to VCC for a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC, see Figure 18. maximum allowed CLK rise and fall time is 50 ns, if 10 % of the CLK period is shorter than 50 ns. [7] The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively. Note: tf is defined as fall time between 90 % and 10 % of the signal amplitude. Conditions: Tamb = -25 °C to +85 °C, unless otherwise specified. Table 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise

Conditions: Tamb = -25 °C to +85 °C, unless otherwise specified. [1] Typical values (± 10 %) are only referenced for information. They are subject to change without notice. [2] The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip. [4] Measured with sine wave at LA, LB. [5] Parameter is valid in contactless ISO14443 compliant operation valid only.

14.3 I2C Bus Timings

Figure 11. I2C Bus Timings

Table 17. I2C Bus Timing Specification

14.4 EMC/EMI

EMC and EMI resistance according to IEC 61967-4.

15 Abbreviations

Table 18. Abbreviations

Table 18. Abbreviations...continued

Plug & Trust Secure Element

16 References

[1] NXP SE05x T=1 Over I2C Specification User manual, document number UM11225. Available on NXP website [2] SOT1969-1; HX2QFN20; Reel packing and package information. Available on NXP website [3] SE050 IoT Applet APDU Specification, document number AN 12413. Available on NXP website [4] SE050 configurations Application Note, document number AN12436. Available on NXP website [5] SE050 Use and Security Guidelines Application Note, document number AN12514. Availavle on NXP website. Product data sheet Rev. 3.4 — 28 March 2022 504934 27 / 32

• Update Section 2.2
• Update Section 2.3
• Update Section 4.1
• Update Section 4.1.1
• Update Section 6.1
• Update Table 3
• Update Figure 2 504933 2021-07-01 Product data sheet 504932 Modifications • Insert SE050F2 variant to Table 3 504932 2021-05-05 Product data sheet 504931 Modifications • updated Section 2.2
• updated Table 2
• Moved technical information on secure objects in Section 3.1.2 to the APDU specification [3]
• Replave "master/slave" with "controller/target"
• updated Figure 1
• Updated references 504931 2020-12-15 Product data sheet 504930 Modifications • updated Figure 2
• updated legal information
• corrected Section 1.3 504930 2020-05-12 Product data sheet 504913 Modifications • updated: Section 7.1.1
• updated: Table 6
• updated: Section 2.3
• added Section 3.4
• added Figure 3
• added Section 14.3
• updated Section 12
• updated Section 14.1.3
• updated Section 14.2
• updated Section 14.1.2
• updated Section 13 504913 20190607 Objective data sheet 504912 504912 20190510 Objective data sheet 504911 504911 20181122 Objective data sheet

Table 19. Revision history

Plug & Trust Secure Element

18 Legal information

18.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 3.4 — 28 March 2022 504934 29 / 32

Plug & Trust Secure Element Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

18.4 Licenses

ICs with DPA Countermeasures functionality NXP ICs containing functionality implementing countermeasures to Differential Power Analysis and Simple Power Analysis are produced and sold under applicable license from Cryptography Research, Inc.

18.5 Trademarks

Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. EdgeLock — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. JCOP — is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. Product data sheet Rev. 3.4 — 28 March 2022 504934 30 / 32

Plug & Trust Secure Element Tables Tab. 4. SE050 Ordering information for Tab. 10. Electrical DC characteristics of Input/ Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V; Tamb = -40 °C to Tab. 11. Electrical DC characteristics of I2C pads SDA, SCL. Conditions: VCC, VIN = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to + Tab. 12. Electrical characteristics of IC supply voltage VCC; VSS = 0 V; Tamb = -40 °C to Tab. 14. Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = Tab. 15. Electrical AC characteristics of IO1, IO2, Tab. 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, Figures Fig. 4. Pin configuration for HX2QFN20 Fig. 5. Characteristic supply voltage operating Fig. 8. Input characteristic of CLK when the IC is Fig. 10. External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL, and RST_N (see 1) and 2)) in open-drain Product data sheet Rev. 3.4 — 28 March 2022 504934 31 / 32