SDU01G64H3BF2MT-50R

SDU01G64H3BF2MT-50R ETC2 | Alldatasheet

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Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 Figure: mechanical dimensions1 1024MB DDR – unbuffered DDR1 UDIMM 184PIN DIMM SDU01G64H3BF2MT-xxR 1GByte in TSOP Technology RoHS compliant Environmental Requirements:  Operating temperature (TA) Standard Grade 0°C to 70°C  Operating Humidity 10% to 90% relative humidity, noncondensing  Operating Pressure 105 to 69 kPa (up to 10000 ft.)  Storage Temperature -55°C to 100°C  Storage Humidity 5% to 95% relative humidity, noncondensing  Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C Options:  Data Rate / Latency Marking DDR 400 MT/s CL3 -50 DDR 333 MT/s CL2.5 -60  Module densitiy 1024MB with 16 dies and 2 ranks  Standard Grade (TA) 0°C to 70°C Features:  184-pin 64-bit Dual-In-Line memory module. Double Date Rate synchronous DRAM Module for industrial applications  VDD 2.5V ±0.2V, VDDQ 2.5V ±0.2V Auto Refresh and self refresh modes: 7.8125 µs  2.5V I/O ( SSTL_2 compatible)  Serial Presence Detect with EEPROM  Gold-contact pad  This module family is fully pin and functional compatible to the JEDEC PC3200 spec. and JEDEC- Standard MO 224. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  DDR1-SDRAM component base: Micron MT46V64M8P-5B DIE rev. F  128Mx8 DDR1 SDRAM in TSOP66 package  Internal, pipelined double data rate (DDR) 2n- prefetch architecture  Programmable CAS Latency, Burst Length and Wrap Sequence 1if no tolerances specified ± 0.15mm

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 This Swissbit module family is industry standard 184-pin 8-byte Double Date rate synchronous SDRAM Dual-In-line Memory Modules (DIMMs), which are organized as x64 high speed memory arrays designed for use in non-parity applications. DIMMs are assembled in TSOP Technology. The passive devices and the EEPROM are SMD components. The DIMM use serial presence detec ts (SPD) implemented via serial EEPROM using the two -pin-I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Swissbit DIMMs provide a high performance, flexible 8-byte interface in a 133.35mm long footprint. All modules of the extended temperature grade have seen special tests during the manufacturing process to ensure proper operation according to the field of operation as stated in the environmental conditions. Module Configuration Organization DDR SDRAMs used Row Addr. Device Bank Addr. Column Addr. Refresh Module Bank Select 128M x 64bit 16 x 64M x 8bit (512Mbit) 13 BA0, BA1 11 8k S0#, S1# Module Dimensions in mm 133.35 (long) x 30(high) x 4.00 [max] (thickness) Product Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SDU01G64H3BF2MT-50R 1024MB 3.2 GB/s 5.0ns/400MT/s 3.0-3-3 SDU01G64H3BF2MT-60R 1024MB 2.7 GB/s 6.0ns/333MT/s 2.5-3-3 Pin Name A0-A12 Address Inputs BA0, BA1 Bank Address Inputs DQ0 – DQ63 Data Input/Output DM0-DM7 Input Data Mask RAS# Row Address Strobe CAS# Column Address Strobe WE# Read / Write Enable CKE0 Clock Enable CK0 – CK1 Clock Inputs, positive line CK0# – CK1# Clock Inputs, negative line DQS0- DQS7 Data strobes

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 3 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 S0# – S1# Chip Select VDD Power (2.5V± 0.2V) VDDQ DQ Power (2.5V±0.2V) VDDSPD SPD Power VREF Input/Output Reference Vss Ground SCL Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 – SA2 Slave Address Select Bus for Presence Detect NC No Connection Pin Configuration Front Side Back Side PIN # PIN Name PIN # PIN Name PIN # PIN Name PIN # PIN Name

1 VREF 47 DQS8 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 DM8

3 VSS 49 NC 95 DQ5 141 A10

4 DQ1 50 VSS 96 VDDQ 142 NC

5 DQS0 51 NC 97 DM0 143 VDDQ

6 DQ2 52 BA1 98 DQ6 144 NC

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDDQ 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 NC 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4

12 DQ8 58 VSS 104 VDDQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDDQ 61 DQ40 107 DM1 153 DQ44

16 NC 62 VDDQ 108 VDD 154 /RAS

17 NC 63 /WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDDQ

19 DQ10 65 /CAS 111 NC 157 /S0

20 DQ11 66 VSS 112 VDDQ 158 NC

21 CKE0 67 DQS5 113 NC 159 DM5

22 VDDQ 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 4 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 Front Side Back Side PIN # PIN Name PIN # PIN Name PIN # PIN Name PIN # PIN Name

26 VSS 72 DQ48 118 A11 164 VDDQ

27 A9 73 DQ49 119 DM2 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 NC 121 DQ22 167 NC

30 VDDQ 76 NC 122 A8 168 VDD

31 DQ19 77 VDDQ 123 DQ23 169 DM6

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDDQ

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 NC 128 VDDQ 174 DQ60

37 A4 83 DQ56 129 DM3 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 NC 180 VDDQ

43 A1 89 VSS 135 NC 181 SA0

44 NC 90 NC 136 VDDQ 182 SA1

45 NC 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 /CK0 184 VDDSPD

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 5 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 FUNCTIONAL BLOCK DIAGRAMM 1024DDR SDRAM DIMM 2RANKS; NON -ECC

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 6 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ TA ≤ + 70°C ; VDD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9 PARAMETER/ CONDITION SYMBOL MIN MAX UNITS Supply Voltage VDD 2.3 2.7 V I/O Supply Voltage VDDQ 2.3 2.7 V I/O Reference Voltage VREF 0.49 x VDDQ 0.51x VDDQ V I/O Termination Voltage (system) VTT VREF – 0.04 VREF + 0.04 V Input High (Logic 1) Voltage VIH (DC) VREF + 0.15 VDD + 0.3 V Input Low (Logic 0) Voltage VIL (DC) -0.3 VREF – 0.15 V INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤1.35V (All other pins not under test = 0V) II -10 µA OUTPUT LEAKAGE CURRENT (DQS are disabled; 0V ≤ VOUT ≤ VDDQ) IOZ -10 10 µA OUTPUT LEVELS: High Current (VOUT = VDDQ-0.373V,minimum VREF, minimum VTT ) Low Current (VOUT =0.373V, maximum VREF, maximum VTT ) IOH IOL -16.8 16.8 mA mA AC INPUT OPERATING CONDITIONS (0°C ≤ TA ≤ + 70°C ; VDD = +2.5V ± 0.2V, VDDQ = +2.5V ± 0.2V) see Note 1 on Page 9 PARAMETER/ CONDITION SYMBOL MIN MAX UNITS Input High (Logic 1) Voltage VIH (AC) VREF + 0.310 - V Input Low (Logic 0) Voltage VIL (AC) - VREF - 0.310 V I/O Reference Voltage VREF(AC) 0.49 x VDDQ 0.51x VDDQ V CAPACITANCE PARAMETER SYMBOL MIN MAX UNITS Input/Output Capacitance: DQ, DQS C10 4.0 5.0 pF Input Capacitance: Command and Address C11 18.0 27.0 pF Input Capacitance: /S 0,1 C11 18.0 27.0 pF Input Capacitance: CK, /CK C12 10.0 14.0 pF Input Capacitance: CKE C13 18.0 27.0 pF

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 7 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 IDD Specifications AND CONDITIONS (0°C ≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9 Parameter & Test Condition Symb. max. 3200-3033 2700-2533 Unit OPERATING CURRENT *) : One device bank; Active- Precharge; tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDDO 1280 1080 mA OPERATING CURRENT :*) One device bank; Active-Read-Precharge; Burst = 2; tRC= tRC (Min); tCK = tCK (Min);IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1920 1320 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (Min); CKE = (LOW) IDD2P 80 80 mA IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK (Min); CKE= HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 880 720 mA ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (Min);CKE = LOW IDD3P 720 560 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC= tRAS (Max); tCK = tCK (Min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 960 800 mA OPERATING CURRENT: Burst = 2; Reads; Continous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); IOUT = 0mA IDD4R 1560 1360 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1648 1440 mA AUTO REFRESH CURRENT tRC = tRC (Min) IDD5 5520 4640 mA tRC = 7.8125µs IDD6 176 160 mA SELF REFRESH CURRENT: CKE ≤ 0.2V IDD7 80 80 mA OPERATING CURRENT*): Four device bank interleaving READs (BL =4) with auto precharge, tRC = tRC (Min); tCK = tCK (Min); Address and control inputs change only during Active READ, or WRITE commands IDD8 3600 3280 mA *) Value ca lculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 8 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9 AC CHARACTERISTICS 3200-3033 2700-2533 PARAMETER SYMBOL MIN MAX MIN MAX Unit Access window of DQS CK/CK# tAC -0.50 +0.50 -0.70 +0.70 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK DQ and DM input hold time relative to DQS tDH 0.40 - 0.45 - ns DQ and DM input setup time relative to DQS tDS 0.40 - 0.45 - ns DQ and DM input pulse width ( for each input ) tDIPW 1.75 - 1.75 - ns Access window of DQS from CK/CK# tDQSCK -0.6 +0.6 -0.6 +0.6 ns DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS –DQ skew, DQS to last DQ valid, per group, per access tDQSQ - 0.40 - 0.45 ns Write command to first DQS latching transition tDQSS 0.72 1.28 0.75 1.25 tCK DQS falling edge to CK rising- setup time tDSS 0.2 - 0.2 - tCK DQS falling edge from CK rising- hold time tDSH 0.2 - 0.2 - tCK Half clock period tHP tch, tcl - tch, tcl - ns Data-out high-impedance window from CK/CK# tHZ +0.7 +0.7 ns Data-out low-impedance window from CK/CK# tLZ -0.7 - -0.7 - ns Address and control input hold time ( fast slew rate ) tIHF 0.6 - 0.75 - ns Address and control input setup time ( fast slew rate ) tISF 0.6 - 0.75 - ns Address and control input hold time ( slow slew rate ) tIHS 0.7 - 0.8 - ns Address and control input setup time ( slow slew rate ) tISS 0.6 - 0.8 - ns LOAD MODE REGISTER command cycle time tMRD 10 - 12 - ns Adress and control input pulse width (for each input) tIPW 2.2 - 2.2 - ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS ns Data hold skew factor tQHS - 0.5 - 0.6 ns

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 AC CHARACTERISTICS 3200-3033 2700-2533 PARAMETER SYMBOL MIN MAX MIN MAX Unit ACTIVE to PRECHARGE command tRAS 40 70.000 42 70.000 ns ACTIVE to READ with Auto precharge command tRAP 15 - 15 - ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 55 - 60 - ns AUTO REFRESH command period tRFC 70 - 72 - ns ACTIVE to READ or WRITE delay tRCD 15 - 15 - ns PRECHARGE command period tRP 15 - 15 - ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 10 - 12 - ns DQS write preamble tWPRE 0.25 - 0.25 - tCK DQS write preamble setup time tWPRES 0 - 0 - ns DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write recovery time tWR 15 - 15 - ns Internal WRITE to READ command delay tWTR 2 - 1 - tCK Data valid output window na tQH - tDQSQ tQH - tDQSQ ns REFRESH to REFRESH command interval tREFC - 70.3 - 70.3 µs Average periodic refresh interval 0 °C ≤ TCASE ≤ 85°C tREFI - 7.8 - 7.8 µs 85 °C < TCASE ≤ 95°C tREFI (IT) 3.9 3.9 Terminating voltage delay to VDD tVTD 0 - 0 - ns Exit SELF REFRESH to non-READ command tXSNR 70 - 75 - ns Exit SELF REFRESH to READ command tXSRD 200 - 200 - tCK Note 1: Values for AC timing, IDD, and electrical AC and DC characteristics might have been collected within the standard temperature range and at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified and for the corresponding field of operation according to the actual temperature grade of the module (extended E, I or W; refer to the environmental conditions for more details).

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 10 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 SERIAL PRESENCE -DETECT MATRIX BYTE DESCRIPTION 3200-3.0-3-3 2700-2.5-3-3

0 NUMBER OF SPD BYTES USED 0x80

1 TOTAL NUMBER OF BYTES IN SPD DEVICE 0x08

2 FUNDAMENTAL MEMORY TYPE 0x07

3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 0x0D

4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 0x0B

5 NUMBER OF PHYSICAL BANKS ON DIMM 0x02

6 MODULE DATA WIDTH 0x40

7 MODULE DATA WIDTH (continued) 0x00

8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) 0x04

9 SDRAM CYCLE TIME, (tCK )

(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200) 0x50 0x60

10 SDRAM ACCESS FROM CLOCK, (tAC)

(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200)) 0x70 0x70

11 MODULE CONFIGURATION TYPE 0x00

12 REFRESH RATE/ TYPE 0x82

13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) 0x08

14 ERROR- CHECKING SDRAM DATA WIDTH 0x00

15 MINIMUM CLOCK DELAY, BACK- TO- BACK

16 BURST LENGTHS SUPPORTED 0x0E

17 NUMBER OF BANKS ON SDRAM DEVICE 0x04

18 CAS LATENCIES SUPPORTED 0x1C 0x0C

19 CS LATENCY 0x01

20 WE LATENCY 0x02

21 SDRAM MODULE ATTRIBUTES 0x20

22 SDRAM DEVICE ATTRIBUTES: GENERAL 0xC0

23 SDRAM CYCLE TIME, (tCK)

(CAS LATENCY=2(2700, 2100) CL=2,5*(3200)) 0x60 0x75

24 SDRAM ACCESS FROM CK, (tAC)

(CAS LATENCY=2(2700, 2100) CL=2.5*(3200) 0x70

25 SDRAM CYCLE TIME, (tCK)

(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)) 0x75 0x00

26 SDRAM ACCESS FROM CK, (tAC)

(CAS LATENCY=1.5(2700, 2100) CL=2*(3200) 0x75 0x00

27 MINIMUM ROW PRECHARGE TIME, (tRP) 0x3C 0x48

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 0x28 0x30

29 MINIMUM RAS# TO CAS# DELAY, (tRCD) 0x3C 0x48

30 MINIMUM RAS# PULSE WIDTH, (tRAS) 0x28 0x2A

31 MODULE BANK DENSITY 0x80

32 ADDRESS AND COMMAND SETUP TIME, (tIS) 0x60 0x80

33 ADDRESS AND COOMAND HOLD TIME, (tIH) 0x60 0x80

34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0x40 0x45

35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0x40 0x45

41 MIN ACTIVE AUTO REFRESH TIME (tRC) 0x37 0x3C

42 MINIMUM AUTO REFRESH TO ACTIVE/

AUTO REFRESH COMMAND PERIOD, (tRFC) 0x46 0x48

43 SDRAM DEVICE MAX CYCLE TIME (tCKMAX) 0x30 0x30

44 SDRAM DEVICE MAX DQS-DQ SKEW TIME

(tDQSQ) 0x28 0x2D

45 SDRAM DEVICE MAX READ DATA HOLD SKEW

FACTOR (tQHS) 0x50 0x60

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 11 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 SERIAL PRESENCE -DETECT MATRIX (continued) BYTE DESCRIPTION 3200-3.0-3-3 2700-2.5-3-3 46-61 RESERVED 0x00

62 SPD REVISION 0x11

63 CHECKSUM FOR BYTES 0-62 0x10 0xC3

64 MANUFACTURER\`S JEDEC ID CODE 7F

65 MANUFACTURER\`S JEDEC ID CODE 7F

66 MANUFACTURER\`S JEDEC ID CODE 7F

67 MANUFACTURER\`S JEDEC ID CODE

(continued) DA

72 MANUFACTURING LOCATION

73-90 MODULE PART NUMBER (ASCII) “SDU01G64H3BF2MT-xx”

91 PCB IDENTIFICATION CODE x

92 IDENTIFICATION CODE (continued) x

93 YEAR OF MANUFACTURE IN BCD x

94 WEEK OF MANUFACTURE IN BCD x

95-98 MODULE SERIAL NUMBER x x Part Number Code S D U 01G 64 H3 B F 2 MT - 50 * R 1 2 3 4 5 6 7 8 9 10 11 12 13 * RoHs compl. Swissbit AG DDR-400MHz SDRAM DDR 184 Pin Unbuffered 2.5V Chip Vendor (Micron) module density (1GByte) 2 Module Ranks module data width Chip Rev. F PCB-Type (BDSA83A) Chip organisation x8 * optional / additional information

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 12 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13

Revision History

1.0 Initial Revision 15.07.2009 1.1 Corrected IDD table 09.01.2013

Data Sheet Rev.1.1 09.01.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 13 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 Locations Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 Swissbit Germany GmbH Wolfener Strasse 36 D – 12681 Berlin Germany Phone: +49 (0)30 93 69 54 – 0 Fax: +49 (0)30 93 69 54 – 55 Swissbit NA, Inc. 1202 E. Winding Creek Drive Eagle, ID 83616 USA Phone: +1 208 870 4525 Fax: +1 208 870 4525 Swissbit Japan, Inc. 3F Core Koenji, 2-1-24 Koenji-Kita, Suginami-Ku, Tokyo 166-0002 Japan Phone: +81 3 5356 3511 Fax: +81 3 5356 3512