SDM862 BURR-BROWN | Alldatasheet
Document overview
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Technical content
FEATURES
l COMPLETE 12-BIT DATA ACQUISITION SYSTEM IN A MINIATURE PACKAGE l INPUT RANGES SELECTABLE FOR UNIPOLAR OR BIPOLAR OPERATION l THROUGHPUT RATES: 862/3 872/3 8-BIT ACCURACY: 45kHz 67kHz 12-BIT ACCURACY: 33kHz 50kHz l SELECTABLE GAINS OF 1, 10, AND 100 l FULL MICROPROCESSOR COMPATIBLE INTERFACE l GUARANTEED NO MISSING CODES OVER TEMPERATURE l SURFACE-MOUNT OR PIN GRID ARRAY PACKAGE OPTIONS l HIGH RELIABILITY SCREENED VERSIONS AVAILABLE l FULL SPECIFICATION OVER THREE TEMPERATURE RANGES: l EVERY UNIT SUPPLIED WITH ELECTRICAL TEST DATA
APPLICATIONS
l INDUSTRIAL PROCESS MONITORING l AIRBORNE SYSTEMS MONITORING l ENGINE MONITORING FPO 43% l POWER PLANT MONITORING l SECURITY SYSTEMS MONITORING l AUTOMATIC TEST EQUIPMENT
DESCRIPTION
16 Single-Ended Inputs: SDM862 SDM872
8 Differential Inputs: SDM863 SDM873
33kHz Throughput Rate: SDM862 SDM863 50kHz Throughput Rate: SDM872 SDM873 The SDM components are complete, pin-compatible, data acquisition systems housed in a hermetically sealed 1"-square leadless chip carrier or a 1.1"-square pin grid array. The small package outlines and low power con- sumption provide an ideal data acquisition solution when space is at a premium. The devices comprise of an input multiplexer, instru- mentation amplifier with selectable gains, sample/hold amplifier and A/D converter with microprocessor inter- face and three-state buffers. The SDM family will accept unipolar or bipolar voltage inputs in the range 0 to +10V, ±5V and ±10V. For low- level signals, jumper-selectable gains of 10 or 100 can be applied. The number of input channels can be ex- panded by the addition of multiplexers. System integra- tion is simplified by the microprocessor interface and the facility of the sample/hold amplifier being con- trolled directly by the A/D converter. INA 16 CH MUX S/H ADC
12 Bits
FPO 46% International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 SDM862 SDM863 SDM872 SDM873
16 Single Ended/8 Differential Input
12-BIT DATA ACQUISITION SYSTEMS © 1988 Burr-Brown Corporation PDS-686F Printed in U.S.A. August, 1993
16 Single-Ended
8 Differential
*(Output MUX Minus) Only on SDM863/873 Input Channel Select Enable S/H Control Output MUX* Input Amp Gain Select Amp Output S/H Input S/H Output Hold Capacitor S/H Output Input Range Bipolar Offset Reference In Reference Out S/H Common Data Mode Byte Select Chip Select Chip Enable Read/Convert Status Reference Sense or SDM863, SDM873 SDM862, SDM872 SPECIFICATIONS ELECTRICAL At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. All grades are burned-in at +125°C for 48 hours min. ±5, ±10 0-10 SDM862/863/872/873 J, A, R SDM862/863/872/873 K, B, S PARAMETER MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 * Bits INPUT ANALOG Voltage Ranges: Bipolar V Unipolar V Input Impedance: On Channel 10 10 * Ω Off Channel 10 10 * Ω Input Capacitance: On Channel 20 * pF Off Channel 20 * pF CMRR (20VDC to 1kHz) 80 85 * * dB Crosstalk (20Vp-p, 1kHz) (1) –85 –80 * * dB Feedthrough (at 1kHz) (1) –85 –80 * * dB Offset (channel to channel) G = 1 (2) 30 100 * * µV Input Bias Current/Channel 1 5 * * nA Input Voltage Range (3) +10 +11 * * V –10 –15 * * V DIGITAL (7, 8) MUX Input Channel Select: Logic ‘1’ 5 30 * * µA Logic ‘0’ 5 30 * * µA MUX Input: Logic High 4.0 * V Logic Low 0.8 * V S/H Command: Logic ‘1’ 0.2 * nA Logic ‘0’ 5 30 * * µA ADC Section: Logic ‘1’ 10 * µA Logic ‘0’ 10 * µA TRANSFER CHARACTERISTICS ACCURACY Integral Linearity (4) ±0.024 ±0.012 %FSR Differential Linearity (4) ±0.024 * %FSR No Missing Codes Over Operating Temperature Range Gain Error (5): G = 1 0.5 * % G = 100 0.9 * % Unipolar Offset Error (5) 16 * mV Bipolar Offset Error (5) 50 * mV Noise Error (Measured at S/H Output) G = 1 0.5 1 * * mVp-p Droop Rate 50 500 * * µV/ms Temperature Coefficients: Unipolar Offset 20 15 ppm of FSR/ °C Bipolar Offset 30 25 ppm of FSR/ °C Full-Scale Calibration 60 35 ppm of FSR/ °C
At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. * Specification same as SDM862/863/872/873J, A, R grades. NOTES: (1) Measured at the same and hold output. (2) Measured with all input channels grounded. (3) The range of voltage on any input with respect to common over which accuracy and leakage current is guaranteed. (4) Applicable over full operating temperature range. NO MISSING CODES GUARANTEED OVER TEMPERATURE RANGE. (5) Adjustable to zero using external potentiometer or select-on-test resistor. (6) Specifications are at +25°C and measured at 50% level of transition. (7) When using TTL drivers a 1kΩ pull-up resistor should be used. (8) Muxes operate in a break-before-make manner. Unipolar Straight Binary (USB) Bipolar Offset Binary (BOB) SDM862/863/872/873 J, A, R SDM862/863/872/873 K, B, S PARAMETERS MIN TYP MAX MIN TYP MAX UNITS SYSTEM TIMINGS ADC Conversion Time: SDM862/SDM863 9 20 25 * * * µs SDM872/SDM873 9 12 15 * * * µs S/H Aperture Delay 50 * ns S/H Aperture Uncertainty 2 * ns TIMING Throughput (Serial Mode) SDM862/SDM863 22 * kHz SDM872/SDM873 28 * kHz (Overlap Mode): SDM862/SDM863 33 * kHz SDM872/SDM873 50 * kHz MULTIPLEXER (6) Switching Time (between channels) +1.5 * µs Settling Time (10V step to 0.02%) 2.5 * µs Enable Time ‘ON’ 1 2 * * µs INSTRUMENTATION AMPLIFIER (6) Settling Time (20V step to 0.01%) G = 1 5 12.5 * * µs G = 10 3 7.5 * * µs G = 100 4 7.5 * * µs Slew Rate 12 17 * * V/ µs S/H AMPLIFIER (6) Acquisition (10V step to 0.01%) 5 * µs Aperture Delay 50 * ns Hold Mode Settling Time 1.5 * µs Slew Rate 10 * V/ µs OUTPUT DIGITAL DATA Output Codes: Unipolar Bipolar Logic Levels: Logic 0 (Sink = 1.6mA) +0.4 * V Logic 1 (Source = 500µA) +2.4 * V Leakage (Data Bits Only), High-Z State –5 0.1 +5 * * * µA POWER SUPPLY REQUIREMENTS Rated Voltage: Analog (±VCC ) 14.25 15 15.75 ***V D C Digital (VDD ) 4.5 5 5.5 * * * VDC Supply Drain: +15V 13 22 * * mA –15V 22 30 * * mA +5V 11 15 * * mA Power Dissipation 580 855 * * mW TEMPERATURE RANGE Operating Temperature Range JH, KH/JL, KL 0 70 * * °C AH, BH/AL, BL –25 +85 * * °C RH, SH/RL, SL –55 +125 * * °C Storage Temperature Range –65 +150 * * °C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
SYMBOL PARAMETER MIN TYP MAX UNITS CONVERT MODE tdsc Status Delay from CE 100 200 ns thec CE Pulse Width 50 30 ns tssc CS to CE Setup 50 20 ns thsc CS Low During CE High 50 20 ns tsrc R/C to CE Setup 50 0 ns thrc R/C Low During CE High 50 20 ns tsac Byte Select to CE Setup 0 0 ns thac Byte Selected Valid During CE High 50 20 ns tc 86X Conversion Time: 12 Bit Cycle 9 20 25 µs
8 Bit Cycle 6 13 17 µs
tc 87X Conversion Time: 12 Bit Cycle 9 12 15 µs
8 Bit Cycle 6 8 10 µs
tdd Access Time from CE 75 150 ns thd Data Valid after CE Low 25 35 ns thl Output Float Delay 100 150 ns tssr CS to CE Setup 50 0 ns tsrr R/C to CE Setup 0 0 ns tsar Byte Select to CE Setup 50 25 ns thsr CS Valid after CE Low 0 0 ns thrr R/C High after CE Low 0 0 ns thar Byte Select Valid after CE Low 50 25 ns ths 86X Status Delay after Data Valid 100 500 1000 ns ths 87X Status Delay after Data Valid 100 300 600 ns ABSOLUTE MAXIMUM RATINGS (1) DBO CE tHEC tSSC tSRC tHSC tHRC tHAC tSAC tDSC tC High Impedance CS R/C STS DB11– Byte Select NOTE: (1) Absolute maximum ratings are limiting values applied individually, beyond which the serviceability of the circuit may be impaired. Functions operation under any of these conditions is not necessarily implied. /QM HIGH RELIABILITY SCREENING High Power Internal READ CYCLE TIMING CE tSSR tSRR tHRR tHS tHD High-Z CS R/C tHSR tHARtSAR Data Valid tHL tDD STS Byte Select DB11– DBO
NOTE: (1) 16 single-ended inputs, LCC package, with accuracy of 0.24% FSR. Temp Range of 0°C to +70°C and throughput of 33kHz = SDM862JL. LCC, PGA Accuracy Temperature LCC, PGA Accuracy Temperature Product Input Package (% FSR) Throughput Range ( °C) Product Input Package (% FSR) Throughput Range ( °C) SDM862J 16SE L,H ±0.024 33kHz 0 to +70 SDM863J 8DIF L, H ±0.024 33kHz 0 to +70 SDM862K 16SE L,H ±0.012 33kHz 0 to +70 SDM863K 8DIF L, H ±0.012 33kHz 0 to +70 SDM862A 16SE L,H ±0.024 33kHz –25 to +85 SDM863A 8DIF L, H ±0.024 33kHz –25 to +85 SDM862B 16SE L,H ±0.012 33kHz –25 to +85 SDM863B 8DIF L, H ±0.012 33kHz –25 to +85 SDM862R 16SE L,H ±0.024 33kHz –55 to +125 SDM863R 8DIF L, H ±0.024 33kHz –55 to +125 SDM862S 16SE L,H ±0.012 33kHz –55 to +125 SDM863S 8DIF L, H ±0.012 33kHz –55 to +125 SDM872J 16SE L,H ±0.024 50kHz 0 to +70 SDM873J 8DIF L,H ±0.024 50kHz 0 to +70 SDM872K 16SE L,H ±0.012 50kHz 0 to +70 SDM873K 8DIF L,H ±0.012 50kHz 0 to +70 SDM872A 16SE L,H ±0.024 50kHz –25 to +85 SDM873A 8DIF L,H ±0.024 50kHz –25 to +85 SDM872B 16SE L,H ±0.012 50kHz –25 to +85 SDM873B 8DIF L,H ±0.012 50kHz –25 to +85 SDM872R 16SE L,H ±0.024 50kHz –55 to +125 SDM873R 8DIF L,H ±0.024 50kHz –55 to +125 SDM872S 16SE L,H ±0.012 50kHz –55 to +125 SDM873S 8DIF L,H ±0.012 50kHz –55 to +125 ORDERING INFORMATION (1) PACKAGE DRAWING PRODUCT DESCRIPTION NUMBER (1) PC862/863-1 LCC (Socketed) Evaluation PCB(2) 907 PC862/863-2 PGA Evaluation PCB 906
PACKAGE INFORMATION
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Socket is MC0068-1.
+15V (1) –15V (1) +5V (2) STATUS D11 D10 MUX ADD2 MUX ADD1 MUX ADD0 MUX ENABLE CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 S/H IN NC S/H OUT HOLD CAP S/H OUT MUX ADD3 DCOM (1) CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 RG G10 G100 MUX OUT +/AMP IN+ AMP IN– NC AMP SENSE S/H COM (2) S/H CONT BYTE SELECT CS DATA MODE R/C CE +15V (2) REF OUT ACOM (2) REF IN BIP OFF ADC IN (10V) ADC IN (20V) –15V (2) DCOM (2) MUX INA A/D DOTTED LINE SHOWS SUPPLY SEPARATION PIN GROUPING BY FUNCTION S/H AMP OUT AMP REF +15V (1) –15V (1) +5V (2) STATUS D11 D10 MUX ADD2 MUX ADD1 MUX ADD0 MUX ENABLE CH0+ CH1+ CH2+ CH3+ CH4+ CH5+ CH6+ CH7+ S/H IN NC S/H OUT HOLD CAP S/H OUT S/H COM (2) S/H CONT BYTE SELECT CS DATA MODE R/C CE +15V (2) REF OUT ACOM (2) REF IN BIP OFF ADC IN (10V) ADC IN (20V) –15V (2) DCOM (2) MUX INA A/D DOTTED LINE SHOWS SUPPLY SEPARATION PIN GROUPING BY FUNCTION S/H NC DCOM (1) CH0– CH1– CH2– CH3– CH4– CH5– CH6– CH7– RG G10 G100 MUX OUT +/AMP IN+ AMP IN– MUX OUT– AMP SENSE TOP VIEW SDM863/SDM873 TOP VIEW SDM862/SDM872
PIN DESIGNATION DEFINITION COMMENTS SDM8X2 = SDM862 OR SDM872 CH0 to CH15 Channel Inputs Analog Inputs (Total 16) for single-ended and differential operation. Unused CH0 to CH7 (+, –) inputs must be connected to analog common. (PINS 40 to 47, 54 to 61) MUX OUT+/AMP IN+ MULTIPLEXER “HI” OUTPUT On the SDM8X2 this is the multiplexer output. On the SDM8X3 it is the output of the positive selected inputs. It is connected internally to the (PIN 65) positive input of the instrumentation amplifier. MUXOUT (Pin 67) MULTIPLEXER “LO” OUTPUT This pin is used on the SDM8X3 only. It should be connected to the negative input of the instrumentation amplifier. AMP IN (Pin 66) Negative input of instrumentation On the SDM8X2 this should be connected to analog common. On the amplifier SDM8X3 it should be connected to Muxout—(Pin 67). AMP OUT (Pin 1) Output of instrumentation amplifier This pin should be connected to the input of the S/H amplifier (Pin 39). AMP SENSE (Pin 68) Output sense line of instrumentation This pin will normally be connected direct to AMP OUT (Pin 1). amplifier AMP REF (Pin 2) Reference for amplifier output This pin will normally be connected to analog common. Care should be taken to minimize tracking and contact resistance to analog common to optimize system accuracy. S/H OUT (Pins 35/37) Output of sample/hold amplifier Two pins are provided to facilitate a guard ring around the hold capacitor pin. These pins should be connected to either ADC in (20V) or ADC in (10V) depending on the desired range. HOLD CAP (Pin 36) Connection for hold capacitor on The tracking to the hold capacitor should be as short as possible and a S/H amplifier guard ring employed using Pins 35 and 37. ADC IN (20V); ADC IN (10V) Inputs to A/D converter Connect to S/H amplifier output. Use appropriate pin for desired range. (Pins 21, 22) RG, G10, G100 Gain settling pins on instrumentation For Gain = 1, no connections. For Gain = 10, connect G10 to RG. (Pins 62, 63, 64) amplifier For Gain = 100, connect G100 to RG. REF OUT (PIN 26) 10V Reference voltage This is the reference voltage for the A/D converter. REF IN, BIP OFF Reference input and offset input to Connect trim potentiometers (or select-on-test resistors) to these pins for (Pins 24, 23) A/D converter unipolar or bipolar operation as shown in Figures 12, 13. S/H IN (Pin 39) Input to sample/hold amplifier Connect to amp out (Pin 1). MUX ENABLE (Pin 48) Multiplex enable/disable Logic ‘1’ on this pin will enable a selected channel on the internal multiplexer. Logic ‘0’ de-selects all channels. MUX ADD0 to MUX ADD3 Address inputs for channel selection These address lines select a particular channel as specified in Figure 24. (Pins 49 to 52) S/H CONT (Pin 33) Track/Hold control on S/H amplifier Logic ‘1’ holds an analog value for conversion by the A/D converter. This line may be controlled by the status (Pin 6) of the converter to simplify external timing control. S/H COM (Pin 34) Reference for S/H logic control Connect to digital common. D0 to D11 (Pins 7 to 18) 3-state digital outputs The 12- or 8-bit result of a conversion is available as output on these pins (D0-LSB, D11-MSB). STATUS (Pin 6) Status of A/D conversion This output is at logic ‘1’ while the internal A/D converter is carrying out a conversion. This pin may be used to directly control the S/H amplifier. CE (Pin 28) Chip enable This input must be at logic ‘1’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). CS (Pin 31) Chip select This input must be at logic ‘0’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). R/C (Pin 29) Read/convert Data can be read when this pin is logic ‘1’ or a conversion can be initiated when this pin is logic ‘0’. This pin is typically connected to the R/W control line of a microprocessor-based system (see Figures 10, 17, 18, 19, 20). DATA MODE (Pin 30) Select 12- or 8-Bit Data When data mode is at logic ‘1’ all 12 output data bits are enabled simultaneously. When data mode is at logic ‘0’ MSBs and LSBs are controlled by byte select (Pin 32). BYTE SELECT (Pin 32) Byte address, short cycle When reading output data, byte select at logic ‘0’ enables the 8 MSBs. Byte select at logic ‘1’ enables the 4 LSBs. The 4 LSBs can therefore be connected to four of the MSB lines for inter-connection to an 8-bit bus. In start convert mode, logic ‘0’ enables a 12-bit conversion while logic ‘1’ will short cycle the conversion to 8 bits (see Figure 10). +15V(1), +15V(2)(Pins 3, 27) Power Supply Connect to +15V supply using decoupling as indicated in Figures 15, 16. –15V(1), –15V(2)(Pins 4, 20) Power Supply Connect to –15V supply using decoupling as indicated in Figures 15, 16. ACOM(2) (Pin 25) Analog Common Analog common connection. Note that a common (including digital common) should be connected together at one point close to the device. DCOM (1) (Pin 53) Reference for MUX logic control. Connect to digital common. +5V (Pin 5) Logic power supply Connect to +5V digital supply line with decoupling as in Figures 15, 16. DCOM(2) (Pin 19) Reference for A/D converter control Connect to S/H common at one point close to device. lines NC (Pin 38) No internal connection
SDM should be offset nulled with the S/H in hold mode.
- The converter can convert unipolar and bipolar signals in
comply with the SDM timing considerations. Figure 8. Droop rate for the SDM is specified with a hold FIGURE 7. Setting Programmable Gains. may be realized with Figure 7. FIGURE 8. Acquisition Time vs Hold Capacitance for a 10V Step Settling to ±10mV of Final Value.
0 X X X X None
FIGURE 9. Control Input Truth Table.
transition value versus a change in ambient temperature. terminology defined for the 574 converter several years ago. (bipolar zero) at the output code transition 7FFH to 800H. sition value versus a change in ambient temperature. a change in ambient temperature. FIGURE 10. Serial and Overlap Modes of Operation.
power supplies to the two sections were directly connected. or high input signal noise immunity is desired. should result whereby all grounds route to a central point. NOTE: (1) 10µF tantalum in parallel with 100nF ceramic. FIGURE 15. Recommended Decoupling of Power Supplies.
4 Opto-Couplers
FIGURE 16. Galvanic Isolation Between Analog and Digital Signals.
FIGURE 17. The SDM Connected to an Input/Output Port.
8255 Port
FIGURE 18. The SDM Connected to a 16-Bit-BUS.
FIGURE 19c. IBM PC SDM Interface. FIGURE 20. SDM on the 6502 BUS.
8 Bit
1700 Hick Road, Ingrow Bridge,
factors will depend on his application and situation. by the user can be examined. applications very few external components will be required. won particular application or problem area. —68 pin LCC socket (Burr-Brown Part No. MC0068). —8 differential or 16 single-ended inputs. BUS systems (connection by wire wrap techniques). —2 voltage regulators (15V). —LC power supply decoupling. common lines are low resistance and low inductance. voltage may vary from ±17V to ±25V. FIGURE 25. Channel Select Truth Table.
measurements should be limited to applications where cur- rent sources are measured via shunts or where signal volt- ages in the range of some volts are available. Bus-Interface As the outputs of the SDM are BUS compatible, only a few ICs are necessary to interface to various BUS systems. For such interfacing, 20-pin IC sockets are provided. Wiring is by wire wrap to the BUS connector. Setting of Various Modes Circuit Board positions are provided for the connection of ‘jumpers’ as follows: J1, J2—ADC analog input volt age settings. J3—Set for differential (SDM8X3) or single ended (SMD8X2) operation. J4—Instrumentation amplifier gain settings. (a) 16 input channels, single ended: —Use SDM8X2 —Consider single-ended filtering —Connect J3 (pin 66) to common (b) Differential inputs —Use SDM8X3 —Consider differential filtering —Connect J3 (pin 66) to pin 67 (c) Analog input ±10V Connect J1 to pin 21 Connect J2 to pot P2 (100Ω ) ±5V Connect J1 to pin 22 Connect J2 to pot P2 (100Ω ) 0 to +10V: Connect J1 to pin 22 Connect J2 to junction of R 1/R2 (d) Gain of instrumentation amplifier G = 1 Jumper J4 open G = 10 Jumper J4 to pin 63 G = 100 Jumper J4 to pin 64 Other gains: use additional resistor between pin 62 and pin 63 (see section on Instrumentation Amplifier) as low tempco resistor is recommended in order to minimize gain drift.
INPUT FILTER AND PROTECTION CIRCUITRY SINGLE-ENDED DIFFERENTIAL 10k Ω C g +15V –15V R f 0.47µF C15 C16 26-Pin Connector SDM Pins Channel Numbers D15 D16 D31 D32 R10 R11 R12 R13 R14 R15 R16 R17 R18 10k R11 Ω 10nF 1% C17 0.47µF C f Channel Numbers C g R f +15V –15V SDM Pins 26-Pin Connector R13 R14 R15 R16 R17 R18 R10 Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to CommonPins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common
D D B B B B B B B B B B B C34 C33 C32 C31 +5V E E C28 C30 C29 C26 100 INA- MUX- A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A BIP UNI 20V ST C36 C35 IC2 IC3 C37 C38 IC5 D16 D32 D15 D31 D14 D30 D13 D29 R17 R16 C13 C15 C12 R14 R11 C10 R12 C11 R13 S/H OUT S/H IN RG C C A A IC1 ©Burr-Brown Ltd 1989 PC862/863-1 REV B G C23 C24 S/H BS CS DM R/C CE Pin Out For LCC Socket SDM C27 10V C14 NOTE: (1) NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 (2) NOT DRAWN TO SCALE
P.C.B. LAYOUT NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2
CIRCUIT DIAGRAM—SDM PC BOARD P.C.B. COMPONENTS PARTS LIST R1 100 Ω C26 10nF Ceramic P3 100k Ω 0–10V Range Only R2 100k Ω C27, C29, C35 L1...L3 100 µH (Decoupling) C1...C16 0.47 µF—Single Ended Input Mode C28, C30, C31 D33, D34 1N4007 10nF 1%—Differential Input Mode C36, C37, C40 78 MC78M15CG C25 4.700pF (Polypropylene, Polystyrene or P1 100 Ω 74175 74LS175 TeflonTM ) P2 100 Ω ±5V, ±10V Range Only LCC Socket MC0068 UNLESS OTHERWISE MARKED—RESISTORS ARE 1/4W, 5%, CAPACITORS ARE 10% 10µF Tantalum (Decoupling) 100nF Ceramic (Decoupling) For 0–10V Settling Teflon™ E.I. du Pont de Nemours & Co. G10 R Sense IN+ Out– Out+ Ref Out Ref In Bip Off EN C26 +5V CS CE RC +15V –15V C27 G100 Out C35 C36 +15V –15V C40 C38 C39 C37 C30 C29 C33 C34 C28 C31 C32 R G +5V D11 10V 20V BS Status Data M In In ADC SHC/COM C25 4700pF INA In Out SH CH +5V CL 74175 +5V J1, J2 = ±10V J3 = 8 Diff Inputs J4 = (G = 10) DCOM ACOM 100µH INX– = Wirewrap Posts Ref MUX DCOM ACOM G 1kΩ +5V
MECHANICAL (P.G.A.) INCHES MILLIMETERS DIM MIN MAX MIN MAX A 1.087 1.109 27.610 28.169 B 1.087 1.109 27.610 28.169 C .095 .120 2.413 3.048 D .162 .198 4.115 5.029 E .045 .055 1.143 1.397 F .045 .055 1.143 1.397 G .016 .020 .406 .508 H .100 BASIC 2.540 BASIC J .100 BASIC 2.540 BASIC NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. TERMINATION: Gold plated KOVAR. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 9 grms (0.32 oz) Package Number 906 TOP VIEW Bottom VIEW A B C E DF G Pin 1 Identifier 4 5 8 9 10 11 12 13 14 15 16 17 18 19 34 35 3637 3839 4041 4243 4445 4647 4849 5051 5355575961636567 56586062646668 H J Package Number 907 — TOP VIEW MECHANICAL (L.C.C.) INCHES MILLIMETERS DIM MIN MAX MIN MAX A .945 .965 24.003 24.511 B .945 .965 24.003 24.511 C .076 .094 1.934 2.388 D .841 .859 21.361 21.819 E .841 .859 21.361 21.819 F .755 .785 19.177 19.939 G .755 .785 19.177 19.939 H .800 BASIC 20.320 BASIC J .027 .033 .686 .838 K .045 BASIC 1.143 BASIC L .050 BASIC 1.270 BASIC NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. TERMINATION: Gold plated nickel on refractory metalliza- tion. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 4.37 grms (0.124 oz) A D F GEB 6866 Pin 1 Identification C K HJ L