STGIPL14K60 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 21

Technical content

Datasheet sections

  • 1 Internal block diagram and pi n configuration
  • 2 Electrical ratings
  • 2.1 Absolute maximum ratings
  • 2.2 Thermal data
  • 3 Electrical characteristics
  • 3.1 Control part
  • 3.1.1 NTC thermistor
  • 3.1.2 Dead time
  • 4 Smart shutdown function
  • 5 Applications information
  • 5.1 Recommendations
  • 6 Package mechanical data
  • 7 Revision history

Features

■ 14 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and free- wheeling diodes ■ 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors ■ Internal bootstrap diode ■ Interlocking function ■ 5 kΩ NTC for temperature control ■ VCE(sat) negative temperature coefficient ■ Short-circuit rugged IGBTs ■ Under-voltage lockout ■ DBC fully isolated package ■ Isolation rating of 2500 Vrms/min ■ Smart shut down function ■ Op-amps for advanced current sensing ■ Comparators for fault protection against over current and short-circuit

Applications

■ 3-phase inverters for motor drives ■ Home appliances, such as washing machines, refrigerators, air conditioners

Description

The STGIPL14K60 intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It mainly targets low power inverters for applications such as home appliances and air conditioners. It combines ST proprietary control ICs with the most advanced short circuit rugged IGBT system technology. Please refer to dedicated technical note TN0107 for mounting instructions. AM01193v1 SDIP-38L Table 1. Device summary

1 Internal block diagram and pin configuration

Figure 1. Internal block diagram

Table 2. Pin description

10 V boot V Bootstrap voltage for V phase

11 LIN V Low side logic input for V phase

12 HIN V High side logic input for V phase

13 OP- V Opamp inverting input for V phase

14 OP OUT V Opamp output for V phase

15 OP+ V Opamp non inverting input for V phase

16 CIN V Comparator input for V phase

17 OUT W High side reference output for W phase

18 V boot W Bootstrap voltage for W phase

19 LIN W Low side logic input for W phase

20 HIN W High side logic input for W phase

21 OP- W Opamp inverting input for W phase

22 OP OUT W Opamp output for W phase

23 OP+ W Opamp non inverting input for W phase

24 CIN W Comparator input for W phase

25 V CC Low voltage power supply

26 SD / OD Shut down logic input (active low) / open drain (comparator output)

27 GND Ground

2 NTC thermistor terminal 2

29 T 1 NTC thermistor terminal 1

30 N W Negative DC input for W phase

31 W W phase output

32 P Positive DC input

33 N V Negative DC input for V phase

34 V V phase output

Figure 2. Pin layout (bottom view)

35 P Positive DC input

36 N U Negative DC input for U phase

37 U U phase output

38 P Positive DC input

Table 2. Pin description (continued)

2 Electrical ratings

2.1 Absolute maximum ratings

Table 3. Inverter part

  1. Applied between HIN i, LINi and GND for i = U, V, W
  2. Calculated according to the iterative formula:
  3. Pulse width limited by max junction temperature

Table 4. Control part

2.2 Thermal data

Table 5. Total system Table 6. Thermal data

3 Electrical characteristics

switching time of IGBT itself under the internally given gate driving condition. Table 7. Inverter part

  1. Applied between HIN i LINi and GND for i = U, V, W (LIN inputs are active-low).

3.1 Control part

Table 8. Low voltage power supply Table 9. Bootstrapped voltage Table 10. Logic inputs

Table 10. Logic inputs (continued) Table 11. OPAMP characteristics (V CC = 15 V)

  1. The direction of input current is out of the IC.

Table 12. Sense comparator characteristics (V CC = 15 V)

3.1.1 NTC thermistor

Table 14. NTC thermistor Symbol Parameter Test cond itions Min. Typ. Max. Unit. Figure 7. NTC resistance vs temperature

3.2 Waveforms definitions

Figure 8. Dead time and inte rlocking waveforms definitions

4 Smart shutdown function

mono-stable circuit, which implements a protection time that follows the fault condition. Figure 9. Smart shutdown timing waveforms

5 Applications information

Figure 10. Typical application circuit

5.1 Recommendations

  • To prevent the input signals oscillation, the wiring of each input should be as short as possible.
  • By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible.
  • Each capacitor should be located as nearby the pins of IPM as possible.
  • Low inductance shunt resistors should be used for phase leg current sensing.
  • Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance.
  • The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info).

Table 15. Recommended operating conditions

6 Package mechanical data

specifications, grade definitions and product status are available at: www.st.com. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-38L mechanical data

Figure 11. SDIP-38L drawing dimensions

7 Revision history

Table 17. Document revision history Minor text changes to improve readability. Document status promoted from preliminary data to datasheet. IC(RMS) current vs. fsine(1).