SD60C31 AUK | Alldatasheet

Document overview

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Technical content

Features

  • 8-bit CPU optimized for control applications. • Power control modes.
  • Pin-to-pin compatible with intel's 80C51/80C31.
  • 60C51 low power mask programmable ROM • 60C31 low power CPU only
  • 64K Program Memory Space, Data Memory space
  • 32K programmable I/O lines. • Two 16bit timer/counters
  • High performance CMOS process. • 5 interrupt sources.
  • 2 Level programmable serial port • 3.5 to 12MHz @ 5V ± 20%

Ordering Information

Type NO. Marking Package Code Type NO. Marking Package Code SD60C31 SD60C31 PLCC44 SD60C31P SD60C31 DIP40 SD60C51 SD60C51 PLCC44 SD60C51P SD60C51 DIP40 O u t l i n e D i m e n s i o n s u n i t : mm SSeemmiiccoonndduuccttoorr 0.120 (3.048) 0.090 (2.286) 0.048 (1.219) 0.042(1.067) 45 o 0.69 5 ( 17 .65 3) 0.68 5 ( 17 .39 9) 0.65 6 ( 16 .66 2) 0.65 0 ( 16 .51 0) 0.695 (17.653) 0.685 (17.399) 0.656 (16.662) 0.650 (16.510) 0.05 0 ( 1.2 70 ) 0.63 0 ( 1 6.00 2) 0.59 0 ( 1 4.90 6) SEATING PLANE MIN 0.020 (0.508) BASE PLANE 0.180 (4.572) 0.165 (4.191) 40 21 1 20 13.4 0.2 15.24 15MAX 0.25 0.5MIN 4.5 0.3 3.5 0.3 50.7±0.2 P L C C 4 4 D I P 4 0

Characteristic Rating Unit Ambient temperature under bias 0 ~+70 °C Storage temperature -65 ~ +150 °C Voltage on any pin to Vss -0.5~Vcc + 0.5 V Maximum IOL per I/O pin 15 ㎃ Power dissipation 1 Watt B l o c k D i a g r a m

Description

The AUK 60C31/P 60C51/P is a high-performan ce micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C51 contains a 4K ×8 ROM, a 128 ×8 RAM, 32I/O lines, two 16-bit counter/times, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multi- processor communication, I/O expansion or fu ll duplex UART, and on-chip oscillator and clock circuists. In addition, the device has tow software selectable modes of power reduction idle mode and powerdown mode. The idle mode freezes the CPU while allowing the RAM, times, serial port, and interrupt system to continue functioning. SD60C31/P SD60C51/P Interrupt Control SFR Timer 1 CPU Osc Bus Control Four I/O Ports Serial Port Timer 0 128 RAM ROM External Interrupts Counter Input TxD RxD P0 P2 P1 P3 Address/Data Figure 60C51L Block Diagram- Figure DMC60C51 Block Diagram -

VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP40), PIN 36~43 (PLCC44) P ort 0 is an 8bit open drain bi -directional I/O port. Port 0 pins that have 1's written to the them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's. SD60C31/P SD60C51/P 44PLCC P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC V CC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 40DIP T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 INT0/P3.2 TxD/P3.1 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 V SS VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/V PP PSEN ALE/PROG P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 DIP40 PLCC44

Pin Description(continued) Port 1 : PIN 1~8 (DIP40), PIN 2~9 (PLCC44) Port 1 is an 8-bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups. Port 2 : PIN 21~28 (DIP40), PIN 24~31 (PLCC44) Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1's. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register Port 3 : PIN 10~17 (DIP40), PIN 13~19 (PLCC44) Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below : Port PIN PIN NO. Alternate Function P3.0 10 RxD (Serial input port) P3.1 11 TxD (Serial output port) P3.2 12 INT0 (external interrupt 0) P3.3 13 INT1 (external interrupt 1) P3.4 14 T0 (Timer 0 external input) P3.5 15 T1 (Timer 1 external input) P3.6 16 WR (external data memory write strobe) P3.7 17 RD (external data memory read strobe) RST : PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits Power-On reset using only an external capacitor to VCC. SD60C31/P SD60C51/P

Pin Description(continued) ALE : PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing of clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX instruction. Otherwise, the pin is weakly pulled high. PSEN : PIN 29 (DIP40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA : PIN 31 (DIP40), PIN 35 (PLCC44) External access enable. EA must be strapped to V SS in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. If EA is strapped to V CC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1 : PIN 19 (DIP40), PIN 21 (PLCC44) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. NC : PIN1, 12, 23, 34 (PLCC44) Non connection pins. XTAL2 : PIN 18 (DIP40), PIN 20(PLCC44) Output from the inverting oscillator amplifier SD60C31/P SD60C51/P

Pin Description(continued)

  • Crystal oscillator Idle Mode In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on -chip RAM and special function register retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held acti ve long enough to allow the oscillator to restart and stabilize. The control bits for the reduced power modes are in the special function register PCON. Table Status of the external pins during Idle and power down modes. Mode Program memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 Float Data Data Data SD60C31/P SD60C51/P 30pF 30pF VSS XTAL1 XTAL2

Electrical Characteristics(DC) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP. MAX UNIT VIL Input low voltage, except EA -0.5 0.2VCC- 0.1 V VILI Input low voltage to EA 0 0.2VCC- 0.3 V VIH Input high voltage, except XTAL1,RST 0.2VCC+ 0.9 V CC+0.5 V VIHI Input high voltage to XTAL1, RST 0.7 V CC V CC+0.5 V VOL Output low voltage to ports VOLI Output low voltage to ports 0, ALE, PSEN IOL=3.2 ㎃ 0.45 V VOH Output high voltage to ports 1,2,3,ALE,PSEN IOH=-60 ㎂ IOH=-25 ㎂ IOH=-10 ㎂ 2.4 0.75VCC 0.9VCC V VOHI Output high voltage (port 0 in external bus mode) IOH=-800 ㎂ IOH=-300 ㎂ IOH=-80 ㎂ 2.4 0.75VCC 0.9VCC V IIL Logical 0 input current to ports 1,2,3 VIN=0.45V -50 µA ITL Logical 1 to 0 transition current to port 1,2,3 VIN=2V -650 µA ILI Input leakage current to port 0, EA 0.45<VIN< VCC ±10 µA ICC Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode See note1 1.7 mA mA µA RRST Internal reset pull-down resistor 50 150 kohm C10 Pin capacitance 10 pF Note : 1. See figure 8 through 11 for I CC test conditions. Minimum VCC for power down is 2V. SD60C31/P SD60C51/P

Electrical AC Characteristics(AC) 12MHz CLOCK V ARIABLE CLOCKSYM -BOL FIGU RE PARAMETER MIN MAX MIN MAX UNIT 1/tCLC L Oscillator frequency : Speed versions 60C31/60C51 3.5 12 MHz tLHLL 1 ALE pulse width 127 2t CLCL-40 ns tAVLL 1 Address valid to ALE low 28 t CLCL-55 ns tLLAX 1 Address hold after ALE low 48 t CLCL-35 ns tLLIV 1 ALE low to valid instruction in 234 4t CLCL-100 ns tLLPL 1 ALE low to PSEN low 43 t CLCL-40 ns tPLPH 1 PSEN pulse width 205 3t CLCL-45 ns tPLIV 1 PSEN low to valid instruction in 145 3 CLCL-105 ns tPXIX 1 Input instruction hold after PSEN 0 0 ns tPXIZ 1 Input instruction float after PSEN 59 t CLCL-25 ns tAVIV 1 Address to valid instruction in 312 5t CLCL-105 ns tPLAZ 1 PSEN low to address float 10 10 ns Data Memory tRLRH 2.3 RD pulse width 400 6t CLCL-100 ns tWLWH 2.3 WR pulse width 400 6t CLCL-100 ns tRLDV 2.3 RD low to valid data in 252 5t CLCL-165 ns tRHDX 2.3 Data hold after RD 0 0 ns tRHDZ 2.3 Data float after RD 97 2t CLCL-70 ns tLLDV 2.3 ALE low to valid data in 517 8t CLCL-150 ns tAVDV 2.3 Address to valid data in 585 9t CLCL-165 ns tLLWL 2.3 ALE low to RD or WR low 200 300 3t CLCL-50 3t CLCL+50 ns tAVWL 2.3 Address valid to WR low or RD low 203 4t CLCL-130 ns tQVWX 2.3 Data valid to WR transition 23 t CLCL-60 ns tWHQZ 2.3 Data hold after WR 33 t CLCL-50 ns tRLAZ 2.3 RD low to address float 0 0 ns tWHLH 2.3 RD or WR high to ALE high 43 123 t CLCL-40 t CLCL+40 ns External Clock tCHCX 4 High time 20 20 ns tCLCX 4 Low time 20 20 ns tCLCH 4 Rise time 20 20 ns tCHCL 4 Fall time 20 20 ns SD60C31/P SD60C51/P