SD60C32 AUK | Alldatasheet

Document overview

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Technical content

Features

  • 8-bit CPU optimized for control applications. • MCS-51 fully compatible instruction set
  • Pin-to-pin compatible with intel's 80C52/80C32. • ONCETM (ON-circuit emulation) mode
  • 256 Bytes of on-chip data RAM. • Power control modes
  • 60C52 low power CPU only. -Idle mode
  • 32 programmable I/O lines. -Power down mode
  • Three 16bit timer/counters. • 6 interrupt source
  • TTL and CMOS compatible logic levels
  • 64K external program memory space and data memory space.

Ordering Information

Type NO. Marking Package Code Type NO. Marking Package Code SD60C32 SD60C32 PLCC44 SD60C32P SD60C32 DIP40 SD60C52 SD60C52 PLCC44 SD60C52P SD60C52 DIP40 Outline Dimensions unit : mm SSeem miiccoonndduuccttoorr 0. 120 ( 3. 048) 0. 090 ( 2. 286) 0. 048 ( 1. 219) 0. 042( 1. 067) 45 o 0.695 (17.653) 0.685 (17.399) 0.656 (16.662) 0.650 (16.510) 0. 695 ( 17. 653) 0. 685 ( 17. 399) 0. 656 ( 16. 662) 0. 650 ( 16. 510) 0.050 (1.270) 0.630 (16.002) 0.590 (14.906) SEATI NG PLANE MI N 0. 020 ( 0. 508) BASE PLANE 0. 180 ( 4. 572) 0. 165 ( 4. 191) 13. 4 0. 2 15. 24 15M AX 0 . 2 5 1. 22TY P 2. 54 1. 4 0. 1 0. 5 0. 1 0. 5MI N 4. 5 0. 3 3. 5 0. 3 50.7± 0.2 PLCC44 DIP40

Ambient temperature under bias 0 ~ +70 Storage temperature - 65 ~ + 150 Voltage on any pin to VSS - 0.5 ~ VCC + 0.5 V Maximum IOL per I/O pin Power dissipation 1.5 W Block Diagram SD60C32/P SD60C52/P Vcc Vss RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 LATCH PORT 0 DRIVERS P0.0- P0.7 P2.0- P2.7 PORT 2 DRIVERS ROM/ EPROM B REGISTER ACC STACK POINTER TMP2 TMP1 ALU PSW PSEN ALE EA RST TIMING AND CONTROL REGISTER PORT 1 LATCH PCON SCON TMOD TCON T2CON TH0 TL0 TL1 TH1 TH2 TL2 RCAP2H RCAP2L SBUF IE PORT 1 DRIVERS IP PORT AND TIMER BLOCKS INTERRUPT SERIAL PORT 3 LATCH PORT 3 DRIVERS OSCILLATOR P1.0- P1.7 XTAL1 XTAL2 PD P3.0- P3.7 PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER PROGRAM COUNTER DPTR INSTRUCTION

VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP 40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's and source and sink several LS TTL inputs. Port 0 outputs the code bytes during program verification on the 60C52 external pullups resistors are required during program verification. Port 1 : PIN 1~8 (DIP40), PIN 2~9 (PLCC44) Port 1 output buffers can drive LSI TTL inputs. Port 1 is an 8bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups SD60C32/P SD60C52/P 44PLC C 2 1 2 2 2 4 2 5 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PS EN P2.7/A15 P2.6/A14 P2.5/A13 WR/P3. 6 RD/P3. 7 XTAL2 XTAL1 VSS NC A8/P2. 0 A9/ P2. 1 A10/P2. 2 A11/P2. 3 A12/P2. 4 P1. 4 P1. 3 P1. 2 P1. 1/T2EX P1. 0/T2 NC VCC P0. 0/AD0 P0. 1/AD1 P0. 2/AD2 P0. 3/AD3 40DIP T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 INT0/P3.2 TxD/P3.1 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VS S VC C P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VP P PSEN ALE/PROG P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 4 4

Pin Description (Continued) In addition, Port 1 serves the functions of the following special features of the 60C52. Port Pin Alternate Function P1.0 T2(External Count Input to Timer / Counter 2) P1.1 T2EX(Timer / Counter 2 Capture/Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during ROM verification. Port 2 : PIN 21~28 (40DIP), PIN 24~31 (44PLCC) Port 2 is an 8-bit bi-directional I/O port with internal pullups. The port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as input. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8 bit addresses (MOVX @ Ri), port 2 emits the contents of the P2 special function register Port 3 : PIN 10~17 (DIP 40), PIN 13~19 (PLCC44) Port 3 is an 8bit bi-directional I/O port with internal pullups. The port 3 output buffers can drive LS TTL input. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below : Port PIN PIN NO. Alternate Function P3.0 RxD (Serial input port) P3.1 TxD (Serial output port) P3.2 INT0 (External interrupt 0) P3.3 INT1 (External interrupt 1) P3.4 T0 (Timer 0 external input) P3.5 T1 (Timer 1 external input) P3.6 WR (External data memory write strobe) P3.7 RD (External data memory read strobe) SD60C32/P SD60C52/P

RST: PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC. ALE: PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input PROG during EPROM programming. PSEN : PIN 29 (DIP 40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA: PIN 31 (DIP40), PIN 35 (PLCC44) External access enable. EA must be strapped to VSS in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. If EA is strapped to VCC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1: PIN 19 (DIP40), PIN 21 (PLCC44) Input to the Inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2: PIN 18 (DIP40), PIN 20 (PLCC44) Output from the inverting oscillator amplifier

0 Crystal Oscillator

NC: PIN1, 12, 23, 34 (PLCC44) Non connection pins. 30pF 30pF VS S XTAL1 XTAL2 SD60C32/P SD60C52/P

In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The control bits for the reduced power modes are in the special function register PCON. Table. Status of the external pins during Idle and power down modes. Mode Program Memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal Data Data Data Data Idle External Float Data Address Data Power Down Internal Data Data Data Data Power Down External Float Data Data Data SD60C32/P SD60C52/P

Electrical Characteristics (DC) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP. MAX UNIT VIL Input low voltage, except EA -0.5 0.2VCC- 0.1 V VIL1 Input low voltage to EA 0.2VCC- 0.3 V VIH Input high voltage, except XTAL1,RST 0.2VCC +0.9 VCC+0.5 V VIH1 Input high voltage to XTAL1, RST

0.7 VCC

VCC+0.5 V VOL Output low voltage to ports 1,2,3 IOL=1.6㎃ 0.45 V VOL1 Output low voltage to ports 0, ALE, PSEN IOL=3.2㎃ 0.45 V VOH Output high voltage to ports 1,2,3,ALE,PSEN IOH=-60㎂ IOH=-30㎂ IOH=-10㎂ VCC-0.3 VCC-0.7 VCC-1.5 V VOH1 Output high voltage (port 0 in external bus mode) IOH=-200㎂ IOH=-3.2㎃ IOH=-7.0㎃ VCC-0.3 VCC-0.7 VCC-1.5 V IIL Logical 0 input current to ports 1,2,3 VIN=0.45V -10 -50 ITL Logical 1 to 0 transition current to ports 1,2,3 VIN=2V - 265 -650 ILI Input leakage current to port 0, EA 0 < VIN < VCC 0.02 ± 10 ICC Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode 7.5 RRST Internal reset pull-down resistor 100 225 kohm C1O Pin capacitance pF SD60C32/P SD60C52/P

Electrical Characteristics (AC) 12MHz CLOCK VARIABLE CLOCK SYSBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency : Speed Versions 60C32/60C52 3.5 MHz tLHLL ALE pulse width 127 2tCLCL-40 tAVLL Address valid to ALE low tCLCL-40 tLLAX Address hold after ALE low tCLCL-30 tLLIV ALE low to valid instruction in 234 4tCLCL-100 tLLPL ALE low to PSEN low tCLCL-30 tPLPH PSEN pulse with 205 3tCLCL-45 tPLIV PSEN low to valid instruction in 145 3CLCL-105 tPXIX Input instruction hold after PSEN tPXIZ Input instruction float after PSEN tCLCL-25 tAVIV Address to valid instruction in 312 5tCLCL-105 tPLAZ PSEN low to address float Data Memory tRLRH 2, 3 RD pulse width 400 6tCLCL-100 tWLWH 2, 3 WR pulse width 400 6tCLCL-100 tRLDV 2, 3 RD low to valid data in 252 5tCLCL-165 tRHDX 2, 3 Data hold after RD tRHDZ 2, 3 Data float after RD 107 2tCLCL-70 tLLDV 2, 3 ALE low to valid data in 517 8tCLCL-150 tAVDV 2, 3 Address to valid data in 585 9tCLCL-165 tLLWL 2, 3 ALE low to RD or WR low 200 300 3tCLCL-50 3tCLCL+50 tAVWL 2, 3 Address valid to WR low or RD low 203 4tCLCL-130 tQVWX 2, 3 Data valid to WR transition tCLCL-50 tWHQX 2, 3 Data hold after WR tCLCL-50 tQVWH 2, 3 Data valid to WR High 433 7tCLCL-150 tRLAZ 2, 3 RD low to address float tWHLH 2, 3 RD or WR high to ALE high 123 tCLCL-40 tCLCL-40 External Clock tCHCX High time tCLCX Low time tCLCH Rise time tCHCL Fall time SD60C32/P SD60C52/P

Electrical Characteristics (Continued) 16MHz CLOCK VARIABLE CLOCK SYMB OL FIGUR E PARAMETER MIN MAX MIN MAX UNI T 1/tCLCL Oscillator frequency : Speed Versions 60C52/60C32 3.5 MHz tLHLL ALE pulse width 2tCLCL-40 tAVLL Address valid to ALE low tCLCL-40 tLLAX Address hold after ALE low tCLCL-30 tLLIV ALE low to valid instruction in 150 4tCLCL-100 tLLPL ALE low to PSEN low tCLCL-40 tPLPH PSEN pulse with 143 3tCLCL-45 tPLIV PSEN low to valid instruction in 3CLCL-105 tPXIX Input instruction hold after PSEN tPXIZ Input instruction float after PSEN tCLCL-25 tAVTV Address to valid instruction in 208 5tCLCL-105 tPLAZ PSEN low to address float Data Memory tRLRH 2, 3 RD pulse width 275 6tCLCL-100 tWLWH 2, 3 WR pulse width 275 6tCLCL-100 tRLDV 2, 3 RD low to valid data in 148 5tCLCL-165 tRHDX 2, 3 Data hold after RD tRHDZ 2, 3 Data float after RD 2tCLCL-70 tLLDV 2, 3 ALE low to valid data in 350 8tCLCL-150 tAVDV 2, 3 Address to valid data in 398 9tCLCL-165 tLLWL 2, 3 ALE low to RD or WR low 138 238 3tCLCL-50 3tCLCL+50 tAVWL 2, 3 Address valid to WR low or RD low 120 4tCLCL-130 tZVWX 2, 3 Data valid to WR transition tCLCL-50 tWHQX 2, 3 Data hold after WR tCLCL-50 tQVWH 2, 3 Data valid to WR High 288 7tCLCL-150 tRLAZ 2, 3 RD low to address float tWHLH 2, 3 RD or WR high to ALE high 103 tCLCL-40 tCLCL+40 External Clock tCHCX High time tCLCX Low time tCLCH Rise time tCHCL Fall time SD60C32/P SD60C52/P

F ig ure 2. E xte rna l D a ta Me mory R e a d C yc le RD A0 - A7 F ROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PC H tWHLH tLLDV tLLWL tRLRH tRHDZ tRHDX tRLDV tRLAX tL L A X tAVLL tAVWL tAVDV tLHLL ALE PSEN PORT0 PORT2 tA V L L tLLPL tLLIV tPLIV tL L A X tP LAZ tPXIX tPXIZ tAVIV A0 - A7 INSTR IN A0 - A7 A8 - A15 A0 - A15 F ig ure 1. E xte rna l P ro g ra m Me mo ry R e a d C yc le tPLPH

Timing Diagram (Continued) SD60C32/P SD60C52/P tQVWX ALE PS E N PORT0 PORT2 F i g ure 3 . E x te rn a l D a ta Me mo ry W ri te C y c le WR P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PCH tWHLH tLLWL tWLWH tWHQX tLLAX tAVLL tAVWL A0 - A7 FROM PCL INSTR IN DATA OUT A0 - A7 FROM RI OR DPL VCC - 0.5 0.45V 0.7VCC 0.2VSS - 0.1 tCLCL tCLCX tCHCX tCLCH tCHCL F ig ure 4. E xternal C loc k Drive F ig ure 5. AC T es ting Input/Output 0.2VCC +0.9 0.2VCC - 0.1 VCC - 0.5 0.45V NOTE : AC Inputs during testing are driven at V CC- 0.5 for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at V IH min for a logic '1' and V IL for a logic '0' F ig ure 6. F loat Waveform NOTE : For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begings to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA TIMING REFERENCE POINTS VLOAD VLOAD - 0.1V VLOAD+ + 0.1V VOL + 0.1V VOH - 0.1V

Timing Diagram (Continued) SD60C32/P SD60C52/P VCC ICC (NC) VCC EA CLOCK SIGNAL XTAL2 XTAL1 VSS F ig ure 9. I C C Tes t C ondition, Idle Mode All other pins are dis c onnec ted RST VCC VCC ICC (NC) VCC EA VCC CLOCK SIGNAL XTAL2 XTAL1 VSS F ig ure 8. I C C Tes t C ondition, Ac tive Mode All other pins are dis c onnec ted RST I CC ㎃ 4MHz 8MHz 12MHz 16MHz TYP IDLE MODE MAX IDLE MODE TYP ACTIVE MODE MAX ACTIVE MODE FREQ AT XTAL1 F ig ure 7. Ic c v s . F R E Q Valid only within frequency specifications of the device under test

Timing Diagram (Continued) SD60C32/P SD60C52/P VCC - 0.5 0.45V 0.7VCC 0.2V SS - 0.1 tCLCL tCLCX tCHCX tCLCH tCHCL F ig ure 10. C loc k S ig nal Waveform for I T es ts in Ac tive and Idle Modes t C L C H = tC H C L = 5㎱ VC C ICC (NC) VC C EA XTAL2 XTAL1 VS S F ig ure 11. I T es t C ondition, P ower down Mode All other pins are dis c onnec ted, V = 2V to 5. 5V RST VC C c c c c c c