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IRDCIP2001-A IRF | Alldatasheet

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IRDCiP2001-A, 500kHz, 40A, 2-phase Synchronous Buck Converter using iP2001 Overview In this document, table 1 and figure 1 are provided to enable engineers to easily evaluate the iP2001 in a 2-phase configuration that is capable of providing up to 40A in a lab environment without airflow. Figures 3, 4, 5 and 6 and the complete bill of materials in table 2 are provided as a reference design to enable engineers to very quickly and easily design a 2-phase converter. In order to optimize this design to your specific requirements refer to the data sheet for the controller listed in the bill of materials. A variety of other controllers may also be used, but the design will require layout and control circuit modifications. Demoboard Quick Start Guide Initial Settings: z The output is set to 1.7V, but can be adjusted from 1.1 to 1.85V by setting S1 according to the VID codes provided in Table 1. Droop control is set to 50mV at 40A, but can be adjusted by following the instructions in the data sheet for the PWM controller. z The switching frequency per phase is set to 500kHz with the frequency set resistor R4. This creates an effective output frequency of 1MHz. The graph in figure 1 shows the relationship between R4 and the switching frequency per phase. This frequency may be adjusted by changing R4 according to this graph; however, extreme changes from the 500kHz set point may require redesigning the control loop and adjusting the values of input and output capacitors. Also, refer to the SOA graph in the iP2001 datasheet for maximum operating current at different frequencies. Procedure for Connecting and Powering Up Demoboard: 1. Apply input voltage (5-12V) across V IN (TP18) and PGND (TP15). Note that this input source must be applied first during the power-up sequence. 2. Apply +5V logic power across +5V (TP19) and PGND (TP20). 3. Apply load across VOUT pads (TP11 & TP12) and PGND pads (TP15 & TP16) 4. Set ENABLE high. 5. Monitor switch node signals (optional) via TP7 & TP8. 6. Adjust load accordingly. iP2001 Recommended Operating Conditions (refer to the iP2001 datasheet for maximum operating conditions) Input voltage: 5 - 12V Output voltage: 1.1 - 1.85V Output current: 20A per phase, 40A total for 2-phase demo board. Switching Freq: 500kHz per phase, 1MHz effective output frequency. IRDCiP2001-A International Rectifier • 233 Kansas Street, El Segundo, CA 90245 USA REFERENCE DESIGNREFERENCE DESIGN

www.irf.com2 IRDCiP2001-A Table 1 - PWM IC Voltage Identification Codes Figure 1 - R4 vs. Frequency (per Phase) VID4 VID3 VID2 VID1 VID0 VDAC VID4 VID3 VID2 VID1 VID0 VDAC 11111 O f f 01111 1 . 4 7 5 11110 1 . 1 0 0 01110 1 . 5 0 0 11101 1 . 2 5 0 01101 1 . 5 2 5 11100 1 . 1 5 0 01100 1 . 5 5 0 11011 1 . 1 7 5 01011 1 . 5 7 5 11010 1 . 2 0 0 01010 1 . 6 0 0 11001 1 . 2 2 5 01001 1 . 6 2 5 11000 1 . 2 5 0 01000 1 . 6 5 0 10111 1 . 2 7 5 00111 1 . 6 7 5 10110 1 . 3 0 0 00110 1 . 7 0 0 10101 1 . 3 2 5 00101 1 . 7 2 5 10100 1 . 3 5 0 00100 1 . 7 5 0 10011 1 . 3 7 5 00011 1 . 7 7 5 10010 1 . 4 0 0 00010 1 . 8 0 0 10001 1 . 4 2 5 00001 1 . 8 2 5 10000 1 . 4 5 0 00000 1 . 8 5 0 100 1000 100 1000 Output Frequency (kHz) Resistance (kΩ)

www.irf.com 3 IRDCiP2001-A Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. Figure 2 - Typical Efficiency vs. Current 80% 82% 84% 86% 88% 90% 92% 0 5 10 15 20 25 30 35 40 Output Current (A) EfficiencyVIN = 12V VOUT = 1.6V TA = 25°C fSW= 1MHz fSW= 500kHz

www.irf.com4 IRDCiP2001-A Fig. 3 - Reference Design Schematic 10K +5V ENABLE 0.022uF open 51K 10uF VID41 VCC 20 VID32 PGOOD19 VID23 PWM4 18 VID14 ISEN4 17 VID05 ISEN1 16 COMP6 PWM1 15 FB7 PWM2 14 FS/DIS8 ISEN2 13 GND9 ISEN3 12 VSEN10 PWM3 11 HIP6311 +5V VDD SGND PWM2 ENABLE PRDY VIN VSW2 PGND IP2001 VDD SGND PWM2 ENABLE PRDY VIN VSW2 PGND C19 100uF 0.54uH 2K 1% +5V 10uF 10uF SWNODE2 C20 100uF TP7 SWNODE2 VDD SGND PWM1 ENABLE PRDY VIN VSW3 PGND IP2001 VDD SGND PWM1 ENABLE PRDY VIN VSW3 PGND C22 100uF 0.54uH +5V 10uF C10 10uF SWNODE3 C23 100uF TP8 SWNODE3R82K 1% VOUT Freq. Set Resistor Vin Vin R12 R11 TP15 PGND TP16 PGND TP5 PGOOD TP12 VOUT TP11 VOUTTP18 Vin TP19 +5V TP20 PGND C27 10uF +5V VID4 VID3 VID2 VID1 VID0 C28 22pF TP21 VOUT SENSE TP22 PGND SENSE VOUT SENSE R14 R16 10K R17 10K ENABLE ENABLE VOUT SENSE C33 0.01uF PGNDSENSE +5V +5V 10uF C30 10uF C11 10uF C31 10uF Rx Cx 4700pF Rx &Cx are not parts of PCB Note: Rx and Cx are add on components

www.irf.com 5 IRDCiP2001-A Fig. 4 - Component Placement Top Layer Fig. 5 - Component Placement Bottom Layer

www.irf.com6 IRDCiP2001-A Table 2 - Reference Design Bill of Materials Fig. 6 - RISEN vs Current (per Phase) Adjusting the Over-Current Limit R7 & R8 are the resistors used to adjust the over-current trip point. The trip point is a function of the controller and corresponds to 165% of the output current indicated on the x-axis of Fig. 6. For example, selecting a resistance of 1.5K at each phase will set the trip point to 165% of 15A, or 24.75A. The trip point for each phase on the demoboard is currently set to 165% of 20A, or 33A. Designator Value 1 Value 2 T ype Tolerance Packa ge Mfr. Mfr. Part No. C1 0.022uF 50V X7R 10% 0805 TD K C2012X7R1H223K C2, C6-C11, C27, C30, C31 10.0uF 16V X5R 10% 1210 TD K C3225X5R1C106K C19, C20, C22, C23 100uF 6.3V X5R 10% 2220 TD K C5750X5R0J107K C28 22.0 pF 50V COG 5% 0805 TD K C2012COG1H220J C33 0.010uF 50V X7R 10% 0805 TD K C2012X7R1H103K Cx 4700 pF 50V X7R 10% 0603 TD K C1608X7R1H472K L2 L3 0.54uH 27A Ferrite 20% SMT Panasonic ETQP6F0R6BF A R1, R2 1 K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ102 R11, R12, R14 0 1/8W Thick film <50m 0805 ROHM MCR10EZHJ000 R6, R16, R17 10 K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ103 R4 51 K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ513 R7, R8 2K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ202 Rx 51 1/10W Thick film 5% 0603 KO A RM73B1J510J S1 SPST 6 position Switch - SMT C&K Com ponents SD06H0S K ST1 - ST4 4-40 - - - - Ke ystone 8412 U1 - - PWM controller 0 - 70°C SOIC20 Intersil HIP6311CB U3, U4 - - DC-DC - 11 x 11 x 3mm IR IP2001 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 10 11 12 13 14 15 16 17 18 19 20 Output Current (A) RISEN (:)

www.irf.com 7 IRDCiP2001-A Sequencing Tip It’s important to have proper sequencing between the control IC and the iP2001 blocks. This assures the soft-start routine of the IC will properly ramp-up the output voltage during a power-up or restart from shut down event. Figure 7 shows a simple and cost effective way to synchronize the iP2001 blocks with an HIP6311 control IC in a 2 Phase configuration. Placing Schottky diodes between the iP2001’s PRDY pin and the IC’s FS/DIS pin creates an interface analogous to an AND operation. With this configuration, no single iP2001 can enable the IC independently. This configuration also resolves any differences in timing and logic thresholds between iP2001 devices. The capacitors are used to filter high frequency noise on the PRDY line. Additionally, the ENABLE pin of the iP2001 blocks can be used as the master control switch for the system. During power-up, the PRDY pin is held low until V DD reaches a typical voltage of 4.4V. Until then, the schottky diode is forward biased and clamps the FS/DIS pin well below the disable voltage of the HIP6311 IC (typically 1V). Upon reaching 4.4V, the PRDY pin transitions to a logic-level high state and releases the clamp on the FS/DIS pin. This enables the IC and allows its soft start routine to begin (see figure 8), assuming the voltage at the IC’s V CC pin is greater than its power-on reset threshold. When the ENABLE pin is held to a logic-level low state (shut down mode), the PRDY pin clamps the FS/DIS pin of the IC below the disable voltage. After the ENABLE pin transitions to a logic-level high state, the PRDY releases the clamp on the FS/DIS pin, enabling the IC and allowing its soft start routine to begin (see figure 9). During power-down, the PRDY pin transitions to a logic-level low state when the V DD reaches the under voltage lock out threshold of the iP2001 blocks. The FS/DIS pin is then clamped below the disable voltage, disabling the control IC. Fig. 7 - Sequencing Schematic 51k VSEN GND FS/DIS FB COMP PWM3 ISEN3 ISEN2 PWM2 PWM1 HIP6311 BAT54 BAT54 ENABLE PRDY1 ENABLE iP2001 iP2001 PRDY2 Master Control 0.22µF 0.22µF

www.irf.com8 IRDCiP2001-A Use of this design for any application should be fully verified by the customer. International Rectifier cannot guarantee suitability for your applications, and is not liable for any result of usage for such applications including, without limitation, personal or property damage or violation of third party intellectual property rights. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Fig. 8 - VDD Rise vs. Output Timing Fig. 9 - Enable On vs. Output Timing Ch 1: VDD Ch 3: VOUT Ch 2: PRDY Ch 1: ENABLE Ch 3: VOUT Ch 2: PRDY