IR3865MPBF IRF | Alldatasheet
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Technical content
Features
Input Voltage Range: 3V to 21V Output Voltage Range: 0.5V to 12V Continuous 10A Load Capability Constant On-Time Control Compensation Loop not Required Excellent Efficiency at Very Low Output Currents Programmable Switching Frequency and Soft Start Thermally Compensated Over Current Protection Power Good Output Precision Voltage Reference (0.5V, +/-1%) Enable Input with Voltage Monitoring Capability Pre-bias Start Up Thermal Shut Down Under/Over Voltage Fault Protection Forced Continuous Conduction Mode Option Very Small, Low Profile 4mm x 5mm QFN Package
2 8/8/2012 Rev3.1 WC WC o PCBJ o JA /32 -
PACKAGE INFORMATION
ORDERING INFORMATION
DESCRIPTION
(Voltages referenced to GND unless otherwise specified)
- Moisture Sensitivity Level ……………………..……… JEDEC Level 2 @ 260°C (Note 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied.
3 8/8/2012 Rev3.1 Simplified Block Diagram
4 8/8/2012 Rev3.1 Pin Description NAME NUMBER I/O LEVEL DESCRIPTION FCCM 1 3.3V Forced Continuous Conduction Mode (CCM). Ground this pin to enable diode emulation mode or discontinuous conduction mode (DCM). Pull this pin to 3.3V to operate in CCM under all load conditions. ISET 2 Connecting resistor to PHASE pin sets over current trip point. PGOOD 3 5V Power good open drain output – pull up with a resistor to 3.3V GND 4,17 Reference Bias return and signal reference. FB 5 3.3V Inverting input to PWM comparator, OVP / PGOOD sense. SS 6 3.3V Soft start/shutdown. This pin provides user programmable soft- start function. Connect an external capacitor from this pin to GND to set the startup time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. NC 7 - - 3VCBP 8 3.3V For internal LDO. Bypass with a 1.0µF capacitor to AGND. A resistor in series with the bypass capacitor may be required in single-ground plane designs. Refer to Layout Recommendation for details. NC 9 - - VCC 10 5V VCC input. Gate drive supply. A minimum of 1.0µF ceramic capacitor is required. PGND 11 Reference Power return. PHASE 12 VIN Phase node (or switching node) of MOSFET half bridge. VIN 13 VIN Input voltage for the system. BOOT 14 VIN +VCC Bootstrapped gate drive supply – connect a capacitor to PHASE. FF 15 VIN Input voltage feed forward – sets on-time with a resistor to VIN. EN 16 5V Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Electrical Specifications) for input voltage monitoring.
5 8/8/2012 Rev3.1 * PHASE pin must not exceed 25V. Symbol Definition Min Max Unit VIN Input Voltage 3 21* V VCC Supply Voltage 4.5 5.5 VOUT Output Voltage 0.5 12 IOUT Output Current 0 10 A Fs Switching Frequency N/A 750 kHz TJ Junction Temperature -40 125 oC PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT CONTROL LOOP Reference Accuracy, VREF VFB = 0.5V 0.495 0.5 0.505 V On-Time Accuracy RFF = 180K, TJ = 65oC 280 300 320 ns Min Off Time 500 ns Soft-Start Current EN = High 8 10 12 µA DCM Comparator Offset Measure at VPHASE -4.5 -2.5 0 mV SUPPLY CURRENT VCC Supply Current (standby) EN = Low, No Switching 23 µA VCC Supply Current (dynamic) EN = High, Fs = 300kHz 7 mA FF Shutdown Current EN = Low 2 µA FORCED CONTINUOUS CONDUCTION MODE (FCCM) FCCM Start Threshold 2 V FCCM Stop Threshold 0.6 V Electrical Specifications Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC. Recommended Operating Conditions
6 8/8/2012 Rev3.1 PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT GATE DRIVE Deadtime 1 Monitor body diode conduction on PHASE pin 5 30 ns BOOTSTRAP PFET Forward Voltage I(BOOT) = 10mA 300 mV UPPER MOSFET Static Drain-to-Source On- Resistance VCC = 5V, ID = 10A, TJ = 25oC 23 28 mΩ LOWER MOSFET Static Drain-to-Source On- Resistance VCC = 5V, ID = 10A, TJ = 25oC 10.7 13 mΩ FAULT PROTECTION ISET Pin Output Current On the basis of 25oC 17 19 21 µA ISET Pin Output Current Temperature Coefficient
1 On the basis of 25oC 4400 ppm/
Under Voltage Threshold Falling VFB & Monitor PGOOD 0.37 0.4 0.43 V Under Voltage Hysteresis 1 Rising VFB 7.5 mV Over Voltage Threshold Rising VFB & Monitor PGOOD 0.586 0.625 0.655 V Over Voltage Hysteresis 1 Falling VFB 7.5 mV VCC Turn-on Threshold -40oC to 125oC 3.9 4.2 4.5 V VCC Turn-off Threshold 3.6 3.9 4.2 V VCC Threshold Hysteresis 300 mV EN Rising Threshold -40oC to 125oC 1.1 1.25 1.45 V EN Hysteresis 400 mV EN Input Current EN = 3.3V 15 µA PGOOD Pull Down Resistance 25 50 Ω PGOOD Delay Threshold (VSS) 1 V Thermal Shutdown Threshold 1 125 140 oC Thermal Shutdown Threshold Hysteresis 1 20 oC Note 1: Guaranteed by design, not tested in production Note 2: Upgrade to industrial/MSL2 level applies from date codes 1227(marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer Market. Electrical Specifications (continued) Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz
1 SW1 SPST switch, DIP, SPST, 2 position, SMT C&K Components SD02H0SK
1 U1 IR3865 4mm X 5mm QFN IRF IR3865MTRPBF
reference (VREF) or the soft start (SS) voltage. RUN signal when all conditions are met. range and the EN pin = HIGH. (tSS) can be calculated from equation 3. voltage and SS pin is held to the FB pin voltage. Figure 20. Normal Startup voltage is within the OV and UV thresholds. discharge of a pre-biased output voltage. pulling the EN pin below its lower threshold. pulling the soft start pin below 0.3V.
will guide one through the process. resistance (ESR) of the output capacitor bank. inductance. ΔI is defined as shown in Figure 24. increases the thermal dissipation. Figure 24. Typical Input Current Waveform before the upper MOSFET can be gated on. stays ‘off’ until the next PWM falling edge. levels by pulling FCCM to HIGH. to sample the PHASE voltage.
node. The typical percentage is 25%. and mid frequency ceramic capacitors. the inductor current, as shown in Figure 25. compared to a fixed frequency control method. Time). This results in reduced recovery time. Figure 25. Charge Requirement during Load Step
voltage to turn on the upper MOSFET. based on charge balance at CCM operation. a ceramic capacitor should be chosen.
- By using the law of energy before and after
capacitance requirement for a load step down. on the characteristic of the output capacitor. ESR times the change of the output current. Figure 26. Typical Output Voltage Response
16 8/8/2012 Rev3.1 DESIGN EXAMPLE Design Criteria: Input Voltage, VIN = 7V to 16V Output Voltage, VOUT = 1.5V Switching Frequency, Fs = 300kHz Inductor Ripple Current, 2ΔI = 2A Maximum Output Current, IOUT = 10A Over Current Trip, IOC = 15A Overshoot Allowance for 5A Load Step Down, VOS = VOUT + 75mV Undershoot Allowance for 5A Load Step Up, VDROP = 75mV Find RFF : Pick a standard value 255 kΩ, 1% resistor. Find RSET : Choose an input capacitor: A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of ripple current at 300kHz. Due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both AC and DC. One 10µF capacitor is recommended. In a practical solution, one 1µF capacitor is required along with 10µF. The purpose of the 1µF capacitor is to suppress the switching noise and deliver high frequency current. Choose an output capacitor: To meet the undershoot and overshoot specification, equation 7b and 8 will be used to calculate the minimum output capacitance. As a result, 240µF will be needed for 5A load removal. To meet the stability requirement, choose an output capacitors with ESR larger than 10mΩ. Combine those two requirements, one can choose a set of output capacitors from manufactures such as SP-Cap (Specialty Polymer Capacitor) from Panasonic or POSCAP from Sanyo. A 330µF (EEFUE0E331XR) from Panasonic with 10mΩ ESR will meet both requirements. If an all ceramic output capacitor solution is desired, the external slope injection circuit composed of R6, C13, and C14 is required as explained in the Stability Consideration Section. In this design example, we can choose C14 = 1nF and C13 = 100nF. To calculate the value of R6 with PIMB104T-2R2MS-39 as our inductor: Pick a standard value for R6 = 3.65kΩ. 8.4k 91 15 10.7mR SET A A H HzAV VVV 2.3 300k216 1.5-161.5 FΔI2V VVVL sIN OUTINOUT AHzHV VVVI 2.1 300k2.261 1.5-611.52Δ Pick a 8.45kΩ, 1% standard resistor. Find a resistive voltage divider for VOUT = 1.5V: Choose the soft start capacitor: Once the soft start time has chosen, such as 1000us to reach to the reference voltage, a 22nF for CSS is used to meet 1000µs. Choose an inductor to meet the design specification: V0.5 V RR RV OUT FB R2 = 1.40kΩ, R1 = 2.80 kΩ, both 1% standard resistors. Choose an inductor with the lowest DCR and AC power loss as possible to increase the overall system efficiency. For instance, choose a PIMB104T-2R2MS-39 manufactured by CYNTEC. The inductance of this part is 2.2µH and has 6.0mΩ DCR. Ripple current needs to be recalculated using the chosen inductor. k nFm H CDCR LR 67.3 1000.6 2.2 k 502 300k201 V AA A V VA 1.310 2/1.2 1161 1.510I IN_RMS
17 8/8/2012 Rev3.1 STABILITY CONSIDERATIONS Constant-on-time control is a fast , ripple based control scheme. Unstable operation can occur if certain conditions are not met. The system instability is usually caused by:
- Switching noise coupled to FB input: This causes the PWM comparator to trigger prematurely after the 400ns minimum on-time for lower MOSFET. It will result in double or multiple pulses every switching cycle instead of the expected single pulse. Double pulsing can causes higher output voltage ripple, but in most application it will not affect operation. This can usually be prevented by careful layout of the ground plane and the FB sensing trace.
- Steady state ripple on FB pin being too small: The PWM comparator in IR3865 requires minimum 7mVp-p ripple voltage to operate stably. Not enough ripple will result in similar double pulsing issue described above. Solving this may require using output capacitors with higher ESR.
- ESR loop instability: The stability criteria of constant on-time is: ESR*Cout>Ton/2. If ESR is too small that this criteria is violated then sub-harmonic oscillation will occur. This is similar to the instability problem of peak-current-mode control with D>0.5. Increasing ESR is the most effective way to stabilize the system, but the tradeoff is the larger output voltage ripple.
- System with all ceramic output capacitors: For applications with all ceramic output capacitors, the ESR is usually too small to meet the stability criteria. In these applications, external slope compensation is necessary to make the loop stable. The ramp injection circuit, composed of R6, C13, and C14, shown in Figure 7 is required. The inductor current ripple sensed by R6 and C13 is AC coupled to the FB pin through C14. C14 is usually chosen between 1 to 10nF, and C13 between 10 to 100nF. R6 should then be chosen such that L/DCR = C13*R6.
- System with electrolytic output capacitors: The electrolytic capacitors usually have higher ESL than POSCAPs and ceramic capacitors. The effect of high ESL is undesirable spike on the FB node causing false trigger of a new switching cycle. The ESR of electrolytic capacitors also comes in a wide range, such that in some cases we need to filter out the spikes caused by its high ESL while providing injected ripple to compensate for low ESR. The circuit composed of R13, C24, and C14 shown in Figure 7 acts as a filter and a ramp generator. As an example, if two Nichicon PW-series, 1000uF, 16V through hole electrolytic capacitor are used for 12Vin, 5Vout, and 300kHz switching; the suggested compensation values are: R13 = 20Ω, C24 = 1uF, and C14 = 1000pF. Equations for determining these values have not been established. If electrolytic or other high ESL capacitors are required, IR's application team will gladly assist you to determine an optimal compensation scheme.
19 8/8/2012 Rev3.1 PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper, or
20 8/8/2012 Rev3.1 Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
21 8/8/2012 Rev3.1 Stencil Design The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste.
22 8/8/2012 Rev3.1 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial Market (Note 2) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 03/12