SCY99080CDWR2G

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Document overview

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Technical content

Features

• High−Frequency Operation from 30 kHz up to 500 kHz
• Selectable Minimum Switching Frequency
• Adjustable Deadtime from 100 ns to 2 /C0109s
• 100 ms Delayed Startup for PFC Stage Stabilization
• Adjustable Preheating Timer via External Capacitor
• Startup Sequence via Adjustable Soft−Start
• 600 V High−V oltage Floating Drivers
• Synchronized Low−Current Outputs for Full Bridge

Applications

• Adjustable Maximum On−Time Clamp for Synchronization Outputs
• Brown−Out Protection for Easier PFC Association
• Delayed Open−Loop Protection
• Latched Input for Severe Fault Conditions, e.g. Over Current
• Secondary Latched Input for Over Temperature Protection
• Auto−Recovery Enable Input
• VCC Operation up to 20 V
• Low Startup Current of 300 /C0109A
• 0.5 A / 0.25 A Peak Current Sink / Source Drive Capability, Respectively
• Internal Temperature Shutdown
• SO19W package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications
• Flat Panel Display Power Converters
• LLC Converters Control for LCD/Plasma TVs
• HCFL / CCFL Backlight Inverters PIN CONNECTIONS MARKING DIAGRAMS DDA002C = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package SOIC−19, LESS PIN 17 D SUFFIX CASE 752AA DDA002C AWLYYWWG See detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet.

ORDERING INFORMATION

*For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Boot Hgd HB Vcc Lgd Gnd Hgs Lgs EN2 BO CIG Dgs SS R_Fmin R_Fmax FB OTP_latch DT EN1 DDA002C DDA002C

Figure 1. Typical Application Example

http://onsemi.com Pin Function Description Pin No. Pin Name Function Pin Description 1 BO Brown−out Detects low input voltage conditions and stops the controller. An internal current source sets the hysteresis.

2 CIG Warm−up time A capacitor connected to ground sets the pre−heat time for ballast applica-

tions.

3 DGS Synchronous output clamp A resistor connected between this pin and ground adjusts the maximum on−

time available on Lgs and Hgs pins.

4 SS Soft−start Monitors the soft−start capacitor voltage to recognize end of the soft−start

period, discharges the soft−start capacitor during any IC restart. 5 R_Fmin Minimum frequency resistor Connecting a resistor between this pin and ground, sets the minimum oscil- lator frequency reached for VFB ≥ 5.1 V

6 R_Fmax Maximum frequency

A resistor connected between this pin and ground sets the maximum fre- quency excursion reached for V FB ≤ 1.2 V

7 FB Optocoupler connection An optocoupler connected (by collector) between this pin and ground (by

emitter) changes the converter operating frequency. The switching frequency increases when optocoupler pulls the FB pin down to ground. 8 OTP_latch OTP latch input If the voltage on this pin decreases below 1.5 V, the circuit latches off. This pin sources 170 /C0109A current so an NTC resistor can be connected directly to this pin.

9 DT Dead time A resistor connected between this pin and ground sets the deadtime

between drivers.

10 EN1 Enable input 1 When the voltage level on this pin exceeds a reference level for more than

50 /C0109s, all pulses are stopped and the circuit permanently latches off.

11 EN2 Enable input 2 When the voltage level on this pin exceeds a reference voltage, the circuit

stops pulsing. The IC auto−restarts via full startup sequence (PFC delay, pre−heat, soft−start) when EN2 is released. 12 Lgs Lower gate signal Duplicates the lower gate signal for synchronization purposes. On time is limited based on the Rdgs resistor value. 13 Hgs Upper gate signal Duplicates the upper gate signal for synchronization purposes. On time is limited based on the Rdgs resistor value.

14 GND Ground The controller ground

15 Lgd Low−side driver Drives the low−side half−bridge MOSFET

16 Vcc Controller Supply Energizing the controller. This pin accepts voltage up to 20 Vdc

17 HB Half−Bridge Connects to the half−bridge output

18 Hgd High−side driver Drives the high−side half−bridge MOSFET

19 Boot High side driver supply line This pin supplies the internal high−side driver

Figure 2. Internal Architecture

http://onsemi.com Maximum Ratings Symbol Rating Value Unit VHB Continuous voltage on the bridge pin, pin 17 −1 to 600 V Qmax Maximum injected charge into the HB pin (Note 3) 11 nC VBOOT−VHB Floating supply voltage, pin 17 and 19 −0.3 to 20 V VHgd High side output voltage, pin 18 VHB−0.3 to VBOOT+0.3 V VLgd Low side output voltage, pin 15 −0.3 to Vcc+0.3 V dVHB/dt Maximum slew rate on the HB pin, pin 17 ±50 V/ns Vcc Power Supply voltage, pin 16 −0.3 to 20 V pin voltage, all pins (except pin 3, 6, 15, 16, 17, 18, and 19) −0.3 to 10 V VDgs Synchronous clamp pin voltage, pin 3 −0.3 to 5 V VR_Fmax Maximum frequency adjust pin voltage, pin 6 −0.3 to 5 V R/C0113J−A Thermal Resistance Junction−to−Ambient, (Soldered on traces with total area of 50 mm2, 1 oz copper) Thermal Resistance Junction−to−Ambient, (Soldered on recommended layout, 1 oz copper) 137 117 °C/W Storage Temperature Range −60 to +150 °C TJmax Maximum Junction Temperature +150 °C ESD Capability, HBM model (Except all HV pins i.e., HB, Hgd and Boot) (Note 1) 2 kV ESD Capability, Machine Model 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC (22A114C − Human Body Model and 22A115A Machine Model) 2. This device contains latch −up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. The maximum injected charge corresponds to the injected current integrated over time into the half −bridge pin. Please refer to Figure 60 and related notes.

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Electrical Characteristics

(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 15 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCCON Turn−on threshold level, Vcc going up 16 11 12 13 V VCC(min) Minimum operating voltage after turn−on (Note 4) 16 8.5 9.5 10.5 V VbootON Startup voltage on the floating section 19,17 8 9 10 V Vboot(min) Cutoff voltage on the floating section 19,17 7.4 8.4 9.4 V Istartup Startup current, Vcc < VCCON 16 − − 300 /C0109A ICC1 Internal IC consumption, no output load on pin 18/17 – 15/14, Fsw = 300 kHz (Note 5) 16 − 5 − mA ICC2 Internal IC consumption, 1 nF output load on pin 18/17 – 15/14, Fsw = 300 kHz (Note 5) 16 − 14 − mA ICC3 Internal IC consumption in fault mode (All drivers disabled, VCC > VCC(min)) 16 − 2.5 − mA VOLTAGE CONTROL OSCILLATOR (VCO) Fsw min Minimum switching frequency, R_Fmin = 41 kΩ on pin 5, Vpin 7 > 5.5 V, DT = 300 ns (Notes 19 and 21) 5 58 60 62 kHz Fsw max Maximum switching frequency, R_Fmax = 2.5 kΩ on pin 6, Vpin 7 < 1.2 V, DT = 100 ns, Rt = 41 kΩ (Notes 20 and 21) 6 450 500 550 kHz SVCO Maximum VCO conversion slope, /C0068f / ΔVfb (Note 6) − − 120 − kHz / V FBSW min Feedback pin swing above which /C0068f = 0, Fsw = Fmin, DC = 50% 7 − 5.1 − V FBSW max Feedback pin swing below which /C0068f = 0, Fsw = Fmax, DC = 50% (Note 6) 7 − 1.2 − V DCsl, DCsh Operating duty−cycle symetry, 5.5 V> Vpin 7 > 0.5 V (Note 7) 18,17; 15,14 48 50 52 % Min Ton Minimum On time 18,17; 15,14 − 880 − ns VFB_DC_0 Skip comparator threshold on the feedback pin (Note 8) 7 − 1.2 − V VFB_DC_0_ Hyste Hysteresis on the skip comparator 7 − 50 − mV VREF Reference voltage for Fmin current generation 5 − 2 − V FEEDBACK SECTION Rfb Internal pull−up resistor 7 − 10 − kΩ Vfb_O Open−loop voltage on the feedback pin, no optocoupler connection 7 − 7.3 − V 4. V CC(min) = VCCreset 5. Outputs Lgs and Hgs (pin 9/10) are unloaded. 6. Guaranteed by design. 7. DCsh = (DChs/(DChs + DCls)) * 100%, DCsl = (DCls/(DChs + DCls)) * 100% 8. The VFB_DC_0 is the FB voltage below which are all outputs disabled. The FB voltage has to increases to VFB_DC_0 + VFB_DC_0_Hyste to re−enable all outputs of the controller. 9. Low impedance source and sink R DS(on) are designed to respectively deliver 0.5 A and −1 A at Tj = 100°C. 10.Pins 17, 18 and 19 are on the same potencial during IHV_LEAK measurements 11. On−time on synchro outputs wont be longer than on−time on power outputs. 12.The soft start pin is pulled down by an internal switch until the CIG timer ending voltage is reached 13.FB timer is disabled until the soft−start ending voltage is reached 14. EN1 input is blanked until the preheat period (CIG) ends. The OTP input is blanked during full startup sequence made of: PFC_del + CIG_t + SS_t 15.The FB timeout circuit starts to operate at the end of PFC_del + CIG_t + SS_t period. 16.An NTC resistor of 8.8 k/C0087 @ T A = 110°C is connected to ground. 17.The EN1 and EN2 input voltages have to go 50 mV below VEN1, VEN2 to release these inputs. 18.The OTP input voltage has to go 50 mV above OTPref_V to release this input. 19.The R_Fmin pin do not accept any bypass capacitor 20.Maximum acceptable capacitance connected to the pin is 100 pF 21.Measured for V CC = 10.5 V

http://onsemi.com (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 15 V unless otherwise noted) Symbol UnitMaxTypMinPinRating LOW IMPEDANCE DRIVE OUTPUTS (HGD, LGD) Tr – Hgd Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 18, 17 − 80 − ns Tf – Hgd Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 18, 17 − 40 − ns ROH – Hgd Source resistance – (Note 9) 18, 17 − 30 − Ω ROL − Hgd Sink resistance – (Note 9) 18, 17 − 15 25 Ω Tr – Lgd Output voltage rise−time @ CL 1 nF, 10−90% of output signal 15, 14 − 80 − ns Tf – Lgd Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 15, 14 − 40 − ns ROH – Lgd Source resistance (Note 9) 15, 14 − 30 − Ω ROL − Lgd Sink resistance (Note 9) 15, 14 − 15 25 Ω T_dead−min Minimum dead−time, RDT = 2.7 kΩ from pin 9 to GND (Notes 20 and 21) 9 − 100 − ns T_dead−nom Nominal dead−time with RDT = 10 kΩ from pin 9 to GND (Notes 20 and 21) 9 245 300 355 ns T_dead−max Maximum dead−time with RDT = 82 kΩ from pin 9 to GND (Notes 20 and 21) 9 − 2 − /C0109s IHV_LEAK Leakage current on high voltage pins to GND (Note 10) 17, 18, 19 − − 5 /C0109A SYNCHRONIZATION DRIVE OUTPUTS (LGS AND HGS) ROH – S Source resistance 12, 13, 14 − 60 − Ω ROL – S Sink resistance 12, 13, 14 − 60 − Ω DGS (SYNCHRONOUS OUTPUT CLAMP) Tdgs Clamped on−time duration, Rdgs = 48 kΩ, Fsw < 24 kHz, DT = 300 ns (Notes 11, 20 and 21) 3, 12, 13 17.1 17.9 18.7 /C0109s Iduty_min Minimum on−time duration, Rdgs = 12 kΩ, Fsw = Fmin (Notes 11, 20 and 21) 3, 12, 13 4.45 4.66 4.87 /C0109s Iduty_nom Minimum on−time duration, Rdgs = 26 kΩ, Fsw < 24 kHz (Notes 11, 20 and 21) 3, 12, 13 9.65 10 10.35 /C0109s TIMERS CIG_I CIG timer charging current 2 − 10 − /C0109A CIG_E CIG timer ending voltage (Note 12) 2 − 5 − V CIG_t Typical CIG duration for a 0.22 /C0109F capacitor on CIG pin 2 − 110 − ms SS_E Soft−start ending voltage (Note 13) 4 − 1.9 − V 4. V CC(min) = VCCreset 5. Outputs Lgs and Hgs (pin 9/10) are unloaded. 6. Guaranteed by design. 7. DCsh = (DChs/(DChs + DCls)) * 100%, DCsl = (DCls/(DChs + DCls)) * 100% 8. The VFB_DC_0 is the FB voltage below which are all outputs disabled. The FB voltage has to increases to VFB_DC_0 + VFB_DC_0_Hyste to re−enable all outputs of the controller. 9. Low impedance source and sink R DS(on) are designed to respectively deliver 0.5 A and −1 A at Tj = 100°C. 10.Pins 17, 18 and 19 are on the same potencial during IHV_LEAK measurements 11. On−time on synchro outputs wont be longer than on−time on power outputs. 12.The soft start pin is pulled down by an internal switch until the CIG timer ending voltage is reached 13.FB timer is disabled until the soft−start ending voltage is reached 14. EN1 input is blanked until the preheat period (CIG) ends. The OTP input is blanked during full startup sequence made of: PFC_del + CIG_t + SS_t 15.The FB timeout circuit starts to operate at the end of PFC_del + CIG_t + SS_t period. 16.An NTC resistor of 8.8 k/C0087 @ T A = 110°C is connected to ground. 17.The EN1 and EN2 input voltages have to go 50 mV below VEN1, VEN2 to release these inputs. 18.The OTP input voltage has to go 50 mV above OTPref_V to release this input. 19.The R_Fmin pin do not accept any bypass capacitor 20.Maximum acceptable capacitance connected to the pin is 100 pF 21.Measured for V CC = 10.5 V

http://onsemi.com (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 15 V unless otherwise noted) Symbol UnitMaxTypMinPinRating TIMERS PFC_del Internal delay timer after brown−out confirmation, EN2 released or Vcc restart − − 100 − ms PROTECTIONS VEN1 Reference voltage for the enable 1 input (latch), (Note 14), (Note 17) 10 0.95 1 1.05 V VEN2 Reference voltage for the enable 2 input (Note 17) 11 0.95 1 1.05 V HysteENX Hysteresis for EN1, EN2 inputs 10, 11 − 50 − mV VdelEN1 Delay before latch confirmation on EN1 input (Note 14) 10 − 50 − /C0109s VdelEN2 Delay between the EN2 activation and driver disable 11 − 80 120 ns VBO Brown−Out level 1 0.95 1 1.05 V IBO Hysteresis current, Vpin 1 = 0.9 V, 0°C < TJ < 125°C Hysteresis current, Vpin 1 = 0.9 V, −40°C < TJ < 125°C 1 17.85 16.31 24.15 24.15 /C0109A IBObias Brown−Out input bias current 1 − 0.02 − /C0109A OTPref_I OTP Reference current (Note 16), 0°C < TJ < 125°C OTP Reference current (Note 16), −40°C < TJ < 125°C 8 155.7 143.7 173 173 190.3 190.3 /C0109A OTPref_V OTP reference voltage (Note 14), (Note 18) 8 1.425 1.5 1.575 V OTP_hyste OTP comparator hysteresis 8 − 50 − mV OTPnoise Noise filter on the OTP output (Note 14) 8 − 50 − /C0109s FB_Fault Above this level, the FB fault timer is activated (Note 15) 7 − 6 − V FB_timer FB timeout duration (Note 15) 7 − 50 − ms TSD Temperature shutdown threshold − 140 − − °C TSDhyste Temperature shutdown hysteresis − − 30 − °C 4. V CC(min) = VCCreset 5. Outputs Lgs and Hgs (pin 9/10) are unloaded. 6. Guaranteed by design. 7. DCsh = (DChs/(DChs + DCls)) * 100%, DCsl = (DCls/(DChs + DCls)) * 100% 8. The VFB_DC_0 is the FB voltage below which are all outputs disabled. The FB voltage has to increases to VFB_DC_0 + VFB_DC_0_Hyste to re−enable all outputs of the controller. 9. Low impedance source and sink R DS(on) are designed to respectively deliver 0.5 A and −1 A at Tj = 100°C. 10.Pins 17, 18 and 19 are on the same potencial during IHV_LEAK measurements 11. On−time on synchro outputs wont be longer than on−time on power outputs. 12.The soft start pin is pulled down by an internal switch until the CIG timer ending voltage is reached 13.FB timer is disabled until the soft−start ending voltage is reached 14. EN1 input is blanked until the preheat period (CIG) ends. The OTP input is blanked during full startup sequence made of: PFC_del + CIG_t + SS_t 15.The FB timeout circuit starts to operate at the end of PFC_del + CIG_t + SS_t period. 16.An NTC resistor of 8.8 k/C0087 @ T A = 110°C is connected to ground. 17.The EN1 and EN2 input voltages have to go 50 mV below VEN1, VEN2 to release these inputs. 18.The OTP input voltage has to go 50 mV above OTPref_V to release this input. 19.The R_Fmin pin do not accept any bypass capacitor 20.Maximum acceptable capacitance connected to the pin is 100 pF 21.Measured for V CC = 10.5 V

Figure 33. VdelEN2 vs. Temperature Figure 34. T_dead −nom vs. Temperature

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Application Information

The DDA002C includes all necessary features that help building a rugged and safe switch −mode power converter for an LCD TV backlighting or LLC resonant SMPS applications. The bullets below detail the benefits brought by implementing the DDA002C controller:

• High−voltage drivers: thanks to the ON Semiconductor proprietary technology, the DDA002C controller can directly drive the upper−side transistor of a half−bridge configuration biased up to 600 V .
• Wide frequency range: a high−speed V oltage Control Oscillator allows operating frequency excursion from 30 kHz up to 500 kHz on the Lgd and Hgd outputs, with a 50% duty−cycle. These two outputs are available as synchronization signals via two ground−referenced low−current outputs (Lgs and Hgs).
• Internal skip comparator: all drivers are disabled when feedback voltage goes below 1.2 V level. The skip comparator includes 50 mV hysteresis.
• PFC−delay: the controller includes a fixed 100 ms delay to allow bulk voltage stabilization after the PFC stage has been started. The PFC timer is reset at power−on, when a brown−out condition occurs and when the EN2 input is released. The controller is ready (VREF is OK) but no pulses are delivered by the outputs during this delay period.
• Pre−heat period: once the PFC delay has elapsed, the circuit starts to pulse with start up frequency to pre−heat the lamps (in HCFL ballast applications). This period is also called CIG period.
• Adjustable soft−start: at the end of the pre−heat period, the soft−start sequence takes place. The controller starts pulsing with Fstart and reduces its frequency down to Fmin. The feedback loop is supposed to take over during this period. The Fstart frequency is dictated by the parallel combination of Rfstart and Rfmin resistors, the soft−start length is given by a capacitor connected to the ground. The soft−start sequence is activated after every controller restart.
• Open−Loop detection: the controller starts to monitor the feedback voltage at the end of the soft−start period. If it remains stuck above 6 V (it means the feedback loop is not closed) the internal timer starts the countdown. The controller latches off if this situation lasts longer than 50 ms.
• Adjustable dead−time: using a single resistor wired to the ground, the user has ability to include needed dead−time that helps to fight cross−conduction between the upper and lower bridge transistors.
• Adjustable minimum and maximum frequency excursion: in resonant applications, it is important to stay away from the resonating peak to keep the converter operating in the right region (ZVS). It is also needed, for ballast applications, to keep the F min accuracy high since it dictates maximum lamp power. Thanks to a single external resistor, the designer can program its lowest frequency point, obtained due to a lack of feedback voltage (during the startup sequence or in short−circuit conditions). Internally trimmed capacitor offers a ±3.3 % precision on the selection of the minimum switching frequency. The adjustable upper frequency limit is less precise (±10%).
• Low startup current: the device requires only 300 /C0109A start−up current. This feature decreases the power dissipation and/or shortening of the start−up time when the controller is powered from an auxiliary winding and starts using a startup resistor connected directly to the bulk voltage.
• Brown−Out detection: the IC incorporates a brown out comparator, which prevents the outputs from switching in case the high−voltage rail is not within the right boundaries. The turn on and off levels of the bulk voltage can be adjusted independently thanks to the internal current sink IBO.
• Enable1 input: when a voltage above 1 V is applied to this pin, for a time longer than 50 /C0109s, the controller permanently latches−off. The latch resets when Vcc is cycled below Vcc(min) or when there is a brown−out event detected. The EN1 input is blanked during the PFC delay and preheat periods.
• Enable2 input: when a voltage higher than 1 V is applied to this pin, the controller immediately stops all pulses. The controller restores operation (including PFC delay, preheat and soft−start) when enable 2 input voltage decreases down again.
• OTP latch input: by connecting an NTC resistor between ground and the OTP_latch input, the designer has ability to latch−off the controller in an over−temperature condition. The OTP input is blanked during the PFC delay, preheat and soft−start periods.
• Synchronization outputs: two low−current ground referenced outputs (Lgs and Hgs) are available to implement a full−bridge converter in higher power configurations. A resistor connected to the Dgs pin sets the maximum allowable on−time that is delivered by these two outputs when used for synchronization purpose.

shows simplified architecture of the VCO. Figure 35. Simplified VCO Architecture The VCO conversion characteristic is shown in Figure 36.

http://onsemi.com PACKAGE DIMENSIONS SOIC20 WB LESS PIN 17 (SO−19) CASE 752AA−01 ISSUE O b19X H10X L A SEATING PLANE /C0113 h X 45/C0095 E D M0.25 MB M0.25 SA SBC e C B A DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 b 0.35 0.49 A3 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 /C0113 0 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. /C0095/C0095 DETAIL A DETAIL A SCALE 2X 11.00 19X 0.52 19X 1.30 1.27 DIMENSIONS: MILLIMETERS PITCH 10 11 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 DDA002C/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative