SCX6206 NSC | Alldatasheet
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Zu] National any 05 | $2 g SCX microCMOS Gate Array Family Application Guide 2 TABLE OF CONTENTS (oe) 2.1 microCMOS Process and Circuit Personalization... 3 SCX6212 (1.2k) 0.00. & 3 SCX6218 (1.8k) 2... cree S Z SCX6232 (9.2K) oe. cccseeeserseeeeeseeeee 6 2 SCX6244 (4.4K) ooo eee cece eee B °o © BA Hardware Macros 2... eee eerie 6 a 5.2. Peripheral Macros 00.20. cece eceeeeeeeeeeeeeees B C) 7.0 Packaging 00... 00cccccevceeeceeeeeeeeeeeeee 10
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11.0 Alternative Interfaces re 22
TRUSTATES is a rogstred trademark of Natonal Semiconductor Co, R23 WSc_. ©1985 Natonal Semiconductor Corporation TL/U/5725, | RD-830M75/Printed in U. S.A. ~ I
1.0 General Description "= On-chip self-test capability (6.0K only) National Semiconductor's CMOS gate array Family utilizes a " 100% auto-place-and-route at 90% utilization dual layer metal technology (microCMOS) to achieve oper- ® Design automation system supported on mainframe and ating speeds similar to Schottky-TTL with the inherent lower workstations Leonel seal standard ows integrated creuits 2.0.1 Enhanced Product Features -Series Family is available in 2-micron drawn ; ; . geometry with a 1.4 micron effective channel length. The The SCX6200-series gate array family is available in seven range of complexity is currently from 600 to 6000 gates. The pow increments from ono Snact of sexes am gates are arranged in cells. Each cell has the equivalent of 6 o id 7 ‘ 6260. Today it has been enhanced and expanded to include three 2-input NAND or NOR gates. All outputs have the abil- the 6244, 6232, 6218 and 6206, Those cnteneod devicos ity to drive 10 LSTTL loads. All inputs have high noise immu- ntain soveral new features as follows nity and are protected from static discharge. contain otlows: National Semiconductor supports gate aay designs win a *ienible VO Structure - The /0 butler has been en variety of user/vendor interfaces. This ranges from produc- > Pie functions | 8: ing arrays from the user's schematic to accepting data- — Low-drive inputs compatible with TTL, CMOS or bases for mask generation. A large dedicated staff of gate Schmitt Trigger array professionals is available to help the user determine —High-drive (Clock Driver) inputs compatible with TTL, the most efficient and cost effective way to interface on any CMOS or Schmitt Trigger given design. — Output compatible with TTL and CMOS and configura- The design automation tools include workstation or text file ble as TRI-STATE®, non TRI-STATE or Open Drain entry (for schematic capture), loge and timing veriers to — Outputs selectable for 1, 2 or 4 mA drive substantiate the actual design, fault grading analysis to — Bidi gauge testability and a large selection of macros (hardware Bidirectional inputs/outputs and software) to speed and simplity the design. — Oscillator macros to drive 1, 2 or 4 mA. — Separate power supply traces for output drivers im-
2.0 Product Features Prove noise immunity
- Latch-up proof, state-of-the-art 2-micron (drawn) dual- The input capacitance loading of the output drivers has also metal silicon-gate microCMOS technology been reduced to enhance the overall circuit performance. ™ Ultra-high performance—1 ns typical gate delays * Selectable Output Drive Capability - The enhanced I/O , structure now makes it possible to offer a variety of output ™ Available from 600 gates to 6000 gates drives for any given I/O location. Through implementation "= CMOS power dissipation of 1/0 macro options, users can select their output drives ™ All inputs and I/Os protected from over-voltage and latch- in 1, 2 or 4 mA for each output buffer. up * Parallel 1/O Buffers for High Drives - By means of spe- "Full design automation support cial 1/0 macros, output drive current in excess of 4 mA — Schematic capture can be achieved by paralleling 1/O butters without losing , ; the input functions. For example, to achieve 24 mA, six aad IF ith timin " Logic simulator with timing information 4 mA I/O buffers need to be paralleled up; through use of — Fault grading the special macros, one pin is needed to implement the ™ Multiple power rail pin connections output which can be bidirectional while 5 pins can still be = Multiple packaging options in ceramic, plastic, leaded and used as inputs. leadless * Dedicated Multiplexed D-Flip/Flops - Incorporated into ™ Pin counts to 172 the internal array core is a number of dedicated multi- «Miltary performance plexed D-flip/flops. These flip/flops have been designed w Alternate od to achieve significant system speed improvement over a fernately sourcs : logically eqivalent macro function while minimizing silicon = Complete hardware/software macrocell libraries space to implement. They are ideal for scan path design techniques as well as registers and counters. ‘Array Equivalent vo Test Vss Name 2-Input Gates (Note 1 Cells Pin Pins ‘SCX6206 poo Tw Ts | ct ] SCx6212 [tao a ae so da SCX6218 1806 {so Ts a dT ee tT SCx6225 [aa30 nes es | CT Cd SCX6232 [steer toe td SOx6244 4380 [sto 3 ae qaer_scxe260(Note2) [600 Ts |= | ~Sta | Cd] Sd Note 1 Input and 1/0 calls are not considered part of the internal cell Count. Note 2: Advanced Architecture with additional 2500 gates for on-chip self-test capability. I
FIGURE 1. Cell lation. After the basic transistors are formed (in their respec- transition. wafers up to the metal layers are common and fixed. Circuit increases power consumption. layers and the VIAs. In this way, the user's design (or circuit nodal capacitance and the frequency of circuit operation. in each cell (see Figure 1). The power and ground lines , . This cell is repeated in all four directions to form columns y. customer's options are designed and the last three patterns output buffers driving large capacitive loads. tion process completed for the metal layers. ticular design.
2.2 GATE ARRAY BASIC CELL an Cr ont]
2.3 POWER DISSIPATION Ht ttt + +I
2.4 ABSOLUTE MAXIMUM RATINGS 2.5 RECOMMENDED OPERATING CONDITIONS. Exceeding the following absolute maximum ratings may re- Min Max Units sult in permanent damage to the device. Vop. Supply Voltage 2 6 v _ V,. Vo, Input or Output Voltage Vsg_~Vpp VV Supply Voltage OSV to7V lo, High or Low Level Output Input or Output Voltage =0.5V to Vpp +0.5V Current 0 +25 mA ‘Storage Temperature —65°C to 150°C Ipp. Vpp or Vgg CurrentperPad 0 +50 mA Power Dissipation (Package Dependent) 1w Ta, Ambient Operating Lead Temp. (Soldering, 10 seconds) 300°C Temperature ~40 +85 °C
2.6 DC ELECTRICAL CHARACTERISTICS
Vop = §V + 10%, min/max limits apply over recommended operating temperature range unless otherwise specified. Symbol| Parameter [Conditions| Min_—(|_“Max_| Unite Vin High Level Input Voltage Vo = 0.5Vo0rVop = 1Vilo=1HA | 07Vp | | Vv Vit Low Level Input Voltage Vo=0.5VorVpp~1Vilo=1HA | _—*|0.3Vpp|_V Vou __ | High Level Output Voltage Vi = Vop or GND, Ig = 1A Von -0.05/ |v Vor __| Low Level Output Voltage Vi = Vpp or GND, lo = 1 wA ee lon __| High Level Output Current Vi= VoporGND,Vo=Voo-osv[ -4 | | ma low Low Level Output Current Vi = Vpp or GND, Vo = 0.4V [ 4 | [ma VinTTL | Min. High Level TTL /P Voltage Vo = 0.8V or Vpp — 1V, lo = 1 pA Vv (for TTL Input Option) ViLTTL | Max. Low Level TTL I/P Voltage Vo = 0.5V or Vpp — 1V,1o = 1 HA v (for TTL Input Option) I Input Current (Without Pull-Up Resistor) | Vi = Vpp or GND [|] tt | pa ‘oc Supply Current Vi_= Vp or GND, Ta = 25°C [100 [pa 2.7 AC ELECTRICAL CHARACTERISTICS Vpp = 5V, Ta = 25°C, 2p process. Symbol [Parameter [Min [Max «| Unita tPLH Output Buffer 14 3.6 ns teu (Non-Inverting, non-TRI-STATE) 1.2 42 ns t, = y= 5ns, OV-5V C= 15 pF tpLH Input Buffer 0.75 ns teat (TTL Type, Non-Inverting) 1.10 ns att, = t) = 5ns, 0V-3V CL = 1pF tPLH Input Buffer 1.75 ns tPaL (CMOS Type, inverting) 1.40 ns att; = y = 5s, OV-5V CL = 1pF Pun Output TRISTATE 1.9 60 ns tHe (Non-Inverting) 25 68 ns tpze att, = t= 5ns 28 78 ns tpzH OV-5V 1.9 6.0 ns teiz Cy = 50pF 72 83 ns tenz Ru = 1ko 7.0 82 ns Delays Measured at 50% ns Point Between Start and Target Voltage teu Internal 2-Input NAND. 0.4 1.55 ns tPHL att, = t¢ = 51ns, OV-5V 0.8 2.30 ns tPHL Load Equivalent to Fan-Out of 0.20 0.75 ns tPLH 3 and 100 mils of Interconnect 0.15 0.55 ns ‘As Above with CL = 0 pF - |
3.0 Topology and Routing
The specific topology and routing resource distribution have er pins (for simultaneous switching outputs) and routing re- been tailored for each family member. Architectural consid- ‘sources consistant with automatic place and route software. erations include the ratio of inputs and |/Os to total cell Internal cell utilizations of greater than 85% can be expected. count, power consumption and package inductance to pow- Individual topologies and a family summary follow.
6206 Die Structure 6212 Die Structure
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6218 Die Structure 6225 Die Structure
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6232 Die Structure 6244 Die Structure
Hikes" a voo 25 \\/o's 's— vssf} u\\ [7] voo wor} tl [7] voo ri +17 COLUMNS ————+! [] vss yss CI \\+—————20 COLUMNS [] vss ie Ya sla 3/4] ai =e 22 ss FQ 10-F/F FAs 10-F/F | a4 | 27 3) 29 25 | 2la 26 Vos) |e o's os | 8]5| Vos he t Fs 1D F/F
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4.0 On-Chip Test Circuitry
Each of the SCX gate arrays is provided with dedicated on- On-Chip Test Circuitry Truth Table chip test circuitry. This circuitry forces all the outputs to spe- [tc [oT | TsTc | Output | cific states to facilitate output parametric testing. These X Active TRISTATE parametric tests include leakage and current sourcing/sink- Non-Active | Non-Active 1 ing measurements on all output pins. ‘Active Non-Active 0 The on-chip test circuitry is enabled by a dedicated test , mode control (TMC) pin. This pin is set aside for testing and Definition of Test Input States cannot be used for any other purpose on the 6212 and Non-Inverting Inverting 6225. However, for the enhanced devices (6244, 6232, Macros Macros 6218 and 6206), the extra TMC pin can be avoided by Non-Active 0 means of an internal TMC decoding circuit of the user's Active 1 design. In addition, an optional internal contro! signal de- rived from the TMC pin is now available. This can be used, for example, as a set or reset contro! signal to the internal 5.0 Macros logic. Three types of macros are available for designers to use: The self-test capability has been further expanded and en- hardware macros, software macros (National Semiconduc- hanced on the 6k-gate 6260. It has an additional 2,500 tor standard library), and user generated software macros. gates dedicated to provide an on-chip maintenance system that includes chip self-test, system interconnect-test, logic 5.1 HARDWARE MACROS analyzer, and system check-sum modes. This self-test fea- The SCX family of gate arrays offers an extensive library of ture on the 6260 is unique from the rest of the SCX family as hardware macros (Table |). Each macro has been fully char- well as in the industry. A low at this input will activate the on- acterized and functionally proven. The designer can select chip test circuitry. When the on-chip test circuitry is activat- those macros that most efficiently implement the design. ed, the states of all outputs are determined by two other The electrical performance of the macros is characterized inputs; these are TRI-STATE test control (TSTC) and data at two sets of conditions: best and worst-case. Under each test (DT). The TSTC and DT can share input pins with the set of conditions, the output loading is specified at 0 pF and user's design. They are only active when the TMC is en- 1.0 pF. The 1.0 pF load is equivalent to a fan-out of 3 and abled. The TSTC input has precedence over the DT input. includes 100 mils length of metal interconnect. A single in- The TMC input is active for the following discussion. Pit Joad is equivalent to 0.13 pF and Is defined as a load ft. When the TSTC input is active, all the output buffers are put actor oft into a high impedance mode. When TSTC is not active, the National Semiconductor has very tight wafer fabrication states of the output buffers are determined by the DT input. guidelines. However, process parameters still do vary from These two inputs can be assigned to any of the input pins. wafer-to-wafer, lot-to-lot. The electrical specifications of the macros take into account such variations. — I
TABLE |. Table of Macros [Function | wacroname] [Function [Macro Name] [eurers SSC~CSY 6-Input Enable Decode if
TABLE I. Table of Macros (Continued) [___Funetion "[Macroname | © [Function | Macroname | ARITHMETIC FUNCTIONS INPUTS AND OUTPUTS 4-Bit Parity Checker C030 (T6) Inputs Only (36) See I/O Macro Table 1-Bit Full Adder 032 (T7) Outputs Only (9) See 1/0 Macro Table 1-Bit ALU with 7 Functions C040 (H2) Bidirectional (72) See I/O Macro Table 2-Bit Magnitude Comparator Oscillator Macros (3) See I/O Macro Table Notes on Macro Name Note 1: Cell Count S = 1 cell (3 gates) Q = 4cells (12 gates) D = 2 cells (6 gates) F = 5 cells (15 gates) T = 3celis (9 gates) H = 6 cells (18 gates) Note 2: The 'C000" designator is a common reference used between National Semiconductor and its alternate source for the purpose of consistency with users. TABLE Il, I/O Macro Table VO Macro | moutmace | Output Macro |__lnput Brive" OutputDrive [Each Capable of jacro Type utput | x] 7x] 16x] smal 2matamal v [> | N Input Only TTL x |x] x x x x (36 Macros) CMOS (INV) x| x1 x x x x CMOS (NINV) x} x] x x x x Schmitt x |x] x x x x Output Only NINV x x x (9 Macros) INV x x x Open Drain x x x Bidirectional TIL NINV x x x x x x x (72 Macros) CMOS (INV) NINV x x x x x x x CMOS (NINV) NINV x x x x x x x Schmitt NINV x x x x x x x TTL INV x x x x x x x CMOS (INV) INV x x x x x x x CMOS (NINV) INV x x x x x x x Schmitt INV x x x x x x Xx Oscitator(@Macros)[ | TT Px Px Px V = Pulp; D = Pull-Down; N = Neither PulLUp nor Pull-Down
5.2 PERIPHERAL MACROS sign, modify it to meet some special consideration, rename
Interfacing to the SCX gate arrays is done through the pe- it, then reference it as a special or new software macro. This ripheral buffers. There are two types of peripheral cells; in- Procedure is coordinated with National's Technology Cen- put only and bi-directional |/O cells (Table II). The peripheral ters. macros are not included in the count of internally available National Semiconductor adds popular software macros to cells, the existing library as required to meet user needs. The buffers are located around the periphery of the die and A representative list is shown in Table Ill. The cell count is a the exact configuration is dependent on the particular family ‘will not exceed’ number, unused portions of cells are avail- member under consideration. Reference section 3 for spe- able for use in unrelated portions of the design. if ti in L . Cific locations of input and 1/0 celts. 6.1 SOFTWARE MACROS (USER GENERATED)
6.0 Software Macros The user always has the option of generating higher order
dit software macros. This is true regardless of where the user In addition to the pre-designed hardware macros, National decides to interface with the design automation system Semiconductor offers a library of software macros. These : software macros emulate the functions of the popular 7400 At the workstation level, the user simply creates the desired and 4000 logic families, From the designer's vantage point, function from existing hardware macros, stores the function these software macros are utiized as though they were under a unique identifier name, then recalls it as a block of hardware macros. The actual implementation of these high- logic as required. er order functions is handled by the design automation tools In the text file mode of schematic capture the user defines in a process that virtually expands the software macro into the higher order function in terms of the basic hardware its hardware macro primitives. macros. These higher order (custom) functions are then Since the software macros reside in the design automation called’ in the same manner as any other software macro. system, a designer may copy a software macro into his de- - \\
TABLE III. Software Macros Cell Cell Cell Cell Device Count Device Count Device Count Device Count 7400 1.3 7495 13.0 74191 22.0 74399 12.0 7402 1.3 7496 18.0 74192 23.0 74445 76 7403 1.3 74100 45 74193 22.0 74490 13.0 7404 15 74101 6.0 74194 20.0 74521 12.0 7405 15 74102 5.0 74195 12.0 74533 12.0 7406 2.0 74103 8.0 74196 23.0 74534 21.0 7407 6.0 74106 8.0 74197 41.0 74540 45 7408 2.0 74107 8.0 74198 21.0 74541 65 7409 2.0 74108 85 74199 26.0 74543 27.0 7410 1.5 74109 8.0 74237 12.0 74544 27.0 7411 2.0 74112 8.0 74240 45 74550 57.0 7412 15 74113 8.0 74241 65 74551 57.0 7414 6.0 74114 85 74242 45 74563 12.5 7415 15 T4116 17.0 74243 45 74564 21.0 7416 2.0 74125 3.0 74244 8.7 74568 28.0 7417 4.0 74126 3.0 74245 65 74569 26.0 7420 1.3 74128 3.0 74251 13.0 74573 13.0 7421 13 74132 1.3 74253 65 74574 21.0 7422 1.3 74133 3.0 74256 19.0 74589 48.0 7425 3.3 74134 3.5 74257 6.0 74590 57.0 7426 1.33 74135 8.0 74258 3.0 74592 58.0 7427 1.5 74136 4.0 74259 14.0 74593 66.0 7428 3.3 74137 12.0 74260 4.0 74595 37.0 7430 2.0 74138 6.7 74261 29.0 74597 51.0 7432 1.3 74139 6.0 74266 4.0 74640 85 7433 3.3 74145 7.6 74273 25.0 74643 12.5 7437 3.3 74147 15.0 74279 27 74646 12.5 7438 33 74148 9.3 74280 7.0 74648 8.5 7440 2.0 74149 15.5 74283 22.0 74670° 60.0 7442 76 74150 15.0 74289 84.0 74688 11.0 7443 76 74151 65 74290 17.0 744002 1.3 7444 76 74152 9.0 74292 138.0 744017 21.0 7445 76 74153 65 74293 17.0 744020 44.0 7446 17.0 74154 13.0 74294 74.0 744024 22.0 7447 17.0 74155 6.0 74295 14.0 744040 38.0 7448 17.0 74156 6.0 74298 13.0 7451 2.0 74157 5.0 74299 43.0 7458 2.0 74158 5.0 74323 48.0 7464 3.3 74159 13.0 74350 16.0 7465 3.3 74160 22.0 74354 30.0 7470 6.0 74161 19.5 74356 30.0 7471 67 74162 22.0 74363 13.0 7472 68 74163 20.0 74364 21.0 7473 8.0 74164 26.0 74365 5.0 7474 6.0 74165 23.0 74366 35 7475 45 74168 25.0 74367 5.0 7476 8.0 74168 22.0 74368 3.5 7477 45 74169 20.0 74373 13.0 7478 8.0 74170 40.0 74374 21.0 7483 12.0 74172 57.0 74375 4.0 7485 12.0 74173 15.0 74377 26.0 7486 4.0 74174 19.0 74378 20.0 7489 84.0 74175 19.0 74379 14.0 7490 13.0 74180 9.8 74386 4.0 7491 17.0 74181 41.7 74390 26.0 7492 13.3 74182 15.0 74393 24.0 7493 13.0 74189 84.0 74395 14.0 7494 13.0 74190 23.0 74398 12.0 i
7.0 Packaging
The SCX family of microCMOS gate arrays is offered in a The primary reason for surface mounting is to allow leads to. very wide variety of packages. The user is provided with be placed closer together than the 0.100 inch standard for many choices in terms of both package type and lead count. DIPs with through-hole mounting. Through-hole mounting The package types offered include ceramic pin grid arrays on smaller than 0.100 inch space is difficult to achieve in (PGA), leaded ceramic chip carriers (LDCC), leadless ce- Production and is generally avoided. The move to 0.050 ramic chip carriers (LCC), plastic leaded chip carriers (PCC), inch lead spacing offered with the current generation of sur- ceramic DIPs, and plastic DIPs. face mounted components, along with a switch from a dual- The availability of such a large variety of packages gives the in-line format to a quad format, has achieved a threefold user flexibility in making the following choices: increase in component mounting density. A need to achieve —Ceramic versus plastic sreater density is a major driving force in today's market- —Through-hole mount versus surface mount Learning how to surface mount components to printed cir- The specific packages offered are listed in Table IVa. cuit boards requires the user to implement an assembly Surface mounting of multi-lead components is rapidly gain- process not typically associated with through-hole inser- ing popularity. To provide the user flexibility, National Semi- tion/wave soldering assembly methods. conductor Offers its CMs gale anys several surface Surface mounting involves three basic process steps: mount package options: leaded and leadless ceramic chip ae a cartier and the plastic leaded chip carrier. 1) Application of solder or solder paste to the printed circuit Surface mounting refers to component attachment, where- A - by the component leads or pads rest on the surface of the 2) Positioning ‘of the component onto the printed circuit PCB instead of the traditional approach of inserting the 3) Reflowing of the solder or solder paste. leads into through-holes which go through the board. With Table IVb lists the manufacturers currently offering sockets surface mounting there are solder pads on the PCB which for each of the advanced package options listed in this data align with the leads or pads on the component. The result- sheet. A matrix of which manufacturers to contact for each ing solder joint forms both the mechanical and electrical socket option is provided. The listing is divided into test/ connections. burn-in and production categories. There may be some indi- vidual sockets that will cover both requirements. TABLE IVa. Gate Array Package Options Package Type _[ Pins | 6206] 6212] 6218] 6225] 6292] 6244] 6260 Plastic DIP, N 20 | Xx 2a} x | x {| x] x 4o; x | x]x}xi}x |x Ceramic DIP, D 20 | x (Side Braze) 2} x |x {x |x 4a| x | x{xi}xi]x]x Plastic Leaded 28) x | x |x | x Chip Carrie, PCC | 44] x | x | xX | x | x | x 68 x |x}x |x] x 84 x | x |x] x 124 x |x] x Ceramic Leaded 124 x x x x Chip Carrier, LOCC Ceramic Leadless | 28 | x | x | x | x ChipCarrier,LCC | 44; x | x | x | x | x 68 x | x] x |x] x 84 x | x] x] x 124 x |x] xx Ceramic Pin 68 x} x} xix] x Grid Array,PGA | 84 x | x | x | x 124 x |x ]x |x 172 x l
" " 7 New Albany, IN c/o Napenthe Dist.
8.0 Propagation Delays
For example: a 2-input NAND (S1) drives six loads. What is er has functionally verified his design in the logic simulator. tpiy for 1 pF = 2.40 ns (3 loads) ance at other than specified values. 4.05 ns = 0.75 ns + 6 (0.55 ns) library book for complete specifications. FIGURE 3. CMOS Propagation Delays
Temperature = —40°C Temperature = 100°C Supply Voltage = 5.5V | Supply Voltage = 4.5V Extreme Process Extreme Process Parameters Parameters TABLE V. 2u Symbol | Fanon | ur Beseteve | Worst case _] Croan (oF) bol Y [tut tra | tru tog | OND Sst 1 0.095 0.19 0.75 0.95 0 0.39 0.67 2.40 4.05 1 S2 0.09 0.27 0.95 1.65 oO 0.37 0.92 2.65 5.75 1 $4 0.16 0.15 Vw 0.95 oO 0.62 0.51 4.15 2.85 1 ss 3-NOR 0.23 0.16 1.65 1.13 O 0.85 0.52 61 3.05 1 s7 Clock Buffer 2 0.07 0.13 0.45, 0.55 oO 0.24 0.33 1.45 4.65 1 SB Inverter 1 0.095 0.16 0.6 0.75 ty) 0.36 0.52 2.35 26 1 si 2-XOR 0.14 0.16 2.6 25 ° 0.54 0.53 5.8 5.65 1 D9 D Flip-Flop CLK toQ 0.71 0.59 5.12 4.38 0 1.02 0.94 7.0 6.25 1 CLK to Qg 0.35 0.54 2.38 3.3 i} 0.64 0.98 5.37 6.62 1 so TRI-STATE Inverter 1 0.18 0.18 1.2 1.35 0 0.60 0.70 4.25 4.15 1 $10 TRI-STATE Buffer 0.30 0.27 1.9 1.8 O 0.53 0.53 3.4 3.4 1 Iq Inverting input Buffer CMOS 0.23 0.19 0.85 0.70 0 0.45 0.39 2.30 1.80 1 ly Input Buffer TTL 0.33 0.39 2.0 2.45 0 0.60 0.78 3.70 4.80 1 le Short Circuit Input CMOS 0.04 0.04 0.07 0.07 i} 0.15 0.15 0.50 0.50 1 10; TTL 0.33 0.39 2.0 2.45 0 0.60 0.78 37 48 1 7 0.62 0.78 44 5.75 15 1.15 1.55 7.0 9.75 50 102 Input (Inverting) CMOS 0.23 0.19 0.85 0.70 i} 0.45 0.39 2.30 1.80 1 7 0.62 0.78 4.40 5.75 15 1.15 1.55 7.0 9.75 50 103 Short Circuit Input CMOS 0.04 0.04 0.07 0.07 oO 0.15 0.15 0.50 0.50 1 0.62 0.78 4.40 5.75 15 4.15 1.55 7.0 9.75 50 104 7 0.65 0.63 4.75 45 15 117 1.45 8.25 8.25 50 ‘Note: All delays in nanoseconds. t= ty = 25s for 2-micron LF = Load Factor. Temperature Derate = 0.3%/"C from 100°C. tT
9.0 Design Automation System
Figure 6 shows the standard gate array development flow are completed at his/her site. are the user's site, user's responsibilities, National Semicon- ‘these files is in the ‘hardware design language’. Of task responsibility and location. Semiconductor offers technical assistance if necessary. FIGURE 6. Standard Gate Array Development Process and Responsibilities
National Semiconductor Technology Center Mask generation, wafer fab, assembly and test are complet- Training includes actual interaction with the design automa- ed by National Semiconductor. tion system and, depending on the level of user experience, Prototype evaluation and acceptance are the responsibility requires from three to five days to complete. All of the con- of the user. siderations necessary for the successful completion of the National Semiconductor has a large staff of applications design are covered during the training. Topics such as, and consulting engineers available to assist users at any hardware (.e., speed, power, pinouts) and software consid- point in the array development process. erations (i.¢., logic simulation, fault grading, critical path analysis) are tailored to meet the user's needs. Training is 9.5 WORKSTATION SUPPORT provided at the closest technology center. Contact the local The above capabilities, specifically the front-end design sales representative for the location nearest you. functions (such as schematic capture, netlist entry, logic Functional verification of the logic is accomplished by sub- simulation and timing estimation), are also available on the mitting the netlist and pattern files to the logic simulator. Valid, Daisy, and Mentor workstations. Such capabilities will The simulator will predict the output results of the specified be extended to other popular CAE design stations such as logic for the applied vectors. The designer can then deter- CAE Systems and the IBM PC. mine if the specified logic meets the design objectives. Sim- To allow workstation users to properly interface with the ulation under actual ‘loaded’ conditions occurs after func- SCX-series gate arrays, National provides a workstation tional verification and fault grading. Functional verification is software design kit. It consists of a set of floppy discs con- the responsibility of the user. taining the logic symbols of all the macros, a netlist extrac- Fault grading is a measure of the ability of the supplied vec- tor and model timing data for pre-layout simulation and tim- tors to detect induced logic errors (.e., on-chip shorts). The ing estimation. This design kit is developed, distributed, vectors supplied eventually become the functional portion maintained and updated solely by National. of the final production test tape. It is important that the fault Some of the more time-consuming tasks such as fault grad- grading figure of merit reach 85%. Fault grading is the re- ing, auto-place-and-route and post-layout logic verification sponsibility of the user. are performed on the mainframe computer. A typical design Performance estimation is the prediction that the logic simu- flow between the workstation and mainframe is illustrated in lator makes by considering actual macro loading and a pro- Figure 7. Generally, there are three design paths as follows: jection of the interconnect lengths. This projection is based * Path A—schematic capture on user's workstation; then on an algorithm which relates fan-out to probable trace transfer of unsimulated design files (netlist and test vec- length. Performance estimation is the responsibility of the tors) to NSC's mainframe for logic simulation, fault grading user. and place-and-route. Place and route are the actual implementation of the user's * Path B—schematic capture, logic simulation and timing design file. Two pieces of design automation software are verification on user's workstation; then transfer of simulat- used to complete the routing. ed design files to NSC’s mainframe for resimulation (one Automatic place and route software completes the majority pass), fault grading and place-and-route. of interconnects and in most cases completes the entire * Path C—schematic capture, logic simulation, timing verifi- array. cation and place-and-route on user's workstation; then Interactive graphics software is used to complete any un- transfer of database file to NSC’s mainframe for resimula- routed interconnects. tion (one pass), fault grading and PG tape generation. Place and route are the responsibility of National Semicon- (This is a future capability.) ductor. Performance verification is the rerunning of the ‘perform- ance estimation’ software with the actual cell placements and associated trace lengths. Performance verification is the responsibility of the user. i
FIGURE 7. National’s Workstation-to-Mainframe Semi-Custom Design Flow
‘, The macro call syntax for the following circuit fragment is as
10.0 Design Example ified
The two most popular ways of interfacing to the design au- -~-— tomation system are 1) alphanumeric text entry and 2) work- r | station output. A different example will be given for each. In 0g —_P-—. 008 either case the design automation system requires two ba- | I sics files to operate. ' Network (File): The network file is the ‘wiring diagram’ of cua I cana the design. It represents how the array is to be ‘wired’. More —-~—d > ° rl specifically, it is the manner in which the hardware macros - are interconnected. The syntax of the network file is speci- ! ! fied by a hardware design language (HDL). cuoce —— oo **- oo —_. ax Pattern (File): The pattern file represents the stimuli or se- L 2. eer Fd | quence of signals used to exercise the design specified by quuisres-—14 the network file. The pattern file ultimately becomes the functional portion of the final test tape used to screen pro- SSUBU $8 duction devices. The logic simulator operates on the network and pattern {* SPECIFIES A PARTICULAR files and predicts the logic output as a function of the pat- MACRO TYPE *) tern file. (+ SPECIFIES A HARDWARE MACRO +) Data Entry SSANO {+ CIRCUIT NAME ASSOCIATED WITH [venoms [ree ABOVE MACRO) CONTAINS CIRCUT CONTAINS INPUT (+ DELIMITER +) DESCRIPTION IN HDL ‘STIMULI FOR IRCUTT SIMULATION CLKB CLK CLRB OGB/ CLOCK CLKB CLEAR OG [Inputs To MACRO ELEMENTS D) k= (+ OUTPUTS FROM MACRO ELEMENTS +) Tu/s725-18 paEvicTe oureut If the designer were using the alphanumeric text mode of quuysres-13 data entry, each unique macro and macro type would be The simulator has two modes of operation. The first mode is Specified in the above manner until the entire network had used to verify the logical integrity of the design. The second been specified. ; mode considers capacitive circuit loading and anticipated In the workstation mode of schematic capture the designer wire lengths. The result of the second mode is the perform- would call and name each desired macro, then graphically ance that can be expected after the circuit has been placed interconnect each macro in the required fashion. The work- and routed. station would then ‘compile’ the schematic into the network The basic form of a network file is as follows: file, $NETWORK (*BEGIN A NETWORK FILE*) $ INP INA INB BTC. (*LIST ALL INPUT NAMES*) $ OUT OUTA OUTB ETC. (*LIST ALL OUTPUT NAMES*) MACRO CALLS (*SPECIFY MACROS AND INTERCONNECTS*) 33° COMMENTS (*MAKE COMMENTS*) — I
10.1 TEXT MODE
FIGURE 8. The Design of a Four-Bit Latch with TRI-STATE Output is Presented. marae
SS RIOR ik kk kkk tO kk tok $NETWORK SINPUT INA INB INC ID1 ID2 OD1 OD2 CLOCK CLEAR $OUTPUT OUTA OUTB OUTC OUTD $$% 0M74173 MACRO SSUBU SB $$ANO CLKB CLK CLAB OGB / CLOCK CLKB CLEAR OG SSUBU S4 SSAN1 1G IGB OG / ID1 ID2 IG CONO OD1 oOD2 SSUBU S15 SSAN2 DAB DA / INA IG IGB QA SSUBU S15 SSAN3 DBB DB / INB IG IGB QB S$SUBU S15 SSAN4 DCB DC / INC IG IGB Qc $SUBU / S15 S$ANS DDB DD / IND IG IGB QD $SUBU T1 $$AN6 QA QAB / CON1 DA CLK CLRB $SUBU Tt SSAN7 QB QBB / CON1 DB CLK CLRB SSUBU T1 SSANB Qc QcB / CON1 DC CLK CLRB $SUBU T1 SSANO QD QDB / CON1 DD CLK CLRB $SUBU S9 SSAN10 OUTA OUTB / QAB OGB QBB OGB S$SUBU S9 SSAN11 OUTG OUTD / QCB OGB QDB OGB SS kk i tk tO tO IO ko RO kk ~--LTTULLL eee
= {> — Fg il = > Ec : ° L : ina
SINPUT CLEAR CLOCK ID1 ID2 INA iNB INC IND OD1 OD2 $OUTPUT OUTA OUTB OUTC OUTD $SUBU S4 $SXCMP 1 xSIG29_XSIG27 XSIG18 / XSIG27 GND ID1 ID2 OD1 OD2 Se SSUBU T1 SSXCMP 10 XSIG33_ XSIG41_/ VCC XSIG34 XSIG20 XSIG21 SS $SUBU S9 S$XCMP 11 OUTA OUTB / XSIG41 XSIG22 XSIG4O xsIG22 $SUBU S9 S$$XCMP 12 OUTC OUTD / XSIG39 XSIG22 XSIG38 XSIG22 $SUBU SB $$XCMP 2 xSIG22 XSIG20 XSIG21 XSIGI9 / XSIG18 XSIG19 CLEAR CLOCK $$e SSUBU S15 SSXCMP 3 OPEN-1 XSIG37 / XSIG30 XSIG29 IND XSIG27 SSUBU S15 SSXCMP 4 OPEN-2 XSIG36 / XSIG31 XSIG29 INC XSIG27 $Se $SUBU S15 S$XCMP 5 OPEN-3 XSIG35 / XSIG32 XSIG29 INB XSIG27 SSUBU S15 SSXCMP 6 OPEN-4 XSIG34 / XSIG33 XSIG29 INA XxSIG27 $$e SSUBU T1 $$XCMP 7 XSIG3O XSIG3B / VCC XSIG37 XSIG20 XxSsIG21 $SUBU T1 S$XCMP 8B XSIG31_XSIG39_/ VCC XSIG36 XSIG20 XSIG21 $SUBU T1 $SXCMP 9 XSIG32_XSIG40 / VCC XSIG35 XSIG20 XxSIG21 $o* ~-- ee ee Le
10.3 PATTERN FILE
SCYCLE = 1000 1000 REPRESENTS THE NUMBER OF INTERVALS PER CYCLE 1 INTERVAL = 100 PICOSECONDS SS IOI III tok $$* PATTERN FILE CODING FOLLOWS: SB ee TORII IIIT $$% PATTERN FILE FOR TESTING DM74173 $$* TEST SHOULD SWEEP 16 CYCLES CLEAR HI 1-2 INA HI 1357 11-12 INB HI 1357 11-12 INC HI 1357 11-12 IND HI 135 7 11-12 > INPUT SIGNALS USED TO SIMULATE THE NETWORK 1D1 HI 135-6 D2 LO 137-8 D1 HI 5-6 13-14 OD2 HI 7-8 15-16 CLOCK LO RPT (01: 1-16) SINGLE CLOCK REPEATING 01 THROUGH CYCLE 16 CIRCUIT INPUTS HI AT SPECIFIED CYCLE. LOW AT ALL OTHER CYCLES CIRCUIT INPUT LO AT SPECIFIED CYCLE. HI AT ALL OTHER CYCLES TL/U/S725~19
10.4 SIMULATOR OUTPUT
INPUTS AS SPECIFIED AS SPECIFIED BY PATTERN FILE BY PATTERN FILE _ — wit 1 oOo CC 0000 NNNN DD DD L L UUUU ABCD 12 12 EO mT AC ABCD RK 1 1111 10 00 410 XXXX "157 1111 10 00 1 0 0000 2 0000 01 00 11 0000 3 1111 10 00 00 0000 4 0000 01 00 01 0000 5 1111 11 10 00 0000 "434.1111 11 10 0 0 2ZZZ 6 0000 11 10 014 2Z2Z 7 1111 00 01 00 222Z 8 0000 00 01 01 2Z2ZZ 9 0000 01 00 0 0 2Z2ZZ 140 0000 01 00 0 0 1414 10 0000 01 00 0 1 qt 1 1111 01 00 00 4111 12 1111 01 00 01 4111 13 0000 01 10 0 0 1111 129 0000 01 10 0 0 22ZZZ 14 0000 01 10 01 2ZZZ 15 0000 01 01 00 2Z2Z 16 0000 01 01 01 2ZZZ | secuenma. NUMBERS REPRESENT TIME CYCLES ZZ2ZZ = HIGH IMPEDANCE STATE 1111 = HIGH STATE 0000 = LOW STATE **Intermittent numbers represent settling time in hundred-picoseconds that ‘occur between time cycles. -- Lt ee ee L e
11.0 Alternative Interfaces * Simulation support
Semiconductor technology center. National Semiconduc- tions Group at (408) 721-4614. Figure 6. sic array develop! low specified in (408) 721-4614, TWX: (910) 339-9240
- User generates logic simulator compatible files from his National Semiconductor Corp.
tion in his/her simulator, then interfaces to design auto- National Semiconductor S.A.
12.0 Training and Technical Telex: 841-527649
worldwide technology centers. At the new Santa Clara train- .
- oe ee ee Ee
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