SCV59748 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Features
- Output Current in Excess of 1.5 A
- VIN Range: 0.8 V to 5.5 V
- VBIAS Range: 2.7 V to 5.5 V
- Output V oltage Range: 0.8 V to 3.6 V (Adjustable)
- Dropout V oltage: 60 mV at 1.5 A
- Open Drain Power Good Output
- Fast Transient Response
- Stable with Any Type of Output Capacitor ≥ 2.2 /C0109F
- Current Limit and Thermal Shutdown Protection
- SCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
- These are Pb−Free Devices
Applications
- Automotive, Consumer and Industrial Equipment Point of Load Regulation
- FPGA, DSP and Logic Power Supplies
- Switching Power Supply Post Regulation MARKING DIAGRAM www.onsemi.com xxxxx = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071= Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS See detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
/C0071
Figure 1. Typical Application Schematic,
Figure 2. Simplified Schematic Block Diagram − Table 1. PIN FUNCTION DESCRIPTION IN 1, 2 Unregulated input to the device. mode. This pin must not be left floating. BIAS 4 Bias input voltage for error amplifier, reference, and internal control circuits. if output monitoring is not necessary. voltage. This pin must not be left floating. to ground to assure stability. PAD/TAB − Should be soldered to the ground plane for increased thermal performance.
Table 2. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
- This device series incorporates ESD protection and is tested by the following methods:
Table 3. THERMAL CHARACTERISTICS
- Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
- Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The foll owing
− DFN10: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. Vias are 0.3 mm diameter, plated. − DFN10: Each of top and bottom copper layers are assumed to have thermal conductivity representing 20% copper coverage.
- The junction −to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
- The junction −to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7) the Recommended Operating Ranges limits may affect device reliability.
- Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Table 5. ELECTRICAL CHARACTERISTICS (At VEN = 1.1 V, VIN =V OUT + 0.3 V, CBIAS = 0.1 /C0109F, CIN =C OUT =1 0 /C0109F, performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Adjustable devices tested at V
REF; external resistor tolerance is not taken into account.
- Dropout is defined as the voltage from the input to V OUT when VOUT is 3% below nominal.
10.3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
- Due to a minimum Bias Pin operating voltage of 2.7 V, VBIAS dropout voltage is not applicable for VOUT ≤ 1.4 V.
Adjustable devices tested at VOUT = 1.5 V.
controll circuitry is powered from the VBIAS voltage. advantageous in applications with large capacitive loads. hysteresis and deglitch filter. V out monitoring and sequencing of other devices. SCV59748 Adjustable V oltage version is available. Typical application schematic is shown in Figure 15. Figure 15. Typical Application Schematics − percents specified in the Electrical Characteristics table. Electrical Characteristics table. joined together and VOUT starts to decrease. having not negligible impedance. switched to serve as a Noise filtering capacitor. frequently used voltages can be found in the Table 6. protects the device against Current Overload or Short. should be limited to +125°C.
Table 6. RESISTOR VALUES FOR PROGRAMMING
0.8 Short Open
Table 7. ORDERING INFORMATION Specifications Brochure, BRD8011/D.
www.onsemi.com PACKAGE DIMENSIONS DFNW10, 3x3, 0.5P CASE 507AE ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURE TO AID IN FILLET FORMA- TION ON THE LEADS DURING MOUNTING. ÉÉÉ ÉÉÉ ÉÉÉ A B E D BOTTOM VIEW b e 10X 0.10 B 0.05 AC C NOTE 3 PIN ONE REFERENCE TOP VIEW A 0.05 C 0.05 C C SEATING PLANESIDE VIEW L10X 1 5 610 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. RECOMMENDED DETAIL B DETAIL A NOTE 4 SOLDERING FOOTPRINT* 10X 0.58 3.30 1.75 0.30 0.50 PITCH 3.30 10X DIMENSIONS: MILLIMETERS 2.50 0.50 PITCH PACKAGE OUTLINE b24X DIM MIN NOM MILLIMETERS A 0.80 0.90 b 0.20 0.25 D D2 2.30 2.40 E E2 1.55 1.65 e 0.50 BSC L 0.30 0.40 A3 0.20 REF 2.90 3.00 K MAX 2.90 3.00 1.00 0.05 0.30 2.50 1.75 0.50 3.10 3.10 ALTERNATE CONSTRUCTION DETAIL A SECTION C−C PLATED SURFACES L DETAIL B PLATING EXPOSED ALTERNATE CONSTRUCTION COPPER L e 0.28 C C
0.25 REF
0.28 REF
0.05 REF
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