Microcontroller

SCN8039H

NXP Semiconductors

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Manufacturer: NXP Semiconductors

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MAB8050H PHILIPS | Alldatasheet

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@ 8 bit CPU, ROM, RAM and 1/0 © 8-bit counter/timer © On-chip oscillator and clock driver circuits © Single-level interrupts: external and counter/timer © 17 internal registers: accumulator, 16 addressable registers © Over 90 instructions: 70% single byte ® All instructions 1 or 2 cycles © Easily expandable memory and 27 1/O lines @ TTL compatible inputs and outputs ® Single 5 V supply ®@ Standard and extended temperature ranges (see Table 5): MAB8OXX: 0 to +70 9C MAF80XX: —40 to +85 OC MAFB80AXX: —40 to +410 0C icati @ Peripheral interfaces and controllers © Modems and data enciphering @ Test and measuring instruments @ Environmental control systems ®@ Sequencers © Audio/video systems PACKAGE OUTLINES All versions: with type no, suffix P (see Table 5): 40-lead DIL; plastic (SOT-129)}, MAB8035/8048/8039/8049H/HLWP : 44-lead PLCC; plastic leaded chip-carrier (SOT187AA).

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Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL wo) U by vc xtaut 2] [38] 1 xtavz [3] [33] P27 reset [a] [a7] P26 eG [ sbiies3:g23 int P24 a P= APPL PAA ELE EA EN fo [ey [33] p16 = int [7] O [33] p24 sen [9 | prs EA [a] Piz —_ | Massossy “ WR [tol assoson (20 Px4 AO [a re ave [Ti] Massosonc [30] ea PSEN [hol [38] pis MaBgoaon = ovo [2] [2] ex.2 wa [nl [35] Pia os: [a] [2] x1 ne. [i] MABBosoN/30NC [34] v« oe2 [ra] P10 ALE MABBO5OH/40HL [33] pas oes [15] [26] Yoo 080 [ra] [32) P12 oes [ie] [25] PROG 081 [is] fai) er ves [i] [24] p23 ve2 [ie] [30] P10 oes [3] [23] p22 oa [I [23] Yoo a7 P21 os [el ay eee FARE SAAT SE Tea gee a8 28 88 8 [8 szorane Fig. 2a Pinning diagram; for pin Fig. 2b Pinning diagram for MAB80XXHWP; designation see next page. for pin designation see next page. Product type numbering European and USA cross-reference scheme Type numbering reference Type numbering equivalent used mainly in Europe reference used mainly in USA MAB8039HLP/HLWP SCN8039HCB N40/A44 MAF8039HLP/HLWP. SCN8039HAB N40/A44 MAB8049HP/HWP SCN8049HCB N40/A44 MAF 8049HP/HWP. SCN8049HAB N40/A44 MAB8040HLP/HLWP. SCN8040HCB N40/A44 MAF8050HP/HWP. SCN8050HCB N40/A44 August 1990 2-31

12-19 | DBO-DB7 Data Bus: true bidirectional I/O port which can be written or read using the RD and WR strobes. This port can also be used as an 8-bit latch. It contains the 8 low order address bits during an external memory access and receives the addressed instruction under control of PSEN. This multiplexed address/data port also contains the address and data during external RAM accesses. 27-34 P1.0-P1.7 Port 1: 8-bit quasi-bidirectional I/O port (note 1). 21-24 P2,0-P2.7 Port 2: 8-bit quasi-bidirectional I/O port (note 1). 35-38 P2.0--P2.3 contains the 4 higher order address bits during an external program memory access and provides a 4-bit bus for 8243 I/O expanders. 25 PROG Output strobe: active LOW for 8243 1/0 expanders. 1 To Test 0: input pin which can be tested by the JTO and JNTO instructions. Clock: TO can be configured as a clock output using the ENTO CLK instruction. 39 1 Test 1: input pin which can be tested using the JT1 and JTN1 instructions. T1 can be configured as the timer/counter input using the STRT CNT instruction. 6 iNT Interrrupt: interrupt input pin which can initiate an interrupt if the external interrupt is enabled. Can also be tested using the JNI instruction. Interrupt is disabled during and after RESET. 4 RESET Reset: active LOW input used to initialize the microcontroller. During program verification, the address is latched by a 0— to —1 transition on RESET and the data at the addressed location is output on BUS (note 2). " ALE Address latch enable: occurs each cycle and is useful as a clock output. During an external program or data memory access, ALE is used to latch the address information multiplexed on the DBO to DB7 outputs.

8 RD Read BUS: active LOW strobe used to gate data on to BUS lines when

reading from an external source.

10 WR Write BUS: active LOW strobe used to write data from BUS lines to an

external designation.

7 EA External access input: when HIGH, all instruction fetches are from

external memory.

9 PSEN Program store enable: active LOW strobe that occurs only during a fetch

from external memory. 5 ss Single step: active LOW input used with ALE to cause the microcontroller to execute a single instruction.

2 XTAL1 Crystal inputs: inputs for a crystal, LC-network or an external timing

3 XTAL2 signal to determine the internal oscillator frequency (note 2). 20 Vss Ground: circuit earth potential. 40 Voc Power supply: + 5 V main power supply pin.

26 Vpb Power supply: + 5 V RAM standby power supply; low power

2.32 August 1990 (CO

Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL Notes 1. Each port line can be individually configured as an input or an output. A line is designated as an input by first writing a logic 1 to the line. RESET sets all port lines to logic 1. 2. Non-standard TTL Vjy. FUNCTIONAL DESCRIPTION The following sections provide a detailed functional description of the MABBOXXH microcontroller as shown in Fig. 1. The generic term “MABBOXXH" is used to refer collectively to the MABBO48H/35HL, MABB049H/39HL and MAB8050H/40HL. Program memory (see Fig. 3) The on-chip program memory consists of 1024, 2048 or 4096 bytes of mask programmed ROM (MAB8048H/49H/50H); the MABBO35HL/39HL/40HL versions do not have on-chip program memory. The total addressing capability is 4096 bytes. The program memory address space is divided into two 2048-byte banks MBO and MB1. These two 2048 byte banks are each divided into 8 pages of 256 bytes for conditional branches, There are three locations in program memory of special interest. These are: © Location 0 — contains the first instruction to be executed after a RESET © Location 3 — contains the first instruction of an external interrupt routine ® Location 7 — contains the first instruction of a timer/counter interrupt routine wassoson/4omL 255 7 sen fae User mau | wansossn/ssne of NADBOSON/AOKL ggg +e _ | i, 31 2ows seumes san weapeoson/aen 2048 Fett meo gins | ay ° 8x8 Wiens | wassorowasm 1224 oo on 291g teven throes pines

7 STACK Rt oe RO

e tocation 7: A 168 é vector progr hare 7 7 5 eank o | 3 lesion mccisrens | seat 1 location 0: 1 Ri j

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Fig. 3 Program memory map. Fig. 4 Data memory map. {august 1990 2-33

FUNCTIONAL DESCRIPTION (continued) Data memory (see Fig. 4) The on-chip data memory consists of a 64, 128 or 256 byte RAM. All locations are indirectly addressable using two RAM pointer registers RO, R1 or RO’, R1’. The first 8 RAM locations (0 to 7) are designated as working register bank 0 and are directly addressable, By selecting register bank 1, RAM locations 24 to 31 become the working registers. RAM locations 8 to 23 are designated as the stack. Two bytes are used per CALL allowing up to 8 levels of subroutine nesting. An extra 256 bytes of RAM may be added and addressed directly using the MOVX instructions. If more RAM is required, 1/O port lines may be used to select additional (256 byte) banks of external memory. Program counter and stack The program counter (PC) is a 12-bit counter/register that points to the location from which the next instruction is to be fetched. When EA is logic 0 the PC can address locations 0 to 1023 (8048H), 2047 (8049H) or 4095 (8050H) of internal program memory. At the 1 K (8048H), 2 K (8049H) boundary, an automatic switch-over to external memory occurs, When EA is logic 1 all fetches are from external program memory. The total address space is 4 K bytes. An interrupt or subroutine CALL causes the contents of the program counter to be stored in one of the 8 register pairs of the program counter stack. A 3-bit stack pointer which is part of the program status word (PSW) points to the relevant register pair. Data RAM locations 8 to 23 are available as stack registers and are used to store the program counter and 4 bits of the PSW register. The stack pointer, when initialized to 000, points to RAM locations 8 and 9. The first subroutine jump or interrupt results in the program counter contents being transferred to locations 8 an 9 of the RAM array. The stack pointer is then incremented by one to point to locations 10 and 11. Nesting of subroutines within subroutines can continue up to 8B times without overflowing the stack. If overflow does occur the deepest address stored (locations 8 and 9) will be overwritten and lost since the stack pointer overflows from 111 to 000. It also underflows from 000 to 111. The end of a subroutine, which is signalled by a return instruction (RET or RETR), causes the stack pointer to be decremented and the contents of the appropriate register pair to be transferred to the program counter. Oscillator and clock (see Figs 5, 6 and 7) The MAB80XXH has on-chip oscillator and clock driver circuitry. A crystal, LC-network or external timing signal (pulse generator) determinesthe oscillator frequency. The output of the oscillator is divided-by-three and is available at TO (pin 1) by executing the ENTO CLK instruction. This clock signal (CLK) is divided-by-five to define a machine (instruction) cycle. It is available at ALE (pin 11). 1510250) crac XTAL2 1810 26 F (1) 7297120.1 (1) Including crystal-socket stray capacities. Fig. 5 Crystal oscillator mode. Crystal series impedance should be < 75 2 at 6 MHz and < 180 Q at 3,6 MHz. When using a ceramic oscillator both capacitors should be 30 pF. 2-34 August 1990 (OO

Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL sv (| |s709 Db: xratt}, Fig. 6 External clock source. Both XTAL 1 and XTAL 2 L) should be driven, Resistors to Vc (+5 V) are required to x |] ensure Vj}4 = 3,8 V if TTL circuitry is used. 3 The minimum HIGH and LOW times are 45%. rzeer40.1 XTALI ¢ ? L c nom. f

1 C+3C, (wH) (pF) (MHz)

Hd preg = St pe © [raz], anc’ 2 52 3,2 reearse.s Fig. 7 LC oscillator. Each capacitor should be ~ 20 pF including stray capacitance Cpp ~ 5 to 10 pF (pin-to-pin capacitance). Timer/event counter An internal counter is available which can count either external events or machine cycles (+32). The machine cycles are divided-by-32 before they are applied to the input of the 8-bit counter. External events are applied directly to the input of the counter. The maximum clock rate is one third of the machine cycle frequency. The minimum positive duty cycle that can be detected is 0,2 times the cycle period. The counter can be configured to generate an interrupt to the processor when it overflows. Interrupt An interrupt may be generated by: © An external input INT (pin 6) or © A timer/counter overflow, when enabled. In either event, the processor completes execution of the present instruction and then calls the interrupt service routine. At the end of the interrupt service routine, a RETR instruction restores the machine to the state it was in prior to the interrupt. The external interrupt has priority over the timer/counter interrupt. Input/output The MABBOXXH has 27 1/0 lines arranged as three 8-bit ports and 3 ‘test’ inputs that can alter program sequences when tested by conditional jump instructions. Each port line can be individually configured as an input or output. | August 1990 2.35

FUNCTIONAL DESCRIPTION (continued) Ports 1 and 2 are both 8-bits wide and have identical characteristics. Data written to these ports is latched and remains unchanged until rewritten. In the input mode, these ports are non-latching; inputs must be present until read by an input instruction. Inputs are fully TTL compatible and outputs will drive one standard TTL load. Ports 1 and 2 are called quasi-bidirectional because they are not high impedance when configured as inputs, Each line is pulled up to + 5 V through a resistor (~ 50 2). This pull-up provides sufficient source current for a TTL HIGH level, yet can be pulled LOW by a standard TTL gate, thus allowing the pin to be used both as an input and an output. To provide fast switching times during a logic 0 - to - 1 transition, transistor TR 2 is switched on for one fifth of a machine cycle when a logic 1 is written to the line. When a logic 0 is written, transistor TR 1 overcomes the pull-up and provides TTL current sinking capability. Since the pull-down transistor is low impedance, a logic 1 must first be written to any line which is to used as an input. RESET initializes all lines to the high impedance logic 1 state. This structure allows input and output on the same pin. Individual port lines can be read and written using the ANL and ORL instructions. BUS (DBO—D87) BUS is a true bidirectional 8-bit port with associated input and output strobes. The BUS port can operate in three different modes: as a latched I/O port, as a bidirectional bus port, or in an expanded ‘system as a program memory address output port. If the bidirectional feature is not needed, BUS can serve as either a statically latched output port or non-latching input port. Input and output lines on this port cannot be mixed, The BUS port lines are either active HIGH, active LOW, or high impedance (floating). As a static port, data is written and latched using the OUTL instruction and input using the INS in instruction. The INS and OUTL instructions generate pulses on the corresponding RD and WR output strobe lines; however, in the static port mode they are generally not used. As a bidirectional port, the MOVX instructions are used to read and write the port. A write to the port generates a pulse on the WR output line and output data is valid at the trailing edge of WR. A read of the port generates a pulse on the RD output line and input data must be valid at the trailing edge of RD. The latched mode (INS, OUTL) is intended for use in the single-chip configuration, where BUS is not being used as an expanded port. OUTL and MOVX instructions can be mixed if required. However, when using a MOVX instruction a previously latched output will be lost and BUS will be left in the high impedance state. INS does not put the BUS in a high impedance state. Therefore, in order to read an external byte (and not the previously latched value) using an INS instruction, it is necessary to precede INS with a MOVX instruction. OUTL should never be used in a system with external program memory, since latching BUS may cause the next instruction to be incorrectly fetched. striction) +sv +5v N.B- The OUTL, ANL and the ORL <| instructions relating to []-soen BUS are for use with internal program memory only. internat > al TR2 es 5 ne = sol 8 179 pon tine a = 300 | (Per 1 and 2) oe] | ra] ® pulse o § suEFER tn 72647372 Fig, 8 Quasi-bidirectional port structure. 2:36 August 1990

Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL Test (TO, T1) and INT These three pins serve as inputs and may be tested by the conditional jump instruction. They allow inputs to cause program branches without the necessity of loading an input port into the accumulator. RESET (see Fig. 9) This active LOW input is used to initialize the microcontroller. This Schmitt-trigger input has an internal pull-up resistor which, in combination with an external 1 uF capacitor, provides an internal reset pulse of sufficient duration to reset all circuitry. If the reset pulse is generated externally, the reset pin must be held at ground (0,45 V) for at least 10 ms after the power supply is within tolerance. Only 5 machine cycles (12,5 us at 6 MHz) are required if power is already on and the oscillator has stabilized. +5V 45V TTL one []z2° Lez? AEST | 1k RESET] BD: ron fF active adv (a) (b) Fig. 9 An external reset is shown in (a) and power-on reset in (b). Single step (SS) This active LOW input when used in combination with ALE will cause the microcontroller to execute a single instruction, then wait until SS is reactivated. Power-down mode (see Fig. 10) In the MAB8OXXH, power can be removed from all but the data RAM array, for low power standby operation. In the power-down mode the contents of the data RAM can be maintained while drawing typically 10% to 15% of the normal operating supply voltage. Vgc serves as the + 5 V supply pin for the bulk of the circuitry, while the Vpp pin supplies only the RAM array. In normal operation, both pins are at +5 V. In the standby mode, Vcc is at ground and only Vip is maintained at +5 V. Applying RESET to the microcontroller through the reset pin inhibits any access to the RAM and ensures that the RAM cannot be inadvertently altered as power is removed from Vcc. POWER procesor SUPPLY farptd / 1 ! POWER tot SUPPLY tt t i sequence follows —_ 1 RESET ! 1 | ---- | 1 a a) dansave acct 0 routine, data RAM executed ‘inibited 7204728.1 Fig. 10 Power down sequence. | { August 1990 2.37

FUNCTIONAL DESCRIPTION (continued) Instruction set (see Tables 1, 2, 3 and 4) The MAB80XXH instruction set consists of over 90 one and two-byte instructions, Program code efficiency is high because: ‘© Working registers and program variables are stored in RAM locations 0 to 127, which require only a single byte to address ‘© Program memory is divided into pages of 256 bytes, which means that branch destination addresses require only one byte The instruction set performs logical, arithmetic and test operations on bytes. It also manipulates and tests bits. A set of MOVE instructions operate indirectly on either RAM or ROM, which permits efficient access of pointers and data tables. The indirect jump instruction performs a multi-way branch (up to 256) on the contents of the accumulator to addresses stored in a look-up table. The ‘decrement register and jump if not zero’ instruction saves a byte each time it is used as opposed to using separate increment and test instructions. The on-chip counter provides the facility for external events or time to be counted by hardware which does not interfere with the main program. The MAB80XXH can either test the counter (under program control) or cause its overflow to generate an interrupt. These features are essential for real-time applications. Table 1 Symbols and definitions used in Table 2. A accumulator addr | program memory address Bb bit designation (b = 0-7) RBS register bank select c carry (bit CY) CNT event counter D mnemonic for 4-bit digit (nibble) data 8-bit number or expression 1 interrupt MB memory bank MBFF memory bank flip-flop Pp mnemonic for ‘in-page’ operation PC | program counter Pp port designation (p = 0, 1, 2) PSW program status word RB register bank Rr register designation (r = 0-7) Sn | serial 1/0 register sP | stack pointer T | timer TF timer flag TO test O input 11 test 1 input # immediate data prefix @ indirect address prefix (x) contents of X (x) contents of location addressed by X ba is replaced by - is exchanged with 2:38 August 1990 {

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Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL DC CHARACTERISTICS (MAB8048H/35HL; MAB8049H/39HL; MAB8050H/40HL) Voc = Vpp = 5 V (+ 10%); Vgg = 0 V; Tamb = 0 to + 70 °C; all voltages with respect to Vgg unless otherwise specified [mene YoYo me Do Supply current at Vpp =5 V # 10%; Vgg = Voc = 0 V MAB8048H/35HL 'pb - - 6 mA MAB8049H/39HL Ipp - - |8 mA MAB8050H/40HL lop - - | 8 mA Supply current (total) at Vpp = Vcc = 5 V + 10%; Vsg = OV MAB8048H/35HL Ippt+lec | - - 80 | mA MAB8049H/39HL lIppttee |- - | 90 |ma MABB050H/40HL Ipptlec | - — | 100 |ma Inputs | Input voltage LOW all inputs except | XTAL 1, XTAL 2, RESET auTe -05 |- | 08 |v Input voltage LOW } | XTAL 1, XTAL 2, RESET Vint -05 |- | 06 |v Input voltage HIGH all inputs except XTAL 1, XTAL 2, RESET Vin 2,0 - Vee | V Input voltage HIGH XTAL 1, XTAL 2, RESET Vint 38 - Vee |v Outputs | Output voltage LOW (DBO to DB7) i | at lol =2mA Vou - - 045 | Vv Output voltage LOW (RD, WR, PSEN, ALE) at lou = 1.8mA Vout - - 045 |v Output voltage LOW (PROG) | | | atlot2=1mA | VoL2 - - 045 |v Output voltage LOW (all other outputs) at loLg = 1,6 mA Vous - - 045 |v Output voltage HIGH (DBO to DB7) i at —IoH = 400 pA Vou 24 - - v Output voltage HIGH (RD, WR, PSEN, ALE) at —IQH1 = 100 pA Vout 24 - - v Output voltage HIGH (all other outputs) at Io = 40 uA Vou2 2,4 - - v August 1990 2-49

DC CHARACTERISTICS (continued) [pment mJm Jo Input leakage current (T1, INT) at Vgg < V1 < Vcc SUL 10 BA Output leakage current (DBO to DB7, TO; high impedance) at Vgg + 0,45 V< V) < Voc tloz 10 HA Input load current _ (P1.0 to P1.7, P2.0 to P2.7, EA, SS) at Vgg + 0,45 V<V) < Vcc lu 500 HA Input load current (RESET) at Vgg < Vi < Voc tut 300 HA DC CHARACTERISTICS MAF8048H/35HL; MAF8049H/39HL; MAF8050H/40HL {at Tamb = —40 to + 85 °C) MAFB0A48H/A35HL; MAF80A49H/A39HL; MAFSOASOH/A4OHL (at Tamb = —40 to + 110 °C) Voc = Vpp =5 V (+ 10%); Vgs = 0 V; Tamb as above; all voltages with respect to Vgg unless otherwise specified ee Ce eo Supply current at Vpp =5 V # 10%; Vgg = Voc =O V MAF8048H/35HL; MAF80A48H/A35HL_ | Ipp 8 mA MAF8049H/39HL; MAF80A49H/A39HL | Ipp 10 mA MAF8050H/40HL; MAF80A50H/A40HL = | Ippo 18 mA Supply current (total) at Vpp = Voc = 5 V + 10%; Vgg = OV MAF8048H/35HL; MAF80A48H/A35HL | Ipp +!cc 90 mA MAF8049H/39HL; MAF80A49H/A39HL._ | Ipp +!cc 100 mA MAF8050H/40HL; MAF80A50H/A40HL | Ipp + !cc 120 mA Inputs Input voltage HIGH all inputs except XTAL 1, XTAL 2, RESET Vin Veo | V Input load current _ (P1.0 to P1.7, P2.0 to P2.7, EA, SS) at Vgg + 0,45 V<V) < Voc uy 06 mA 2-50 August 1990 {

Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL AC CHARACTERISTICS (MAB8048H/35HL; MAB8049H/39HL; MAB8050H/40HL) Voc = Vpp =5 V (+ 10%); Vgg = 0 V; Tamb = 0 to + 70 °C; note 1. See waveforms Figs 14, 15, 16, 17 and 18 parameter symbol | flteL) [aimee | unit (note 2) win [max._| Clock period (note 2) tet WiytaL) 90,9 | 1000 | ns ALE pulse duration tLL 3,5t¢_-170 150 | — ns Address set-up time to ALE (note 3) | tay. 2teL—-110 7 | - ns ‘Address hold time after ALE tLa tcL—40 50 | - ns Control pulse duration RD, WR tec1 7,5tc,-200 | 480 | — | ns Control pulse duration PSEN tec2 6tcL-200 | 350 | - | ns Data set-up time before WR tow 6,5tc,-200 390 | - | ns Data set-up time after WR two tcL—50 40 - j ns Data hold time | RD, PSEN tor 1,5t¢_-30 0 110 | ns RD to data input tRDI 6tcL—-170 - 350 | ns PSEN to data input trp2 4,5tc_—170 - 190 | ns Address set-up time to WR. taw Stc_—150 300 | - ns Address set-up time to data | | input (RD) tap1 10,5tc,-220 - | 730 | ns Address set-up time to data | | | input (PSEN) tap2 7,5tc.-200. | - 460 | ns Address floating to RD, WR tarct 2teL-40 40 | - ns Address floating to PSEN (note 3) taFC2 0,5tc.—40 10 - ns ALE to control pulse RD, WR trarc1 | 3tcL-75 200 | - ns ALE to contro! pulse PSEN. trarc2 | 15tc_-75 60 - ns Control pulse to ALE | RD, WR, PROG teat teL—40 50 | - ns Control pulse to ALE | PSEN tca2 4tc—40 320 | - ns Port control set-up to PROG top 1,5tc¢_-80 50 - ns Port control hold to PROG tec 4tcL-260 100 | — ns PROG to Port 2 input must be valid | tpR 8,5tc,-120 - 650 | ns Input data hold time from PROG tpr 1,5tcL 0 150 ns Output data set-up time top 6tc_—290 250 140 ns Output data hold time tep 1,5t¢_-90 40. | - ns PROG pulse duration tpp 10,5t¢_—250 700 | - ns Port 2 1/O data set-up time toALE | tp, 4tcL-200 160 | — ns Port 2 1/0 data hold time to ALE tLp 1,5t¢_—120 15 - ns ) { August 1990 251

AC CHARACTERISTICS (continued) parameter wymbel| fu) [wre] ont woe [in Toe | Port output from ALE tpy 4,5tc_+100 - 510 ns TO repetition rate toprR | 3tcL 270 | — ns Cycle time tcy 15/fXTAL 1,36 | 15 bs MAF8048H/35HL; MAF8049H/39HL; MAF8050H/40HL Clock period (note 2) te. WfXTAL) 90,8 | 1000 ns Notes to AC characteristics 1. Control outputs: C_ = 80 pF. Bus outputs: CL = 150 pF. 2. f(teL) assumes 50% duty cycle on XTAL 1 and XTAL 2; minimum frequency = 1 MHz. 3. Bus high-impedance load: 20 pF. 20v 20v 24V o4sy ov ogy test points y297119 A.C. testing inputs are driven at 2,4 V for a logic 1 and 0,45 V for a logic 0. Output timing measurements are taken 2,0 V for a logic 1 and 0,8 V for a logic 0. Fig. 13 A.C. testing input, output waveform. tLaFci-> ALE +—— cer r—tcat beoy Te tROI | 7287393 ap) + Fig. 14 Read from external data memory. 2-52 August 1990 | {

Single-chip 8-bit microcontroller MAB8049H/39HL MAB8050H/40HL ‘LaFci ~ Ate Wa + two > i tow-! | taw ——— 7207384 Fig. 15 Write to external memory. toy =— ttt ——+, ALE — +! 'ca2 FEN [tba torn tal le oR Fig. 16 Instruction fetch from program memory. ALE TCAle ie tee taL ‘La ——+ a tro to! 1 top EXPANDER a Cone CE CS Ce) ourPuT | | | "T EXPANDER a CC) CEI CE INPUT oa! top PROG 72073959 Fig 17 Port 2 timing. ) { August 1990 2.53

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Product Information

SCN8039H specifications and overview.

Summary

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Description

SINGLE-CHIP 8-BIT MICROCONTROLLER August 1990

Source title SCN8039H Datasheet(PDF) - NXP Semiconductors

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